diff options
194 files changed, 42661 insertions, 678 deletions
diff --git a/AUTHORS.txt b/AUTHORS.txt index 2c147e4..0db2323 100644 --- a/AUTHORS.txt +++ b/AUTHORS.txt @@ -1,18 +1,21 @@ -Joel Bodenmann aka Tectu -https://github.com/Tectu -Git repository maintainer - -Uladzimir Pylinsky aka barthess -https://github.com/barthess -Git repository maintainer - -Marco Veeneman aka Marco -https://github.com/marcoveeneman -Maintainer of the ChibiOS port for the Texas Instruments -Tiva C Series Microcontrollers - -Fabien Poussin aka fpoussin -https://github.com/fpoussin - -Matthias Blaicher aka mabl -https://github.com/mabl +Joel Bodenmann aka Tectu
+https://github.com/Tectu
+Git repository maintainer
+
+Uladzimir Pylinsky aka barthess
+https://github.com/barthess
+Git repository maintainer
+
+Marco Veeneman aka Marco
+https://github.com/marcoveeneman
+Maintainer of the ChibiOS port for the Texas Instruments
+Tiva C Series Microcontrollers
+
+Fabien Poussin aka fpoussin
+https://github.com/fpoussin
+
+Matthias Blaicher aka mabl
+https://github.com/mabl
+
+Andrea Zoppi aka TexZK
+https://github.com/TexZK
@@ -6,4 +6,3 @@ notes in file headers. Code is maintained via Github https://github.com/ChibiOS/ChibiOS-Contrib Feel free to send pull request there. - diff --git a/demos/NRF51/RT-WVSHARE_BLE400/Makefile b/demos/NRF51/RT-WVSHARE_BLE400/Makefile new file mode 100644 index 0000000..c6b59cf --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/Makefile @@ -0,0 +1,210 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+# Startup files.
+include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/NRF51/NRF51822/platform.mk
+include $(CHIBIOS)/community/os/hal/boards/WVSHARE_BLE400/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/NRF51822.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/NRF51/RT-WVSHARE_BLE400/chconf.h b/demos/NRF51/RT-WVSHARE_BLE400/chconf.h new file mode 100644 index 0000000..fc9a52b --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/chconf.h @@ -0,0 +1,499 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/NRF51/RT-WVSHARE_BLE400/debug/openocd.cfg b/demos/NRF51/RT-WVSHARE_BLE400/debug/openocd.cfg new file mode 100644 index 0000000..078915a --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/debug/openocd.cfg @@ -0,0 +1,6 @@ +source [find interface/stlink-v2.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x4000 +source [find target/nrf51.cfg] diff --git a/demos/NRF51/RT-WVSHARE_BLE400/halconf.h b/demos/NRF51/RT-WVSHARE_BLE400/halconf.h new file mode 100644 index 0000000..fa27306 --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/halconf.h @@ -0,0 +1,327 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/NRF51/RT-WVSHARE_BLE400/main.c b/demos/NRF51/RT-WVSHARE_BLE400/main.c new file mode 100644 index 0000000..4f5e49d --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/main.c @@ -0,0 +1,70 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+static THD_WORKING_AREA(waThread1, 64);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ uint8_t led = LED0;
+ chRegSetThreadName("Blinker");
+ while (1) {
+ palSetPad(IOPORT1, led);
+ chThdSleepMilliseconds(100);
+ palClearPad(IOPORT1, led);
+ if (++led > LED4) led = LED0;
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ SerialConfig serial_config = {
+ .speed = 38400,
+ .tx_pin = UART_TX,
+ .rx_pin = UART_RX,
+ };
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates UART0 using the driver default configuration.
+ */
+ sdStart(&SD1, &serial_config);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ TestThread(&SD1);
+ while (1) {
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/NRF51/RT-WVSHARE_BLE400/mcuconf.h b/demos/NRF51/RT-WVSHARE_BLE400/mcuconf.h new file mode 100644 index 0000000..aaf9473 --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/mcuconf.h @@ -0,0 +1,25 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * HAL driver system settings.
+ */
+#define NRF51_SERIAL_USE_UART0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/demos/NRF51/RT-WVSHARE_BLE400/readme.txt b/demos/NRF51/RT-WVSHARE_BLE400/readme.txt new file mode 100644 index 0000000..3ac2704 --- /dev/null +++ b/demos/NRF51/RT-WVSHARE_BLE400/readme.txt @@ -0,0 +1,18 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M0 WvShare BLE400 (nRF51822). **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an WvShare BLE400 board. This board is powered by a Nordic
+Semiconductor nRF51822 processor which is an ARM Cortex-M0 with bluetooth radio
+hardware. This board can be easily found on chinese websites.
+
+** The Demo **
+
+This demo will print the standard TestThread output and blink all LEDs in a
+sequential.
+
+** Build Procedure **
+
+The demo has been tested using the freely available GCC ARM Embedded toolchain.
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject new file mode 100644 index 0000000..ddfa092 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject @@ -0,0 +1,58 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore new file mode 100644 index 0000000..060dd31 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore @@ -0,0 +1,2 @@ +build/
+.dep/
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project new file mode 100644 index 0000000..8f3403e --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project @@ -0,0 +1,90 @@ +<?xml version="1.0" encoding="UTF-8"?>
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+ <name>RT-STM32F429-DISCOVERY-DMA2D</name>
+ <comment></comment>
+ <projects>
+ </projects>
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+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
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+ <key>?name?</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildArguments</key>
+ <value>-j1</value>
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+ <value>make</value>
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+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>true</value>
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+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile new file mode 100644 index 0000000..4e53d19 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile @@ -0,0 +1,227 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/community/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT = STM32F429xI_SDRAM.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/community/os/various/devices_lib/lcd/ili9341.c \
+ ./main.c \
+ ./wolf3d_palette.c \
+ ./res/wolf3d_vgagraph_chunk87.c \
+ # eol
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various \
+ $(CHIBIOS)/os/hal/lib/streams \
+ $(CHIBIOS)/community/os/various/devices_lib/lcd \
+ ./res \
+ # eol
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/STM32F429xI_SDRAM.ld b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/STM32F429xI_SDRAM.ld new file mode 100644 index 0000000..1fb424a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/STM32F429xI_SDRAM.ld @@ -0,0 +1,54 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * ST32F429xI memory setup.
+ * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 2M
+ ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
+ ram1 : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20020000, len = 64k /* SRAM3 */
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0xD0000000, len = 8M /* SDRAM */
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for SDRAM segment.*/
+REGION_ALIAS("SDRAM_RAM", ram7);
+
+INCLUDE rules.ld
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h new file mode 100644 index 0000000..48ada74 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h @@ -0,0 +1,499 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS TRUE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..a7d2f61 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
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+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch new file mode 100644 index 0000000..93158b9 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType"> +<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/> +<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/> +<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F429-DISCOVERY-DMA2D"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/RT-STM32F429-DISCOVERY-DMA2D"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/> +</listAttribute> +</launchConfiguration> diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h new file mode 100644 index 0000000..a0b3a2e --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h @@ -0,0 +1,340 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI TRUE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Community drivers' includes */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h new file mode 100644 index 0000000..44e89df --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c new file mode 100644 index 0000000..d0b07d3 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -0,0 +1,670 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "chprintf.h"
+#include "shell.h"
+#if HAL_USE_SERIAL_USB
+#include "usbcfg.h"
+#endif
+
+#include "fsmc_sdram.h"
+#include "ili9341.h"
+#include "stm32_ltdc.h"
+#include "stm32_dma2d.h"
+
+#include "res/wolf3d_vgagraph_chunk87.h"
+
+/*===========================================================================*/
+/* SDRAM related. */
+/*===========================================================================*/
+
+// TODO: Move constants below elsewhere, and normalize their name
+
+/* SDRAM bank base address.*/
+#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
+
+/*
+ * FMC SDRAM Mode definition register defines
+ */
+#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
+/*
+ * FMC_ReadPipe_Delay
+ */
+#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
+
+/*
+ * FMC_Read_Burst
+ */
+#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
+
+/*
+ * FMC_SDClock_Period
+ */
+#define FMC_SDClock_Disable ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
+#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
+
+/*
+ * FMC_ColumnBits_Number
+ */
+#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
+
+/*
+ * FMC_RowBits_Number
+ */
+#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
+
+/*
+ * FMC_SDMemory_Data_Width
+ */
+#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
+
+/*
+ * FMC_InternalBank_Number
+ */
+#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
+
+/*
+ * FMC_CAS_Latency
+ */
+#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
+
+/*
+ * FMC_Write_Protection
+ */
+#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
+
+/*
+ * SDRAM driver configuration structure.
+ */
+static const SDRAMConfig sdram_cfg = {
+ .sdcr = (uint32_t)(FMC_ColumnBits_Number_8b |
+ FMC_RowBits_Number_12b |
+ FMC_SDMemory_Width_16b |
+ FMC_InternalBank_Number_4 |
+ FMC_CAS_Latency_3 |
+ FMC_Write_Protection_Disable |
+ FMC_SDClock_Period_2 |
+ FMC_Read_Burst_Disable |
+ FMC_ReadPipe_Delay_1),
+
+ .sdtr = (uint32_t)((2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
+ (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
+ (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
+ (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
+ (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
+ (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
+ (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
+
+ .sdcmr = (uint32_t)(((4 - 1) << 5) |
+ ((FMC_SDCMR_MRD_BURST_LENGTH_2 |
+ FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
+ FMC_SDCMR_MRD_CAS_LATENCY_3 |
+ FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
+ FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
+
+ /* if (STM32_SYSCLK == 180000000) ->
+ 64ms / 4096 = 15.625us
+ 15.625us * 90MHz = 1406 - 20 = 1386 */
+ //.sdrtr = (1386 << 1),
+ .sdrtr = (uint32_t)(683 << 1),
+};
+
+/* SDRAM size, in bytes.*/
+#define IS42S16400J_SIZE (8 * 1024 * 1024)
+
+/*
+ * Erases the whole SDRAM bank.
+ */
+static void sdram_bulk_erase(void) {
+
+ volatile uint8_t *p = (volatile uint8_t *)SDRAM_BANK_ADDR;
+ volatile uint8_t *end = p + IS42S16400J_SIZE;
+ while (p < end)
+ *p++ = 0;
+}
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker1");
+ while (true) {
+ palClearPad(GPIOG, GPIOG_LED4_RED);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOG, GPIOG_LED4_RED);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+/*
+ * Green LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread2, 128);
+static THD_FUNCTION(Thread2, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker2");
+ while (true) {
+ palClearPad(GPIOG, GPIOG_LED3_GREEN);
+ chThdSleepMilliseconds(250);
+ palSetPad(GPIOG, GPIOG_LED3_GREEN);
+ chThdSleepMilliseconds(250);
+ }
+}
+
+/*===========================================================================*/
+/* LTDC related. */
+/*===========================================================================*/
+
+static uint8_t frame_buffer[240 * 320 * 3] __attribute__((section(".ram7")));
+
+static uint8_t view_buffer[240 * 320];
+
+extern const ltdc_color_t wolf3d_palette[256];
+
+static const ltdc_window_t ltdc_fullscreen_wincfg = {
+ 0,
+ 240 - 1,
+ 0,
+ 320 - 1,
+};
+
+static const ltdc_frame_t ltdc_view_frmcfg1 = {
+ view_buffer,
+ 240,
+ 320,
+ 240 * sizeof(uint8_t),
+ LTDC_FMT_L8,
+};
+
+static const ltdc_laycfg_t ltdc_view_laycfg1 = {
+ <dc_view_frmcfg1,
+ <dc_fullscreen_wincfg,
+ LTDC_COLOR_FUCHSIA,
+ 0xFF,
+ 0x980088,
+ wolf3d_palette,
+ 256,
+ LTDC_BLEND_FIX1_FIX2,
+ (LTDC_LEF_ENABLE | LTDC_LEF_PALETTE),
+};
+
+static const ltdc_frame_t ltdc_screen_frmcfg1 = {
+ frame_buffer,
+ 240,
+ 320,
+ 240 * 3,
+ LTDC_FMT_RGB888,
+};
+
+static const ltdc_laycfg_t ltdc_screen_laycfg1 = {
+ <dc_screen_frmcfg1,
+ <dc_fullscreen_wincfg,
+ LTDC_COLOR_FUCHSIA,
+ 0xFF,
+ 0x980088,
+ NULL,
+ 0,
+ LTDC_BLEND_FIX1_FIX2,
+ LTDC_LEF_ENABLE,
+};
+
+static const LTDCConfig ltdc_cfg = {
+ /* Display specifications.*/
+ 240, /**< Screen pixel width.*/
+ 320, /**< Screen pixel height.*/
+ 10, /**< Horizontal sync pixel width.*/
+ 2, /**< Vertical sync pixel height.*/
+ 20, /**< Horizontal back porch pixel width.*/
+ 2, /**< Vertical back porch pixel height.*/
+ 10, /**< Horizontal front porch pixel width.*/
+ 4, /**< Vertical front porch pixel height.*/
+ 0, /**< Driver configuration flags.*/
+
+ /* ISR callbacks.*/
+ NULL, /**< Line Interrupt ISR, or @p NULL.*/
+ NULL, /**< Register Reload ISR, or @p NULL.*/
+ NULL, /**< FIFO Underrun ISR, or @p NULL.*/
+ NULL, /**< Transfer Error ISR, or @p NULL.*/
+
+ /* Color and layer settings.*/
+ LTDC_COLOR_TEAL,
+ <dc_view_laycfg1,
+ NULL,
+};
+
+extern LTDCDriver LTDCD1;
+
+const SPIConfig spi_cfg5 = {
+ NULL,
+ GPIOC,
+ GPIOC_SPI5_LCD_CS,
+ (((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
+};
+
+extern SPIDriver SPID5;
+
+const ILI9341Config ili9341_cfg = {
+ &SPID5,
+ GPIOD,
+ GPIOD_LCD_WRX
+};
+
+static void initialize_lcd(void) {
+
+ static const uint8_t pgamma[15] = {
+ 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
+ 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00
+ };
+ static const uint8_t ngamma[15] = {
+ 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
+ 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F
+ };
+
+ ILI9341Driver *const lcdp = &ILI9341D1;
+
+ /* XOR-checkerboard texture.*/
+ unsigned x, y;
+ for (y = 0; y < 320; ++y)
+ for (x = 0; x < 240; ++x)
+ view_buffer[y * 240 + x] = (uint8_t)(x ^ y);
+
+ ili9341AcquireBus(lcdp);
+ ili9341Select(lcdp);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FRAME_CTL_NORMAL);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x1B);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
+ ili9341WriteByte(lcdp, 0x0A);
+ ili9341WriteByte(lcdp, 0xA2);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_1);
+ ili9341WriteByte(lcdp, 0x10);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_2);
+ ili9341WriteByte(lcdp, 0x10);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_1);
+ ili9341WriteByte(lcdp, 0x45);
+ ili9341WriteByte(lcdp, 0x15);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_2);
+ ili9341WriteByte(lcdp, 0x90);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_MEM_ACS_CTL);
+ ili9341WriteByte(lcdp, 0xC8);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_RGB_IF_SIG_CTL);
+ ili9341WriteByte(lcdp, 0xC2);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
+ ili9341WriteByte(lcdp, 0x0A);
+ ili9341WriteByte(lcdp, 0xA7);
+ ili9341WriteByte(lcdp, 0x27);
+ ili9341WriteByte(lcdp, 0x04);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_COL_ADDR);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0xEF);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_PAGE_ADDR);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x01);
+ ili9341WriteByte(lcdp, 0x3F);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_IF_CTL);
+ ili9341WriteByte(lcdp, 0x01);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x06);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_GAMMA);
+ ili9341WriteByte(lcdp, 0x01);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_PGAMMA);
+ ili9341WriteChunk(lcdp, pgamma, 15);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_NGAMMA);
+ ili9341WriteChunk(lcdp, ngamma, 15);
+
+ ili9341WriteCommand(lcdp, ILI9341_CMD_SLEEP_OFF);
+ chThdSleepMilliseconds(10);
+
+ ili9341WriteCommand(lcdp, ILI9341_CMD_DISPLAY_ON);
+ ili9341WriteCommand(lcdp, ILI9341_SET_MEM);
+ chThdSleepMilliseconds(10);
+
+ ili9341Unselect(lcdp);
+ ili9341ReleaseBus(lcdp);
+}
+
+static const DMA2DConfig dma2d_cfg = {
+ /* ISR callbacks.*/
+ NULL, /**< Configuration error, or @p NULL.*/
+ NULL, /**< Palette transfer done, or @p NULL.*/
+ NULL, /**< Palette access error, or @p NULL.*/
+ NULL, /**< Transfer watermark, or @p NULL.*/
+ NULL, /**< Transfer complete, or @p NULL.*/
+ NULL /**< Transfer error, or @p NULL.*/
+};
+
+static const dma2d_palcfg_t dma2d_palcfg = {
+ wolf3d_palette,
+ 256,
+ DMA2D_FMT_ARGB8888
+};
+
+static const dma2d_laycfg_t dma2d_bg_laycfg = {
+ view_buffer,
+ 0,
+ DMA2D_FMT_L8,
+ DMA2D_COLOR_RED,
+ 0xFF,
+ &dma2d_palcfg
+};
+
+static const dma2d_laycfg_t dma2d_fg_laycfg = {
+ (void *)wolf3d_vgagraph_chunk87,
+ 0,
+ DMA2D_FMT_L8,
+ DMA2D_COLOR_LIME,
+ 0xFF,
+ &dma2d_palcfg
+};
+
+static const dma2d_laycfg_t dma2d_frame_laycfg = {
+ frame_buffer,
+ 0,
+ DMA2D_FMT_RGB888,
+ DMA2D_COLOR_BLUE,
+ 0xFF,
+ NULL
+};
+
+static void dma2d_test(void) {
+
+ DMA2DDriver *const dma2dp = &DMA2DD1;
+ LTDCDriver *const ltdcp = <DCD1;
+
+ chThdSleepSeconds(1);
+
+ ltdcBgSetConfig(ltdcp, <dc_screen_laycfg1);
+ ltdcReload(ltdcp, TRUE);
+
+ dma2dAcquireBus(dma2dp);
+
+ /* Target the frame buffer by default.*/
+ dma2dBgSetConfig(dma2dp, &dma2d_frame_laycfg);
+ dma2dFgSetConfig(dma2dp, &dma2d_frame_laycfg);
+ dma2dOutSetConfig(dma2dp, &dma2d_frame_laycfg);
+
+ /* Copy the background.*/
+ dma2dFgSetConfig(dma2dp, &dma2d_bg_laycfg);
+ dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
+ dma2dJobSetSize(dma2dp, 240, 320);
+ dma2dJobExecute(dma2dp);
+
+ /* Draw the splashscren picture at (8, 0).*/
+ dma2dFgSetConfig(dma2dp, &dma2d_fg_laycfg);
+ dma2dOutSetAddress(dma2dp, dma2dComputeAddress(
+ frame_buffer, ltdc_screen_frmcfg1.pitch, DMA2D_FMT_RGB888, 8, 0
+ ));
+ dma2dOutSetWrapOffset(dma2dp, ltdc_screen_frmcfg1.width - 200);
+ dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
+ dma2dJobSetSize(dma2dp, 200, 320);
+ dma2dJobExecute(dma2dp);
+
+ dma2dReleaseBus(dma2dp);
+}
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#if HAL_USE_SERIAL_USB
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+#endif
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
+
+static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
+ size_t n, size;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: mem\r\n");
+ return;
+ }
+ n = chHeapStatus(NULL, &size);
+ chprintf(chp, "core free memory : %u bytes\r\n", chCoreGetStatusX());
+ chprintf(chp, "heap fragments : %u\r\n", n);
+ chprintf(chp, "heap free total : %u bytes\r\n", size);
+}
+
+static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static const char *states[] = {CH_STATE_NAMES};
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: threads\r\n");
+ return;
+ }
+ chprintf(chp, " addr stack prio refs state time\r\n");
+ tp = chRegFirstThread();
+ do {
+ chprintf(chp, "%08lx %08lx %4lu %4lu %9s\r\n",
+ (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
+ (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
+ states[tp->p_state]);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+
+static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: test\r\n");
+ return;
+ }
+ tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
+ TestThread, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory\r\n");
+ return;
+ }
+ chThdWait(tp);
+}
+
+static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: reset\r\n");
+ return;
+ }
+
+ chprintf(chp, "Will reset in 200ms\r\n");
+ chThdSleepMilliseconds(200);
+ NVIC_SystemReset();
+}
+
+static const ShellCommand commands[] = {
+ {"mem", cmd_mem},
+ {"threads", cmd_threads},
+ {"test", cmd_test},
+ {"reset", cmd_reset},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+#if HAL_USE_SERIAL_USB
+ (BaseSequentialStream *)&SDU1,
+#else
+ (BaseSequentialStream *)&SD1,
+#endif
+ commands
+};
+
+/*===========================================================================*/
+/* Initialization and main thread. */
+/*===========================================================================*/
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ thread_t *shelltp = NULL;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+#if HAL_USE_SERIAL_USB
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1000);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+#else
+ /*
+ * Initializes serial port.
+ */
+ sdStart(&SD1, NULL);
+#endif /* HAL_USE_SERIAL_USB */
+
+ /*
+ * Initialise FSMC for SDRAM.
+ */
+ fsmcSdramInit();
+ fsmcSdramStart(&SDRAMD, &sdram_cfg);
+ sdram_bulk_erase();
+
+ /*
+ * Activates the LCD-related drivers.
+ */
+ spiStart(&SPID5, &spi_cfg5);
+ ili9341ObjectInit(&ILI9341D1);
+ ili9341Start(&ILI9341D1, &ili9341_cfg);
+ initialize_lcd();
+ ltdcInit();
+ ltdcStart(<DCD1, <dc_cfg);
+
+ /*
+ * Activates the DMA2D-related drivers.
+ */
+ dma2dInit();
+ dma2dStart(&DMA2DD1, &dma2d_cfg);
+ dma2d_test();
+
+ /*
+ * Creating the blinker threads.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1),
+ NORMALPRIO + 10, Thread1, NULL);
+ chThdCreateStatic(waThread2, sizeof(waThread2),
+ NORMALPRIO + 10, Thread2, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it just performs
+ * a shell respawn upon its termination.
+ */
+ while (true) {
+ if (!shelltp) {
+#if HAL_USE_SERIAL_USB
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ /* Spawns a new shell.*/
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ }
+#else
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+#endif
+ }
+ else {
+ /* If the previous shell exited.*/
+ if (chThdTerminatedX(shelltp)) {
+ /* Recovers memory of the previous shell.*/
+ chThdRelease(shelltp);
+ shelltp = NULL;
+ }
+ }
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h new file mode 100644 index 0000000..7aab0c4 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h @@ -0,0 +1,360 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+#define STM32_SAISRC STM32_SAISRC_PLL
+#define STM32_PLLSAIN_VALUE 192
+#define STM32_PLLSAIQ_VALUE 7
+#define STM32_PLLSAIR_VALUE 4
+#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 TRUE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 TRUE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * LTDC driver system settings.
+ */
+#define STM32_LTDC_USE_LTDC TRUE
+#define STM32_LTDC_EV_IRQ_PRIORITY 11
+#define STM32_LTDC_ER_IRQ_PRIORITY 11
+
+/*
+ * DMA2D driver system settings.
+ */
+#define STM32_DMA2D_USE_DMA2D TRUE
+#define STM32_DMA2D_IRQ_PRIORITY 11
+
+/*
+ * Header for community drivers.
+ */
+#include "mcuconf_community.h"
+
+#endif /* _MCUCONF_H_ */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h new file mode 100644 index 0000000..81c7e2c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt new file mode 100644 index 0000000..3342a4c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt @@ -0,0 +1,29 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M4 STM32F429. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an ST STM32F429I-Discovery board.
+
+** The Demo **
+
+A simple command shell is activated on virtual serial port SD1.
+The demo makes use of FMC, LTDC, and DMA2D peripherals to show graphical
+contents on the display of the board, composed both on the on-chip SRAM
+and the on-board SDRAM.
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO. just modify the TRGT line in the makefile in order to use
+different GCC toolchains.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin Binary files differnew file mode 100644 index 0000000..aee3942 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp Binary files differnew file mode 100644 index 0000000..c50e16b --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif Binary files differnew file mode 100644 index 0000000..4cb7105 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c new file mode 100644 index 0000000..6439a45 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c @@ -0,0 +1,4005 @@ +/* Generated by bin2c, do not edit manually */
+
+/* Contents of file chunk87.bin */
+const unsigned char wolf3d_vgagraph_chunk87[64000] = {
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+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h new file mode 100644 index 0000000..6c0a15f --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h @@ -0,0 +1,9 @@ +/* Generated by bin2c, do not edit manually */
+#ifndef __wolf3d_vgagraph_chunk87_h_included
+#define __wolf3d_vgagraph_chunk87_h_included
+
+/* Contents of file chunk87.bin */
+#define wolf3d_vgagraph_chunk87_size 64000
+extern const unsigned char wolf3d_vgagraph_chunk87[64000];
+
+#endif /* __wolf3d_vgagraph_chunk87_h_included */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c new file mode 100644 index 0000000..9f95a2a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c @@ -0,0 +1,314 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Endpoints to be used for USBD2.
+ */
+#define USBD2_DATA_REQUEST_EP 1
+#define USBD2_DATA_AVAILABLE_EP 1
+#define USBD2_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0483, /* idVendor (ST). */
+ 0x5740, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 3 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(38), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+ 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+ 'c', 0, 's', 0
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(56), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
+ 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
+ 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
+ 'o', 0, 'r', 0, 't', 0
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ NULL
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD2,
+ USBD2_DATA_REQUEST_EP,
+ USBD2_DATA_AVAILABLE_EP,
+ USBD2_INTERRUPT_REQUEST_EP
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h new file mode 100644 index 0000000..2ffaa17 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h @@ -0,0 +1,25 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c new file mode 100644 index 0000000..666cbcb --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c @@ -0,0 +1,277 @@ +#include <ch.h>
+#include <hal.h>
+#include <stm32_ltdc.h>
+
+const ltdc_color_t wolf3d_palette[256] __attribute__((aligned(4))) = {
+ 0xFF000000, /* 0x00 */
+ 0xFF0000A8, /* 0x01 */
+ 0xFF00A800, /* 0x02 */
+ 0xFF00A8A8, /* 0x03 */
+ 0xFFA80000, /* 0x04 */
+ 0xFFA800A8, /* 0x05 */
+ 0xFFA85400, /* 0x06 */
+ 0xFFA8A8A8, /* 0x07 */
+ 0xFF545454, /* 0x08 */
+ 0xFF5454FC, /* 0x09 */
+ 0xFF54FC54, /* 0x0A */
+ 0xFF54FCFC, /* 0x0B */
+ 0xFFFC5454, /* 0x0C */
+ 0xFFFC54FC, /* 0x0D */
+ 0xFFFCFC54, /* 0x0E */
+ 0xFFFCFCFC, /* 0x0F */
+ 0xFFECECEC, /* 0x10 */
+
+ 0xFFDCDCDC, /* 0x11 */
+ 0xFFD0D0D0, /* 0x12 */
+ 0xFFC0C0C0, /* 0x13 */
+ 0xFFB4B4B4, /* 0x14 */
+ 0xFFA8A8A8, /* 0x15 */
+ 0xFF989898, /* 0x16 */
+ 0xFF8C8C8C, /* 0x17 */
+ 0xFF7C7C7C, /* 0x18 */
+ 0xFF707070, /* 0x19 */
+ 0xFF646464, /* 0x1A */
+ 0xFF545454, /* 0x1B */
+ 0xFF484848, /* 0x1C */
+ 0xFF383838, /* 0x1D */
+ 0xFF2C2C2C, /* 0x1E */
+ 0xFF202020, /* 0x1F */
+ 0xFFFC0000, /* 0x20 */
+
+ 0xFFEC0000, /* 0x21 */
+ 0xFFE00000, /* 0x22 */
+ 0xFFD40000, /* 0x23 */
+ 0xFFC80000, /* 0x24 */
+ 0xFFBC0000, /* 0x25 */
+ 0xFFB00000, /* 0x26 */
+ 0xFFA40000, /* 0x27 */
+ 0xFF980000, /* 0x28 */
+ 0xFF880000, /* 0x29 */
+ 0xFF7C0000, /* 0x2A */
+ 0xFF700000, /* 0x2B */
+ 0xFF640000, /* 0x2C */
+ 0xFF580000, /* 0x2D */
+ 0xFF4C0000, /* 0x2E */
+ 0xFF400000, /* 0x2F */
+ 0xFFFCD8D8, /* 0x30 */
+
+ 0xFFFCB8B8, /* 0x31 */
+ 0xFFFC9C9C, /* 0x32 */
+ 0xFFFC7C7C, /* 0x33 */
+ 0xFFFC5C5C, /* 0x34 */
+ 0xFFFC4040, /* 0x35 */
+ 0xFFFC2020, /* 0x36 */
+ 0xFFFC0000, /* 0x37 */
+ 0xFFFCA85C, /* 0x38 */
+ 0xFFFC9840, /* 0x39 */
+ 0xFFFC8820, /* 0x3A */
+ 0xFFFC7800, /* 0x3B */
+ 0xFFE46C00, /* 0x3C */
+ 0xFFCC6000, /* 0x3D */
+ 0xFFB45400, /* 0x3E */
+ 0xFF9C4C00, /* 0x3F */
+ 0xFFFCFCD8, /* 0x40 */
+
+ 0xFFFCFCB8, /* 0x41 */
+ 0xFFFCFC9C, /* 0x42 */
+ 0xFFFCFC7C, /* 0x43 */
+ 0xFFFCF85C, /* 0x44 */
+ 0xFFFCF440, /* 0x45 */
+ 0xFFFCF420, /* 0x46 */
+ 0xFFFCF400, /* 0x47 */
+ 0xFFE4D800, /* 0x48 */
+ 0xFFCCC400, /* 0x49 */
+ 0xFFB4AC00, /* 0x4A */
+ 0xFF9C9C00, /* 0x4B */
+ 0xFF848400, /* 0x4C */
+ 0xFF706C00, /* 0x4D */
+ 0xFF585400, /* 0x4E */
+ 0xFF404000, /* 0x4F */
+ 0xFFD0FC5C, /* 0x50 */
+
+ 0xFFC4FC40, /* 0x51 */
+ 0xFFB4FC20, /* 0x52 */
+ 0xFFA0FC00, /* 0x53 */
+ 0xFF90E400, /* 0x54 */
+ 0xFF80CC00, /* 0x55 */
+ 0xFF74B400, /* 0x56 */
+ 0xFF609C00, /* 0x57 */
+ 0xFFD8FCD8, /* 0x58 */
+ 0xFFBCFCB8, /* 0x59 */
+ 0xFF9CFC9C, /* 0x5A */
+ 0xFF80FC7C, /* 0x5B */
+ 0xFF60FC5C, /* 0x5C */
+ 0xFF40FC40, /* 0x5D */
+ 0xFF20FC20, /* 0x5E */
+ 0xFF00FC00, /* 0x5F */
+ 0xFF00FC00, /* 0x60 */
+
+ 0xFF00EC00, /* 0x61 */
+ 0xFF00E000, /* 0x62 */
+ 0xFF00D400, /* 0x63 */
+ 0xFF04C800, /* 0x64 */
+ 0xFF04BC00, /* 0x65 */
+ 0xFF04B000, /* 0x66 */
+ 0xFF04A400, /* 0x67 */
+ 0xFF049800, /* 0x68 */
+ 0xFF048800, /* 0x69 */
+ 0xFF047C00, /* 0x6A */
+ 0xFF047000, /* 0x6B */
+ 0xFF046400, /* 0x6C */
+ 0xFF045800, /* 0x6D */
+ 0xFF044C00, /* 0x6E */
+ 0xFF044000, /* 0x6F */
+ 0xFFD8FCFC, /* 0x70 */
+
+ 0xFFB8FCFC, /* 0x71 */
+ 0xFF9CFCFC, /* 0x72 */
+ 0xFF7CFCF8, /* 0x73 */
+ 0xFF5CFCFC, /* 0x74 */
+ 0xFF40FCFC, /* 0x75 */
+ 0xFF20FCFC, /* 0x76 */
+ 0xFF00FCFC, /* 0x77 */
+ 0xFF00E4E4, /* 0x78 */
+ 0xFF00CCCC, /* 0x79 */
+ 0xFF00B4B4, /* 0x7A */
+ 0xFF009C9C, /* 0x7B */
+ 0xFF008484, /* 0x7C */
+ 0xFF007070, /* 0x7D */
+ 0xFF005858, /* 0x7E */
+ 0xFF004040, /* 0x7F */
+ 0xFF5CBCFC, /* 0x80 */
+
+ 0xFF40B0FC, /* 0x81 */
+ 0xFF20A8FC, /* 0x82 */
+ 0xFF009CFC, /* 0x83 */
+ 0xFF008CE4, /* 0x84 */
+ 0xFF007CCC, /* 0x85 */
+ 0xFF006CB4, /* 0x86 */
+ 0xFF005C9C, /* 0x87 */
+ 0xFFD8D8FC, /* 0x88 */
+ 0xFFB8BCFC, /* 0x89 */
+ 0xFF9C9CFC, /* 0x8A */
+ 0xFF7C80FC, /* 0x8B */
+ 0xFF5C60FC, /* 0x8C */
+ 0xFF4040FC, /* 0x8D */
+ 0xFF2024FC, /* 0x8E */
+ 0xFF0004FC, /* 0x8F */
+ 0xFF0000FC, /* 0x90 */
+
+ 0xFF0000EC, /* 0x91 */
+ 0xFF0000E0, /* 0x92 */
+ 0xFF0000D4, /* 0x93 */
+ 0xFF0000C8, /* 0x94 */
+ 0xFF0000BC, /* 0x95 */
+ 0xFF0000B0, /* 0x96 */
+ 0xFF0000A4, /* 0x97 */
+ 0xFF000098, /* 0x98 */
+ 0xFF000088, /* 0x99 */
+ 0xFF00007C, /* 0x9A */
+ 0xFF000070, /* 0x9B */
+ 0xFF000064, /* 0x9C */
+ 0xFF000058, /* 0x9D */
+ 0xFF00004C, /* 0x9E */
+ 0xFF000040, /* 0x9F */
+ 0xFF282828, /* 0xA0 */
+
+ 0xFFFCE034, /* 0xA1 */
+ 0xFFFCD424, /* 0xA2 */
+ 0xFFFCCC18, /* 0xA3 */
+ 0xFFFCC008, /* 0xA4 */
+ 0xFFFCB400, /* 0xA5 */
+ 0xFFB420FC, /* 0xA6 */
+ 0xFFA800FC, /* 0xA7 */
+ 0xFF9800E4, /* 0xA8 */
+ 0xFF8000CC, /* 0xA9 */
+ 0xFF7400B4, /* 0xAA */
+ 0xFF60009C, /* 0xAB */
+ 0xFF500084, /* 0xAC */
+ 0xFF440070, /* 0xAD */
+ 0xFF340058, /* 0xAE */
+ 0xFF280040, /* 0xAF */
+ 0xFFFCD8FC, /* 0xB0 */
+
+ 0xFFFCB8FC, /* 0xB1 */
+ 0xFFFC9CFC, /* 0xB2 */
+ 0xFFFC7CFC, /* 0xB3 */
+ 0xFFFC5CFC, /* 0xB4 */
+ 0xFFFC40FC, /* 0xB5 */
+ 0xFFFC20FC, /* 0xB6 */
+ 0xFFFC00FC, /* 0xB7 */
+ 0xFFE000E4, /* 0xB8 */
+ 0xFFC800CC, /* 0xB9 */
+ 0xFFB400B4, /* 0xBA */
+ 0xFF9C009C, /* 0xBB */
+ 0xFF840084, /* 0xBC */
+ 0xFF6C0070, /* 0xBD */
+ 0xFF580058, /* 0xBE */
+ 0xFF400040, /* 0xBF */
+ 0xFFFCE8DC, /* 0xC0 */
+
+ 0xFFFCE0D0, /* 0xC1 */
+ 0xFFFCD8C4, /* 0xC2 */
+ 0xFFFCD4BC, /* 0xC3 */
+ 0xFFFCCCB0, /* 0xC4 */
+ 0xFFFCC4A4, /* 0xC5 */
+ 0xFFFCBC9C, /* 0xC6 */
+ 0xFFFCB890, /* 0xC7 */
+ 0xFFFCB080, /* 0xC8 */
+ 0xFFFCA470, /* 0xC9 */
+ 0xFFFC9C60, /* 0xCA */
+ 0xFFF0945C, /* 0xCB */
+ 0xFFE88C58, /* 0xCC */
+ 0xFFDC8854, /* 0xCD */
+ 0xFFD08050, /* 0xCE */
+ 0xFFC87C4C, /* 0xCF */
+ 0xFFBC7848, /* 0xD0 */
+
+ 0xFFB47044, /* 0xD1 */
+ 0xFFA86840, /* 0xD2 */
+ 0xFFA0643C, /* 0xD3 */
+ 0xFF9C6038, /* 0xD4 */
+ 0xFF905C34, /* 0xD5 */
+ 0xFF885830, /* 0xD6 */
+ 0xFF80502C, /* 0xD7 */
+ 0xFF744C28, /* 0xD8 */
+ 0xFF6C4824, /* 0xD9 */
+ 0xFF5C4020, /* 0xDA */
+ 0xFF543C1C, /* 0xDB */
+ 0xFF483818, /* 0xDC */
+ 0xFF403018, /* 0xDD */
+ 0xFF382C14, /* 0xDE */
+ 0xFF28200C, /* 0xDF */
+ 0xFF600064, /* 0xE0 */
+
+ 0xFF006464, /* 0xE1 */
+ 0xFF006060, /* 0xE2 */
+ 0xFF00001C, /* 0xE3 */
+ 0xFF00002C, /* 0xE4 */
+ 0xFF302410, /* 0xE5 */
+ 0xFF480048, /* 0xE6 */
+ 0xFF500050, /* 0xE7 */
+ 0xFF000034, /* 0xE8 */
+ 0xFF1C1C1C, /* 0xE9 */
+ 0xFF4C4C4C, /* 0xEA */
+ 0xFF5C5C5C, /* 0xEB */
+ 0xFF404040, /* 0xEC */
+ 0xFF303030, /* 0xED */
+ 0xFF343434, /* 0xEE */
+ 0xFFD8F4F4, /* 0xEF */
+ 0xFFB8E8E8, /* 0xF0 */
+
+ 0xFF9CDCDC, /* 0xF1 */
+ 0xFF74C8C8, /* 0xF2 */
+ 0xFF48C0C0, /* 0xF3 */
+ 0xFF20B4B4, /* 0xF4 */
+ 0xFF20B0B0, /* 0xF5 */
+ 0xFF00A4A4, /* 0xF6 */
+ 0xFF009898, /* 0xF7 */
+ 0xFF008C8C, /* 0xF8 */
+ 0xFF008484, /* 0xF9 */
+ 0xFF007C7C, /* 0xFA */
+ 0xFF007878, /* 0xFB */
+ 0xFF007474, /* 0xFC */
+ 0xFF007070, /* 0xFD */
+ 0xFF006C6C, /* 0xFE */
+ 0xFF980088, /* 0xFF */
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.cproject b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.cproject new file mode 100644 index 0000000..742db7a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.cproject @@ -0,0 +1,58 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="0.114656749"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg"> + <folderInfo id="0.114656749." name="/" resourcePath=""> + <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain"> + <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/> + <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> + <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> + <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1821379090" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.586544031" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1379525985" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="RT-STM32F429-DISCOVERY-TRIBUF.null.1703860681" name="RT-STM32F429-DISCOVERY-TRIBUF"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + <scannerConfigBuildInfo instanceId="0.114656749"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope" versionNumber="2"> + <configuration configurationName="Default"> + <resource resourceType="PROJECT" workspacePath="/RT-STM32F429-DISCOVERY-TRIBUF"/> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> +</cproject> diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.gitignore b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.gitignore new file mode 100644 index 0000000..0a3664e --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.gitignore @@ -0,0 +1,2 @@ +build/ +.dep/ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.project b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.project new file mode 100644 index 0000000..26c76f3 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/.project @@ -0,0 +1,90 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>RT-STM32F429-DISCOVERY-TRIBUF</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.autoBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value>-j1</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>make</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>os-community</name> + <type>2</type> + <locationURI>PARENT-3-PROJECT_LOC/os</locationURI> + </link> + <link> + <name>os-git</name> + <type>2</type> + <locationURI>PARENT-4-PROJECT_LOC/os</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/Makefile b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/Makefile new file mode 100644 index 0000000..ac6db0e --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/Makefile @@ -0,0 +1,225 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/community/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT = $(STARTUPLD)/STM32F429xI.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/community/os/various/tribuf.c \
+ ./usbcfg.c \
+ ./main.c \
+ # eol
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various \
+ $(CHIBIOS)/os/hal/lib/streams \
+ $(CHIBIOS)/community/os/various \
+ # eol
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/chconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/chconf.h new file mode 100644 index 0000000..9e83c6b --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/chconf.h @@ -0,0 +1,501 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS FALSE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES FALSE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES FALSE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES FALSE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS FALSE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS TRUE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#define TRIBUF_USE_WAIT TRUE
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..10e0dc6 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Run Only).launch b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Run Only).launch new file mode 100644 index 0000000..b28c65c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/debug/RT-STM32F429-DISCOVERY-TRIBUF (OpenOCD, Run Only).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-TRIBUF\debug"/>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf.h new file mode 100644 index 0000000..2e601fc --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf.h @@ -0,0 +1,340 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 115200
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Community drivers' includes */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h new file mode 100644 index 0000000..44e89df --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/main.c new file mode 100644 index 0000000..25ffd87 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/main.c @@ -0,0 +1,551 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "chprintf.h"
+#include "shell.h"
+#if (HAL_USE_SERIAL_USB == TRUE)
+#include "usbcfg.h"
+#endif
+
+#include "tribuf.h"
+#include <string.h>
+#include <stdlib.h>
+
+#if (HAL_USE_SERIAL_USB == TRUE)
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+static BaseSequentialStream *const chout = (BaseSequentialStream *)&SDU1;
+#else
+static BaseSequentialStream *const chout = (BaseSequentialStream *)&SD1;
+#endif
+
+/*===========================================================================*/
+/* Triple buffer related. */
+/*===========================================================================*/
+
+#define READER_STACK_SIZE 256
+#define READER_WA_SIZE THD_WORKING_AREA_SIZE(READER_STACK_SIZE)
+#define READER_DELAY_MS 200
+#define READER_PRIORITY (NORMALPRIO + 2)
+
+#define WRITER_STACK_SIZE 256
+#define WRITER_WA_SIZE THD_WORKING_AREA_SIZE(WRITER_STACK_SIZE)
+#define WRITER_DELAY_MS 100
+#define WRITER_PRIORITY (NORMALPRIO + 1)
+
+static thread_t *reader_tp;
+static uint16_t reader_delay = READER_DELAY_MS;
+static tprio_t reader_priority = READER_PRIORITY;
+static bool reader_suspend = false;
+static systime_t reader_timeout = TIME_INFINITE;
+
+static thread_t *writer_tp;
+static uint16_t writer_delay = WRITER_DELAY_MS;
+static tprio_t writer_priority = WRITER_PRIORITY;
+static bool writer_suspend = false;
+
+static tribuf_t tribuf_handler;
+static char buffer_a, buffer_b, buffer_c;
+
+static const char text[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";
+
+/**
+ * @brief Reads from the front buffer.
+ *
+ * @return Buffered character from @p text or special symbol.
+ * @retval '.' No new front buffer within timeout.
+ */
+static char read_front(void) {
+
+ const char *front;
+ msg_t error;
+ char c;
+
+ /* Wait until a new front buffer gets available with prepared data */
+ error = tribufWaitReadyTimeout(&tribuf_handler, reader_timeout);
+ if (error == MSG_OK) {
+ /* Retrieve the new front buffer */
+ tribufSwapFront(&tribuf_handler);
+ front = (const char *)tribufGetFront(&tribuf_handler);
+
+ /* Read data from the new front buffer */
+ c = front[0];
+ } else {
+ c = '.'; /* Timeout placeholder */
+ }
+ return c;
+}
+
+/*
+ * @brief Overwrites the back buffer with the provided character.
+ *
+ * @param[in] c Character to store into the current back buffer.
+ */
+static void write_back(char c) {
+
+ char *back;
+
+ /* Retrieve the current back buffer */
+ back = (char *)tribufGetBack(&tribuf_handler);
+
+ /* Prepare data onto the current back buffer */
+ back[0] = c;
+
+ /* Exchange the prepared buffer with a new one */
+ tribufSwapBack(&tribuf_handler);
+}
+
+/*
+ * Reads the front buffer and prints it.
+ */
+static THD_WORKING_AREA(reader_wa, READER_STACK_SIZE);
+static THD_FUNCTION(reader_thread, arg) {
+
+ thread_reference_t thread_ref;
+ tprio_t old_priority;
+ char c;
+ (void)arg;
+
+ chRegSetThreadName("reader_thread");
+ old_priority = chThdGetPriorityX();
+
+ for (;;) {
+ /* Read from the fron buffer and print the retrieved character */
+ c = read_front();
+ chprintf(chout, "%c", c);
+
+ /* Change priority, suspend or delay */
+ osalSysLock();
+ palTogglePad(GPIOG, GPIOG_LED3_GREEN);
+ if (old_priority != reader_priority) {
+ chThdSetPriority(reader_priority);
+ }
+ if (reader_suspend) {
+ thread_ref = NULL;
+ osalThreadSuspendS(&thread_ref);
+ reader_suspend = false;
+ } else {
+ osalThreadSleepS(MS2ST(reader_delay));
+ }
+ old_priority = chThdGetPriorityX();
+ osalSysUnlock();
+ }
+}
+
+/*
+ * Overwrites the back buffer with a fixed text, character by character.
+ */
+static THD_WORKING_AREA(writer_wa, WRITER_STACK_SIZE);
+static THD_FUNCTION(writer_thread, arg) {
+
+ thread_reference_t thread_ref;
+ tprio_t old_priority;
+ size_t i;
+ char c;
+ (void)arg;
+
+ chRegSetThreadName("writer_thread");
+ old_priority = chThdGetPriorityX();
+
+ for (;;) {
+ for (i = 0; i < sizeof(text); ++i) {
+ /* Write the next character on the current back buffer */
+ c = text[i];
+ write_back(c);
+
+ /* Change priority, suspend or delay */
+ osalSysLock();
+ palTogglePad(GPIOG, GPIOG_LED4_RED);
+ if (old_priority != writer_priority) {
+ chThdSetPriority(writer_priority);
+ }
+ if (writer_suspend) {
+ thread_ref = NULL;
+ osalThreadSuspendS(&thread_ref);
+ writer_suspend = false;
+ } else {
+ osalThreadSleepS(MS2ST(writer_delay));
+ }
+ osalSysUnlock();
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define streq(s1, s2) (strcmp((s1), (s2)) == 0)
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
+
+static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ size_t n, size;
+ (void)argv;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: mem\r\n");
+ return;
+ }
+
+ n = chHeapStatus(NULL, &size);
+ chprintf(chp, "core free memory : %u bytes\r\n", chCoreGetStatusX());
+ chprintf(chp, "heap fragments : %u\r\n", n);
+ chprintf(chp, "heap free total : %u bytes\r\n", size);
+}
+
+static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ static const char *states[] = {CH_STATE_NAMES};
+ thread_t *tp;
+ (void)argv;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: threads\r\n");
+ return;
+ }
+
+ chprintf(chp, " addr stack prio refs state name\r\n");
+ tp = chRegFirstThread();
+ do {
+ chprintf(chp, "%08lx %08lx %4lu %4lu %9s %s\r\n",
+ (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
+ (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
+ states[tp->p_state], tp->p_name);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+
+static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ thread_t *tp;
+ (void)argv;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: test\r\n");
+ return;
+ }
+
+ tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
+ TestThread, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory\r\n");
+ return;
+ }
+ chThdWait(tp);
+}
+
+static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ (void)argv;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: reset\r\n");
+ return;
+ }
+
+ chprintf(chp, "Will reset in 200ms\r\n");
+ chThdSleepMilliseconds(200);
+ NVIC_SystemReset();
+}
+
+static void cmd_run(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ thread_reference_t thread_ref;
+ const char *const usage = "Usage: run (reader|writer)\r\n";
+
+ if (argc != 1) {
+ chprintf(chp, usage);
+ return;
+ }
+
+ if (streq(argv[0], "reader")) {
+ osalSysLock();
+ if (reader_suspend) {
+ thread_ref = (thread_reference_t)reader_tp;
+ osalThreadResumeS(&thread_ref, MSG_OK);
+ }
+ osalSysUnlock();
+ }
+ else if (streq(argv[0], "writer")) {
+ osalSysLock();
+ if (writer_suspend) {
+ thread_ref = (thread_reference_t)writer_tp;
+ osalThreadResumeS(&thread_ref, MSG_OK);
+ }
+ osalSysUnlock();
+ }
+ else {
+ chprintf(chp, usage);
+ }
+}
+
+static void cmd_stop(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ const char *const usage = "Usage: stop (reader|writer)\r\n";
+
+ if (argc != 1) {
+ chprintf(chp, usage);
+ return;
+ }
+
+ if (streq(argv[0], "reader")) {
+ osalSysLock();
+ reader_suspend = true;
+ osalSysUnlock();
+ }
+ else if (streq(argv[0], "writer")) {
+ osalSysLock();
+ writer_suspend = true;
+ osalSysUnlock();
+ }
+ else {
+ chprintf(chp, usage);
+ }
+}
+
+static void cmd_delay(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ const char *const usage = "Usage: delay (reader|writer) DELAY_MS\r\n";
+ uint16_t delay;
+
+ if (argc != 2) {
+ chprintf(chp, usage);
+ return;
+ }
+ delay = (uint16_t)atoi(argv[1]);
+
+ if (streq(argv[0], "reader")) {
+ osalSysLock();
+ reader_delay = delay;
+ osalSysUnlock();
+ }
+ else if (streq(argv[0], "writer")) {
+ osalSysLock();
+ writer_delay = delay;
+ osalSysUnlock();
+ }
+ else {
+ chprintf(chp, usage);
+ }
+}
+
+static void cmd_priority(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ const char *const usage =
+ "Usage: priority (reader|writer) THREAD_PRIORITY\r\n";
+ tprio_t priority;
+
+ if (argc != 2) {
+ chprintf(chp, usage);
+ return;
+ }
+ priority = (tprio_t)atoi(argv[1]);
+
+ if (streq(argv[0], "reader")) {
+ osalSysLock();
+ reader_priority = priority;
+ osalSysUnlock();
+ }
+ else if (streq(argv[0], "writer")) {
+ osalSysLock();
+ writer_priority = priority;
+ osalSysUnlock();
+ }
+ else {
+ chprintf(chp, usage);
+ }
+}
+
+static void cmd_timeout(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ const char *const usage = "Usage: timeout TIMEOUT_MS\r\n";
+ systime_t timeout;
+
+ if (argc != 1) {
+ chprintf(chp, usage);
+ return;
+ }
+
+ if (streq(argv[0], "-"))
+ timeout = TIME_IMMEDIATE;
+ else if (streq(argv[0], "*"))
+ timeout = TIME_INFINITE;
+ else
+ timeout = (systime_t)atoi(argv[0]);
+
+ osalSysLock();
+ reader_timeout = timeout;
+ osalSysUnlock();
+}
+
+static void cmd_params(BaseSequentialStream *chp, int argc, char *argv[]) {
+
+ const char *const usage = "Usage: params\r\n";
+
+ uint32_t reader_delay_;
+ uint32_t reader_priority_;
+ uint32_t reader_suspend_;
+ uint32_t reader_timeout_;
+
+ uint32_t writer_delay_;
+ uint32_t writer_priority_;
+ uint32_t writer_suspend_;
+
+ (void)argv;
+ if (argc != 0) {
+ chprintf(chp, usage);
+ return;
+ }
+
+ osalSysLock();
+ reader_delay_ = (uint32_t)reader_delay;
+ reader_priority_ = (uint32_t)reader_priority;
+ reader_suspend_ = (uint32_t)reader_suspend;
+ reader_timeout_ = (uint32_t)reader_timeout;
+
+ writer_delay_ = (uint32_t)writer_delay;
+ writer_priority_ = (uint32_t)writer_priority;
+ writer_suspend_ = (uint32_t)writer_suspend;
+ osalSysUnlock();
+
+ chprintf(chp, "reader_delay %U\r\n", reader_delay_);
+ chprintf(chp, "reader_priority %U\r\n", reader_priority_);
+ chprintf(chp, "reader_suspend %U\r\n", reader_suspend_);
+ if (reader_timeout_ == TIME_IMMEDIATE)
+ chprintf(chp, "reader_timeout -\r\n");
+ if (reader_timeout_ == TIME_INFINITE)
+ chprintf(chp, "reader_timeout *\r\n");
+ else
+ chprintf(chp, "reader_timeout %U\r\n", reader_timeout_);
+
+ chprintf(chp, "writer_delay %U\r\n", writer_delay_);
+ chprintf(chp, "writer_priority %U\r\n", writer_priority_);
+ chprintf(chp, "writer_suspend %U\r\n", writer_suspend_);
+}
+
+static const ShellCommand commands[] = {
+ {"mem", cmd_mem},
+ {"threads", cmd_threads},
+ {"test", cmd_test},
+ {"reset", cmd_reset},
+ {"run", cmd_run},
+ {"stop", cmd_stop},
+ {"delay", cmd_delay},
+ {"priority", cmd_priority},
+ {"timeout", cmd_timeout},
+ {"params", cmd_params},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+#if (HAL_USE_SERIAL_USB == TRUE)
+ (BaseSequentialStream *)&SDU1,
+#else
+ (BaseSequentialStream *)&SD1,
+#endif
+ commands
+};
+
+/*===========================================================================*/
+/* Initialization and main thread. */
+/*===========================================================================*/
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ thread_t *shelltp = NULL;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+#if (HAL_USE_SERIAL_USB == TRUE)
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1000);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+#else
+ /*
+ * Initializes serial port.
+ */
+ sdStart(&SD1, NULL);
+#endif /* HAL_USE_SERIAL_USB */
+
+ /*
+ * Writer and reader threads started for triple buffer demo.
+ */
+ tribufObjectInit(&tribuf_handler, &buffer_a, &buffer_b, &buffer_c);
+
+ reader_tp = chThdCreateStatic(reader_wa, READER_WA_SIZE,
+ reader_priority, reader_thread, NULL);
+
+ writer_tp = chThdCreateStatic(writer_wa, WRITER_WA_SIZE,
+ writer_priority, writer_thread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it just performs
+ * a shell respawn upon its termination.
+ */
+ for (;;) {
+ if (!shelltp) {
+#if (HAL_USE_SERIAL_USB == TRUE)
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ /* Spawns a new shell.*/
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ }
+#else
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+#endif
+ }
+ else {
+ /* If the previous shell exited.*/
+ if (chThdTerminatedX(shelltp)) {
+ /* Recovers memory of the previous shell.*/
+ chThdRelease(shelltp);
+ shelltp = NULL;
+ }
+ }
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
+
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf.h new file mode 100644 index 0000000..0438c01 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf.h @@ -0,0 +1,347 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+#define STM32_SAISRC STM32_SAISRC_PLL
+#define STM32_PLLSAIN_VALUE 192
+#define STM32_PLLSAIQ_VALUE 7
+#define STM32_PLLSAIR_VALUE 4
+#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 FALSE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 TRUE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * Header for community drivers.
+ */
+#include "mcuconf_community.h"
+
+#endif /* _MCUCONF_H_ */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf_community.h new file mode 100644 index 0000000..5fd93fb --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/mcuconf_community.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 FALSE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/readme.txt b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/readme.txt new file mode 100644 index 0000000..cc7f406 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F429. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F429I-Discovery board. + +** The Demo ** + +This demo shows how to use a triple buffer handler, with one writer thread and +one reader thread. +The writer thread puts a character into the current back buffer, thus swapping +the back buffer with the orphan buffer for a new write. The writer then sleeps +for a specified delay in milliseconds. +The reader thread gets waits (if there is a timeout) until the orphan buffer +contains available data, becoming the new front buffer. The character is read +from the new front buffer and printed. The reader then sleeps for a specified +delay in milliseconds. +A simple command shell is activated on virtual serial port SD1 or SDU1. +Via command line it is possible to start, stop, set the delay, and set the +thread priority of the reader and writer threads. +The reader can also be assigned a wait timeout in milliseconds, with special +cases of "*" for infinite timeout, and "-" (or 0 ms) for none. + +** Build Procedure ** + +The demo has been tested by using the free GNU Tools ARM Embedded toolchain +and ChibiStudio. Just modify the TRGT line in the makefile in order to use +different GCC toolchains. diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.c b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.c new file mode 100644 index 0000000..9f95a2a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.c @@ -0,0 +1,314 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Endpoints to be used for USBD2.
+ */
+#define USBD2_DATA_REQUEST_EP 1
+#define USBD2_DATA_AVAILABLE_EP 1
+#define USBD2_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0483, /* idVendor (ST). */
+ 0x5740, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 3 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(38), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+ 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+ 'c', 0, 's', 0
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(56), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
+ 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
+ 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
+ 'o', 0, 'r', 0, 't', 0
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ NULL
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD2,
+ USBD2_DATA_REQUEST_EP,
+ USBD2_DATA_AVAILABLE_EP,
+ USBD2_INTERRUPT_REQUEST_EP
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.h new file mode 100644 index 0000000..2ffaa17 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/usbcfg.h @@ -0,0 +1,25 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile index 6a6d35e..884406a 100644 --- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,26 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -123,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile index 2841644..ed53024 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -lm + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,31 +81,36 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C129xNC.ld +LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ $(LWSRC) \ $(CHIBIOS)/os/various/evtimer.c \ main.c \ web/web.c \ - $(CHIBIOS)/os/various/chprintf.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -127,11 +137,11 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ - $(CHIBIOS)/os/various +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various $(LWINC) # # Project, sources and paths @@ -154,6 +164,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex @@ -180,7 +191,7 @@ CPPWARN = -Wall -Wextra # # List all user C define here, like -D_DEBUG=1 -UDEFS = -DLWIP_DEBUG=0 +UDEFS = # Define ASM defines here UADEFS = diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h index a3c6b3b..00b4fe5 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h @@ -95,6 +95,6 @@ * ST driver system settings. */ #define TIVA_ST_IRQ_PRIORITY 2 -#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_USE_WIDE_TIMER FALSE #define TIVA_ST_TIMER_NUMBER 5 #define TIVA_ST_TIMER_LETTER A diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile index 5321329..12680c1 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,26 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C129xNC.ld +LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -123,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h index a3c6b3b..00b4fe5 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h @@ -95,6 +95,6 @@ * ST driver system settings. */ #define TIVA_ST_IRQ_PRIORITY 2 -#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_USE_WIDE_TIMER FALSE #define TIVA_ST_TIMER_NUMBER 5 #define TIVA_ST_TIMER_LETTER A diff --git a/demos/various/RT-Win32-TriBuf/.cproject b/demos/various/RT-Win32-TriBuf/.cproject new file mode 100644 index 0000000..f7198ab --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/.cproject @@ -0,0 +1,50 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.759990224">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.759990224" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.759990224" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.759990224." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.221916885" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.221916885.1754418474" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.978207162" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.1955256520" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.681446675" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.2122537408" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.2123891590" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.977304391" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1641835309" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1340673795" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="RT-Win32-TRIBUF.null.623541221" name="RT-Win32-TRIBUF"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.759990224">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/demos/various/RT-Win32-TriBuf/.gitignore b/demos/various/RT-Win32-TriBuf/.gitignore new file mode 100644 index 0000000..dfbbe17 --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/.gitignore @@ -0,0 +1,9 @@ +*.origin
+*.swp
+*~
+.dep
+build
+*.o
+*.exe
+*.lst
+*.map
\ No newline at end of file diff --git a/demos/various/RT-Win32-TriBuf/.project b/demos/various/RT-Win32-TriBuf/.project new file mode 100644 index 0000000..1e168ca --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/.project @@ -0,0 +1,38 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RT-Win32-TRIBUF</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>board</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os/hal/boards/simulator</locationURI>
+ </link>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/demos/various/RT-Win32-TriBuf/Makefile b/demos/various/RT-Win32-TriBuf/Makefile new file mode 100644 index 0000000..8674226 --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/Makefile @@ -0,0 +1,151 @@ +#
+# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!!
+#
+##############################################################################################
+#
+# On command line:
+#
+# make all = Create project
+#
+# make clean = Clean project files.
+#
+# To rebuild project do "make clean" and "make all".
+#
+
+##############################################################################################
+# Start of default section
+#
+
+TRGT = mingw32-
+CC = $(TRGT)gcc
+AS = $(TRGT)gcc -x assembler-with-cpp
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = -DSIMULATOR
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS = -lws2_32
+
+#
+# End of default section
+##############################################################################################
+
+##############################################################################################
+# Start of user section
+#
+
+# Define project name here
+PROJECT = ch
+
+# Define linker script file here
+LDSCRIPT =
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# Imported source files
+CHIBIOS = ../../../..
+include $(CHIBIOS)/os/hal/boards/simulator/board.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/ports/simulator/win32/platform.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/test/rt/test.mk
+
+# List C source files here
+SRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(OSALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/community/os/various/tribuf.c \
+ main.c \
+ # eol
+
+# List ASM source files here
+ASRC =
+
+# List all user directories here
+UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/community/os/various/ \
+ # eol
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+# Define optimisation level here
+OPT = -ggdb -O2
+
+#
+# End of user defines
+##############################################################################################
+
+INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
+LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
+LIBS = $(DLIBS) $(ULIBS)
+
+LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
+ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
+CPFLAGS = -Wall -Wextra -Wundef -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS)
+
+# Generate dependency information
+CPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+#
+# makefile rules
+#
+
+all: $(OBJS) $(PROJECT).exe
+
+%.o : %.c
+ $(CC) -c $(OPT) $(CPFLAGS) -I . $(INCDIR) $< -o $@
+
+%.o : %.s
+ $(AS) -c $(OPT) $(ASFLAGS) $< -o $@
+
+%exe: $(OBJS)
+ $(CC) $(OPT) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+
+gcov:
+ -mkdir gcov
+ $(COV) -u $(subst /,\,$(SRC))
+ -mv *.gcov ./gcov
+
+clean:
+ -rm -f $(OBJS)
+ -rm -f $(PROJECT).exe
+ -rm -f $(PROJECT).map
+ -rm -f $(SRC:.c=.c.bak)
+ -rm -f $(SRC:.c=.lst)
+ -rm -f $(ASRC:.s=.s.bak)
+ -rm -f $(ASRC:.s=.lst)
+ -rm -fR .dep
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/demos/various/RT-Win32-TriBuf/chconf.h b/demos/various/RT-Win32-TriBuf/chconf.h new file mode 100644 index 0000000..835d59b --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/chconf.h @@ -0,0 +1,502 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0x20000
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS FALSE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS FALSE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES FALSE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES FALSE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES FALSE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS FALSE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS TRUE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+ halt(reason); \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+void halt(const char *reason);
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/various/RT-Win32-TriBuf/halconf.h b/demos/various/RT-Win32-TriBuf/halconf.h new file mode 100644 index 0000000..286864b --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/halconf.h @@ -0,0 +1,326 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+/*#include "mcuconf.h"*/
+
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM FALSE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL FALSE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 32
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/various/RT-Win32-TriBuf/main.c b/demos/various/RT-Win32-TriBuf/main.c new file mode 100644 index 0000000..bab25cd --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/main.c @@ -0,0 +1,171 @@ +/*
+ Copyright (C) 2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "tribuf.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+/*===========================================================================*/
+/* TriBuf related. */
+/*===========================================================================*/
+
+#define WRITER_DELAY_MS 10
+#define READER_DELAY_MS 20
+
+#define WRITER_STACK_SIZE 4096
+#define READER_STACK_SIZE 4096
+
+#define WRITER_PRIORITY (NORMALPRIO + 1)
+#define READER_PRIORITY (NORMALPRIO + 2)
+
+static thread_t *writertp;
+static thread_t *readertp;
+
+static tribuf_t tribuf;
+static char buffers[3];
+
+static const char text[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";
+
+/*
+ * Reads from the front buffer.
+ */
+static char read_front(void) {
+
+ const char *front;
+ msg_t error;
+
+ /* Wait until a new front buffer gets available with prepared data */
+ error = tribufWaitReadyTimeout(&tribuf, MS2ST(1000));
+ if (error == MSG_TIMEOUT)
+ chSysHalt("ERROR: read_front() timed out");
+
+ /* Retrieve the new front buffer */
+ tribufSwapFront(&tribuf);
+ front = (const char *)tribufGetFront(&tribuf);
+
+ /* Read data from the new front buffer */
+ return front[0];
+}
+
+/*
+ * Overwrites the back buffer with the provided character.
+ */
+static void write_back(char c) {
+
+ char *back;
+
+ /* Retrieve the current back buffer */
+ back = (char *)tribufGetBack(&tribuf);
+
+ /* Prepare data onto the current back buffer */
+ back[0] = c;
+
+ /* Exchange the prepared buffer with a new one */
+ tribufSwapBack(&tribuf);
+}
+
+/*
+ * Overwrites the back buffer with a fixed text, character by character.
+ */
+static THD_WORKING_AREA(writer_wa, WRITER_STACK_SIZE);
+static THD_FUNCTION(writer_thread, arg) {
+
+ const uint32_t delay = (uint32_t)(msg_t)arg;
+ size_t i;
+ char c;
+
+ chRegSetThreadName("writer_thread");
+ for (;;) {
+ for (i = 0; i < sizeof(text); ++i) {
+ c = text[i];
+ write_back(c);
+ chThdSleepMilliseconds(delay);
+ }
+ }
+}
+
+/*
+ * Reads the front buffer and prints it.
+ */
+static THD_WORKING_AREA(reader_wa, READER_STACK_SIZE);
+static THD_FUNCTION(reader_thread, arg) {
+
+ const uint32_t delay = (uint32_t)(msg_t)arg;
+ char c;
+
+ chRegSetThreadName("reader_thread");
+ for (;;) {
+ c = read_front();
+ fprintf(stdout, "%c", c);
+ chThdSleepMilliseconds(delay);
+ }
+}
+
+/*===========================================================================*/
+/* Initialization and main thread. */
+/*===========================================================================*/
+
+/*
+ * Simulator main.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Writer and reader threads started for triple buffer demo.
+ */
+ tribufObjectInit(&tribuf, &buffers[0], &buffers[1], &buffers[2]);
+
+ readertp = chThdCreateStatic(reader_wa, sizeof(reader_wa),
+ READER_PRIORITY,
+ reader_thread, (void *)READER_DELAY_MS);
+
+ writertp = chThdCreateStatic(writer_wa, sizeof(writer_wa),
+ WRITER_PRIORITY,
+ writer_thread, (void *)WRITER_DELAY_MS);
+
+ /*
+ * Let the threads process data.
+ */
+ for (;;)
+ chThdSleepMilliseconds(1000);
+
+ return 0;
+}
+
+/*
+ * Critical error function.
+ */
+void halt(const char *reason) {
+
+ fflush(stdout);
+ fputs("\n", stdout);
+ fputs(reason, stderr);
+ fflush(stderr);
+ exit(1);
+}
diff --git a/demos/various/RT-Win32-TriBuf/readme.txt b/demos/various/RT-Win32-TriBuf/readme.txt new file mode 100644 index 0000000..e72e2e0 --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/readme.txt @@ -0,0 +1,33 @@ +*****************************************************************************
+** ChibiOS/RT port for x86 into a Win32 process **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs under any Windows version as an application program. The serial
+I/O is simulated over TCP/IP sockets.
+
+** The Demo **
+
+The demo listens on the two serial ports, when a connection is detected a
+thread is started that serves a small command shell.
+The demo shows how to create/terminate threads at runtime, how to listen to
+events, how to work with serial ports, how to use the messages.
+You can develop your ChibiOS/RT application using this demo as a simulator
+then you can recompile it for a different architecture.
+See demo.c for details.
+
+** Build Procedure **
+
+The demo was built using the MinGW toolchain.
+
+** Connect to the demo **
+
+In order to connect to the demo a telnet client is required. A good choice
+is PuTTY:
+
+http://www.putty.org/
+
+Host Name: 127.0.0.1
+Port: 29001 and/or 29002
+Connection Type: Raw
diff --git a/demos/various/RT-Win32-TriBuf/run.bat b/demos/various/RT-Win32-TriBuf/run.bat new file mode 100644 index 0000000..5d697c5 --- /dev/null +++ b/demos/various/RT-Win32-TriBuf/run.bat @@ -0,0 +1,2 @@ +ch.exe
+PAUSE
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/NRF51822.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/NRF51822.ld new file mode 100644 index 0000000..ba12060 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/NRF51822.ld @@ -0,0 +1,48 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * NRF51822 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 256k + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + +INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld new file mode 100644 index 0000000..9ba192e --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld @@ -0,0 +1,50 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/* + * ST32F103x8 memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 64k + ram0 : org = 0x20000000, len = 20k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld new file mode 100644 index 0000000..705a44f --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld @@ -0,0 +1,50 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/* + * ST32F103xC memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram0 : org = 0x20000000, len = 48k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld index 53e04bd..8f676a0 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 32k - ram : org = 0x20000000, len = 12k + ram0 : org = 0x20000000, len = 12k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld index 4378c41..1968cd0 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 64k - ram : org = 0x20000000, len = 24k + ram0 : org = 0x20000000, len = 24k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld index cad084f..7b12b53 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 128k - ram : org = 0x20000000, len = 32k + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld index ecdcf26..5c049b9 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld @@ -20,7 +20,28 @@ MEMORY { flash : org = 0x00000000, len = 256k - ram : org = 0x20000000, len = 32k + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld index 875158e..0f3fef1 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 512k - ram : org = 0x20000000, len = 256k + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld index f36164e..fd23266 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld @@ -19,8 +19,30 @@ */ MEMORY { - flash : org = 0x00000000, len = 1024k - ram : org = 0x20000000, len = 256k + flash : org = 0x00000000, len = 1M + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_nrf51.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_nrf51.mk new file mode 100644 index 0000000..7433ba2 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_nrf51.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS generic NRF51 startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s
+
+STARTUPINC = $(CHIBIOS)/community/os/common/ports/ARMCMx/devices/NRF51822 \
+ $(CHIBIOS)/os/ext/CMSIS/include
+
+STARTUPLD = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld
+
diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk new file mode 100644 index 0000000..35d4fc8 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic TM4C123x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s + +STARTUPINC = $(CHIBIOS)/community/os/common/ports/ARMCMx/devices/TM4C123x \ + $(CHIBIOS)/os/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk new file mode 100644 index 0000000..6ce72da --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic TM4C129x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s + +STARTUPINC = $(CHIBIOS)/community/os/common/ports/ARMCMx/devices/TM4C129x \ + $(CHIBIOS)/os/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/common/ports/ARMCMx/devices/NRF51822/cmparams.h b/os/common/ports/ARMCMx/devices/NRF51822/cmparams.h new file mode 100644 index 0000000..126acf6 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/NRF51822/cmparams.h @@ -0,0 +1,82 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file NRF51822/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the Nordic Semi NRF51822 family.
+ *
+ * @defgroup ARMCMx_NRF51x Nordic semiconductor NRF51x.
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * NRF51x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "nrf51.h"
+
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h b/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h index 3e5457c..c9e98bd 100644 --- a/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h +++ b/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h @@ -26,7 +26,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M4 +#define CORTEX_MODEL 4 /** * @brief Memory Protection unit presence. diff --git a/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h b/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h index ea5821f..5bd8a7b 100644 --- a/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h +++ b/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h @@ -26,7 +26,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M4 +#define CORTEX_MODEL 4 /** * @brief Memory Protection unit presence. diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index 9145af2..05aeceb 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -24,7 +24,7 @@ /* * Board identifier. */ -#define BOARD_NAME "NAND and SRAM test board. Codename Buod" +#define BOARD_NAME "NAND and SRAM test board (codename Buod)" /* * Board oscillators-related settings. @@ -60,14 +60,22 @@ #define GPIOA_PIN6 6 #define GPIOA_PIN7 7 #define GPIOA_PIN8 8 -#define GPIOA_PIN9 9 +#define GPIOA_USB_PRESENT 9 #define GPIOA_PIN10 10 -#define GPIOA_PIN11 11 -#define GPIOA_PIN12 12 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 #define GPIOA_JTMS 13 #define GPIOA_JTCK 14 #define GPIOA_JTDI 15 + + +#define GPIOA_USB_PRESENT 9 +#define GPIOA_PIN10 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 + + #define GPIOB_PIN0 0 #define GPIOB_NAND_WP 1 #define GPIOB_PIN2 2 @@ -238,10 +246,10 @@ PIN_MODE_INPUT(GPIOA_PIN6) | \ PIN_MODE_INPUT(GPIOA_PIN7) | \ PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_USB_PRESENT) | \ PIN_MODE_INPUT(GPIOA_PIN10) | \ - PIN_MODE_INPUT(GPIOA_PIN11) | \ - PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ PIN_MODE_ALTERNATE(GPIOA_JTDI)) @@ -254,10 +262,10 @@ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_PRESENT) |\ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTDI)) @@ -270,10 +278,10 @@ PIN_OSPEED_100M(GPIOA_PIN6) | \ PIN_OSPEED_100M(GPIOA_PIN7) | \ PIN_OSPEED_100M(GPIOA_PIN8) | \ - PIN_OSPEED_100M(GPIOA_PIN9) | \ + PIN_OSPEED_100M(GPIOA_USB_PRESENT) | \ PIN_OSPEED_100M(GPIOA_PIN10) | \ - PIN_OSPEED_100M(GPIOA_PIN11) | \ - PIN_OSPEED_100M(GPIOA_PIN12) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ PIN_OSPEED_100M(GPIOA_JTMS) | \ PIN_OSPEED_100M(GPIOA_JTCK) | \ PIN_OSPEED_100M(GPIOA_JTDI)) @@ -286,10 +294,10 @@ PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_PRESENT) |\ PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ PIN_PUPDR_FLOATING(GPIOA_JTMS) | \ PIN_PUPDR_FLOATING(GPIOA_JTCK) | \ PIN_PUPDR_FLOATING(GPIOA_JTDI)) @@ -302,10 +310,10 @@ PIN_ODR_HIGH(GPIOA_PIN6) | \ PIN_ODR_HIGH(GPIOA_PIN7) | \ PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_USB_PRESENT) | \ PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_PIN11) | \ - PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ PIN_ODR_HIGH(GPIOA_JTMS) | \ PIN_ODR_HIGH(GPIOA_JTCK) | \ PIN_ODR_HIGH(GPIOA_JTDI)) @@ -318,10 +326,10 @@ PIN_AFIO_AF(GPIOA_PIN6, 0) | \ PIN_AFIO_AF(GPIOA_PIN7, 0)) #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_USB_PRESENT, 0) | \ PIN_AFIO_AF(GPIOA_PIN10, 0) | \ - PIN_AFIO_AF(GPIOA_PIN11, 0) | \ - PIN_AFIO_AF(GPIOA_PIN12, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ PIN_AFIO_AF(GPIOA_JTMS, 0) | \ PIN_AFIO_AF(GPIOA_JTCK, 0) | \ PIN_AFIO_AF(GPIOA_JTDI, 0)) diff --git a/os/hal/boards/WVSHARE_BLE400/board.c b/os/hal/boards/WVSHARE_BLE400/board.c new file mode 100644 index 0000000..9bae7ab --- /dev/null +++ b/os/hal/boards/WVSHARE_BLE400/board.c @@ -0,0 +1,85 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + .pads = { + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.0: SDA */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.1: SCL */ + PAL_MODE_UNCONNECTED, /* P0.2 */ + PAL_MODE_UNCONNECTED, /* P0.3 */ + PAL_MODE_UNCONNECTED, /* P0.4 */ + PAL_MODE_UNCONNECTED, /* P0.5 */ + PAL_MODE_UNCONNECTED, /* P0.6 */ + PAL_MODE_UNCONNECTED, /* P0.7 */ + PAL_MODE_UNCONNECTED, /* P0.8 UART_RTS */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.9: UART_TX */ + PAL_MODE_UNCONNECTED, /* P0.10 UART_CTS */ + PAL_MODE_INPUT_PULLUP, /* P0.11: UART_RX */ + PAL_MODE_UNCONNECTED, /* P0.12 */ + PAL_MODE_UNCONNECTED, /* P0.13 */ + PAL_MODE_UNCONNECTED, /* P0.14 */ + PAL_MODE_UNCONNECTED, /* P0.15 */ + PAL_MODE_INPUT_PULLUP, /* P0.16: KEY1 */ + PAL_MODE_INPUT_PULLUP, /* P0.17: KEY2 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.18: LED0 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.19: LED1 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: LED2 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: LED3 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: LED4 */ + PAL_MODE_INPUT, /* P0.23: SPI_MISO */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: SPI_MOSI */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_SCK */ + PAL_MODE_UNCONNECTED, /* P0.26 */ + PAL_MODE_UNCONNECTED, /* P0.27 */ + PAL_MODE_UNCONNECTED, /* P0.28 */ + PAL_MODE_UNCONNECTED, /* P0.29 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.30: SPI_NSS */ + PAL_MODE_UNCONNECTED, /* P0.31 */ + }, +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ + //FIXME: not really needed yet + //NRF_CLOCK->XTALFREQ = 0xff; + //NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + //NRF_CLOCK->TASKS_HFCLKSTART = 1; + //while (!NRF_CLOCK->EVENTS_HFCLKSTARTED) {} +} diff --git a/os/hal/boards/WVSHARE_BLE400/board.h b/os/hal/boards/WVSHARE_BLE400/board.h new file mode 100644 index 0000000..957fe7e --- /dev/null +++ b/os/hal/boards/WVSHARE_BLE400/board.h @@ -0,0 +1,46 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Board identifier. */ +#define BOARD_WVSHARE_BLE400 +#define BOARD_NAME "WvShare BLE400" + +/* Board oscillators-related settings. */ +#define XTAL_VALUE 16000000 + +/* GPIO pins. */ +#define LED0 18 +#define LED1 19 +#define LED2 20 +#define LED3 21 +#define LED4 22 +#define UART_TX 9 +#define UART_RX 11 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/WVSHARE_BLE400/board.mk b/os/hal/boards/WVSHARE_BLE400/board.mk new file mode 100644 index 0000000..1fddc87 --- /dev/null +++ b/os/hal/boards/WVSHARE_BLE400/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/community/os/hal/boards/WVSHARE_BLE400/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/community/os/hal/boards/WVSHARE_BLE400 diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 2508c90..51cda56 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -1,8 +1,8 @@ include ${CHIBIOS}/os/hal/hal.mk
HALSRC += ${CHIBIOS}/community/os/hal/src/hal_community.c \
- ${CHIBIOS}/community/os/hal/src/nand.c \
- ${CHIBIOS}/community/os/hal/src/onewire.c \
- ${CHIBIOS}/community/os/hal/src/eicu.c
+ ${CHIBIOS}/community/os/hal/src/nand.c \
+ ${CHIBIOS}/community/os/hal/src/onewire.c \
+ ${CHIBIOS}/community/os/hal/src/eicu.c
HALINC += ${CHIBIOS}/community/os/hal/include
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 6a60491..6cd6b66 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -1,20 +1,17 @@ /*
- ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+ ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
- This file is part of ChibiOS/HAL
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/HAL is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
diff --git a/os/hal/include/nand.h b/os/hal/include/nand.h index e20add3..a1d2f86 100644 --- a/os/hal/include/nand.h +++ b/os/hal/include/nand.h @@ -1,25 +1,18 @@ /* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - This file is part of ChibiOS/HAL + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/HAL is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ /** * @file nand.h @@ -111,31 +104,28 @@ extern "C" { #endif void nandInit(void); void nandObjectInit(NANDDriver *nandp); - void nandStart(NANDDriver *nandp, const NANDConfig *config); + void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map); void nandStop(NANDDriver *nandp); - void nandReadPageWhole(NANDDriver *nandp, uint32_t block, - uint32_t page, uint8_t *data, size_t datalen); - uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *data, size_t datalen); - void nandReadPageData(NANDDriver *nandp, uint32_t block, - uint32_t page, uint8_t *data, size_t datalen, uint32_t *ecc); - uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *data, size_t datalen, uint32_t *ecc); - void nandReadPageSpare(NANDDriver *nandp, uint32_t block, - uint32_t page, uint8_t *spare, size_t sparelen); - uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *spare, size_t sparelen); + void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, + uint8_t *data, size_t datalen); void nandMarkBad(NANDDriver *nandp, uint32_t block); - uint8_t nandReadBadMark(NANDDriver *nandp, - uint32_t block, uint32_t page); + void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, + uint8_t *data, size_t datalen, uint32_t *ecc); + void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, + uint8_t *spare, size_t sparelen); + uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *data, size_t datalen); + uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *data, size_t datalen, uint32_t *ecc); + uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *spare, size_t sparelen); + uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page); uint8_t nandErase(NANDDriver *nandp, uint32_t block); bool nandIsBad(NANDDriver *nandp, uint32_t block); - #if NAND_USE_MUTUAL_EXCLUSION void nandAcquireBus(NANDDriver *nandp); void nandReleaseBus(NANDDriver *nandp); #endif /* NAND_USE_MUTUAL_EXCLUSION */ - #ifdef __cplusplus } #endif diff --git a/os/hal/include/onewire.h b/os/hal/include/onewire.h index dc82a67..a2760e6 100644 --- a/os/hal/include/onewire.h +++ b/os/hal/include/onewire.h @@ -14,8 +14,6 @@ limitations under the License. */ - - /** * @file onewire.h * @brief 1-wire Driver macros and structures. diff --git a/os/hal/ports/NRF51/NRF51822/hal_lld.c b/os/hal/ports/NRF51/NRF51822/hal_lld.c new file mode 100644 index 0000000..e1d2ed5 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/hal_lld.c @@ -0,0 +1,62 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file NRF51/NRF51822/hal_lld.c + * @brief NRF51822 HAL Driver subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ +} + +/** + * @} + */ diff --git a/os/hal/ports/NRF51/NRF51822/hal_lld.h b/os/hal/ports/NRF51/NRF51822/hal_lld.h new file mode 100644 index 0000000..1cc9057 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/hal_lld.h @@ -0,0 +1,77 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file NRF51/NRF51822/hal_lld.h + * @brief NRF51822 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "Nordic Semiconductor nRF51822" + +/** + * @} + */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "nvic.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void nrf51_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** + * @} + */ diff --git a/os/hal/ports/NRF51/NRF51822/nrf51.h b/os/hal/ports/NRF51/NRF51822/nrf51.h new file mode 100644 index 0000000..1ed33d6 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/nrf51.h @@ -0,0 +1,1315 @@ +
+/****************************************************************************************************//**
+ * @file nrf51.h
+ *
+ * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ * nrf51 from Nordic Semiconductor.
+ *
+ * @version V522
+ * @date 26. January 2015
+ *
+ * @note Generated with SVDConv V2.81d
+ * from CMSIS SVD File 'nrf51.xml' Version 522,
+ *
+ * @par Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+/** @addtogroup nrf51
+ * @{
+ */
+
+#ifndef NRF51_H
+#define NRF51_H
+
+#include "nrf51_bitfields.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UART0_IRQn = 2, /*!< 2 UART0 */
+ SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
+ SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ ADC_IRQn = 7, /*!< 7 ADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
+ SWI0_IRQn = 20, /*!< 20 SWI0 */
+ SWI1_IRQn = 21, /*!< 21 SWI1 */
+ SWI2_IRQn = 22, /*!< 22 SWI2 */
+ SWI3_IRQn = 23, /*!< 23 SWI3 */
+ SWI4_IRQn = 24, /*!< 24 SWI4 */
+ SWI5_IRQn = 25 /*!< 25 SWI5 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+ __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
+ __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
+ __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
+ __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
+ __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
+ __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
+} AMLI_RAMPRI_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK. */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t MISO; /*!< Pin select for MISO. */
+} SPIM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
+ __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
+} SPIM_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
+ __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
+} SPIM_TXD_Type;
+
+typedef struct {
+ __O uint32_t EN; /*!< Enable channel group. */
+ __O uint32_t DIS; /*!< Disable channel group. */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+ __IO uint32_t EEP; /*!< Channel event end-point. */
+ __IO uint32_t TEP; /*!< Channel task end-point. */
+} PPI_CH_Type;
+
+
+/* ================================================================================ */
+/* ================ POWER ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Control. (POWER)
+ */
+
+typedef struct { /*!< POWER Structure */
+ __I uint32_t RESERVED0[30];
+ __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
+ __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
+ __I uint32_t RESERVED1[34];
+ __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __IO uint32_t RESETREAS; /*!< Reset reason. */
+ __I uint32_t RESERVED4[9];
+ __I uint32_t RAMSTATUS; /*!< Ram status register. */
+ __I uint32_t RESERVED5[53];
+ __O uint32_t SYSTEMOFF; /*!< System off register. */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t POFCON; /*!< Power failure configuration. */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
+ register. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t RAMON; /*!< Ram on/off. */
+ __I uint32_t RESERVED9[7];
+ __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
+ is a retained register. */
+ __I uint32_t RESERVED10[3];
+ __IO uint32_t RAMONB; /*!< Ram on/off. */
+ __I uint32_t RESERVED11[8];
+ __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
+ __I uint32_t RESERVED12[291];
+ __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================ CLOCK ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Clock control. (CLOCK)
+ */
+
+typedef struct { /*!< CLOCK Structure */
+ __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
+ __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
+ __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
+ __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
+ __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
+ __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
+ __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
+ __I uint32_t RESERVED0[57];
+ __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
+ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
+ __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
+ __I uint32_t RESERVED2[124];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[63];
+ __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
+ __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
+ __I uint32_t RESERVED4;
+ __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
+ __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
+ __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+ triggered. */
+ __I uint32_t RESERVED5[62];
+ __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t CTIV; /*!< Calibration timer interval. */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================ MPU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Memory Protection Unit. (MPU)
+ */
+
+typedef struct { /*!< MPU Structure */
+ __I uint32_t RESERVED0[330];
+ __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
+ __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
+ __I uint32_t RESERVED1[52];
+ __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
+ __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
+} NRF_MPU_Type;
+
+
+/* ================================================================================ */
+/* ================ PU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Patch unit. (PU)
+ */
+
+typedef struct { /*!< PU Structure */
+ __I uint32_t RESERVED0[448];
+ __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
+ __I uint32_t RESERVED1[24];
+ __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
+ __I uint32_t RESERVED2[24];
+ __IO uint32_t PATCHEN; /*!< Patch enable register. */
+ __IO uint32_t PATCHENSET; /*!< Patch enable register. */
+ __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
+} NRF_PU_Type;
+
+
+/* ================================================================================ */
+/* ================ AMLI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AHB Multi-Layer Interface. (AMLI)
+ */
+
+typedef struct { /*!< AMLI Structure */
+ __I uint32_t RESERVED0[896];
+ AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
+} NRF_AMLI_Type;
+
+
+/* ================================================================================ */
+/* ================ RADIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief The radio. (RADIO)
+ */
+
+typedef struct { /*!< RADIO Structure */
+ __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
+ __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
+ __O uint32_t TASKS_START; /*!< Start radio. */
+ __O uint32_t TASKS_STOP; /*!< Stop radio. */
+ __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
+ __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
+ __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
+ __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
+ __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
+ __I uint32_t RESERVED0[55];
+ __IO uint32_t EVENTS_READY; /*!< Ready event. */
+ __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
+ __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
+ __IO uint32_t EVENTS_END; /*!< End event. */
+ __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
+ __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
+ __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
+ __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
+ sample is ready for readout at the RSSISAMPLE register. */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
+ __I uint32_t RESERVED2[53];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
+ __I uint32_t RESERVED3[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED4[61];
+ __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
+ __I uint32_t CD; /*!< Carrier detect. */
+ __I uint32_t RXMATCH; /*!< Received address. */
+ __I uint32_t RXCRC; /*!< Received CRC. */
+ __I uint32_t DAI; /*!< Device address match index. */
+ __I uint32_t RESERVED5[60];
+ __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
+ __IO uint32_t FREQUENCY; /*!< Frequency. */
+ __IO uint32_t TXPOWER; /*!< Output power. */
+ __IO uint32_t MODE; /*!< Data rate and modulation. */
+ __IO uint32_t PCNF0; /*!< Packet configuration 0. */
+ __IO uint32_t PCNF1; /*!< Packet configuration 1. */
+ __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
+ __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
+ __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
+ __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
+ __IO uint32_t TXADDRESS; /*!< Transmit address select. */
+ __IO uint32_t RXADDRESSES; /*!< Receive address select. */
+ __IO uint32_t CRCCNF; /*!< CRC configuration. */
+ __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
+ __IO uint32_t CRCINIT; /*!< CRC initial value. */
+ __IO uint32_t TEST; /*!< Test features enable register. */
+ __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
+ __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
+ __I uint32_t RESERVED6;
+ __I uint32_t STATE; /*!< Current radio state. */
+ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t BCC; /*!< Bit counter compare. */
+ __I uint32_t RESERVED8[39];
+ __IO uint32_t DAB[8]; /*!< Device address base segment. */
+ __IO uint32_t DAP[8]; /*!< Device address prefix. */
+ __IO uint32_t DACNF; /*!< Device address match configuration. */
+ __I uint32_t RESERVED9[56];
+ __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
+ __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
+ __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
+ __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
+ __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
+ __I uint32_t RESERVED10[561];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================ UART ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+ */
+
+typedef struct { /*!< UART Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
+ __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
+ __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
+ __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
+ __I uint32_t RESERVED0[3];
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
+ __I uint32_t RESERVED1[56];
+ __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
+ __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
+ __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
+ __I uint32_t RESERVED2[4];
+ __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
+ __I uint32_t RESERVED3;
+ __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
+ __I uint32_t RESERVED5[46];
+ __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
+ __I uint32_t RESERVED6[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED7[93];
+ __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
+ __I uint32_t RESERVED8[31];
+ __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
+ __I uint32_t RESERVED9;
+ __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
+ __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
+ __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
+ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
+ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
+ Once read the character is consumed. If read when no character
+ available, the UART will stop working. */
+ __O uint32_t TXD; /*!< TXD register. */
+ __I uint32_t RESERVED10;
+ __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
+ __I uint32_t RESERVED11[17];
+ __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
+ __I uint32_t RESERVED12[675];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI master 0. (SPI)
+ */
+
+typedef struct { /*!< SPI Structure */
+ __I uint32_t RESERVED0[66];
+ __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
+ __I uint32_t RESERVED1[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[125];
+ __IO uint32_t ENABLE; /*!< Enable SPI. */
+ __I uint32_t RESERVED3;
+ __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
+ __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
+ __I uint32_t RESERVED4;
+ __I uint32_t RXD; /*!< RX data. */
+ __IO uint32_t TXD; /*!< TX data. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t FREQUENCY; /*!< SPI frequency */
+ __I uint32_t RESERVED6[11];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED7[681];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================ TWI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Two-wire interface master 0. (TWI)
+ */
+
+typedef struct { /*!< TWI Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
+ __I uint32_t RESERVED0;
+ __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
+ __I uint32_t RESERVED2;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
+ __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
+ __I uint32_t RESERVED3[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
+ __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
+ __I uint32_t RESERVED4[4];
+ __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
+ __I uint32_t RESERVED6[4];
+ __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
+ __I uint32_t RESERVED8[45];
+ __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
+ __I uint32_t RESERVED9[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED10[110];
+ __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
+ __I uint32_t RESERVED11[14];
+ __IO uint32_t ENABLE; /*!< Enable two-wire master. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
+ __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
+ __I uint32_t RESERVED13[2];
+ __I uint32_t RXD; /*!< RX data register. */
+ __IO uint32_t TXD; /*!< TX data register. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
+ __I uint32_t RESERVED15[24];
+ __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
+ __I uint32_t RESERVED16[668];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIS ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI slave 1. (SPIS)
+ */
+
+typedef struct { /*!< SPIS Structure */
+ __I uint32_t RESERVED0[9];
+ __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
+ __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
+ __I uint32_t RESERVED1[54];
+ __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
+ __I uint32_t RESERVED2[8];
+ __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
+ __I uint32_t RESERVED3[53];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
+ __I uint32_t RESERVED4[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED5[61];
+ __I uint32_t SEMSTAT; /*!< Semaphore status. */
+ __I uint32_t RESERVED6[15];
+ __IO uint32_t STATUS; /*!< Status from last transaction. */
+ __I uint32_t RESERVED7[47];
+ __IO uint32_t ENABLE; /*!< Enable SPIS. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
+ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
+ __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
+ __I uint32_t RESERVED9[7];
+ __IO uint32_t RXDPTR; /*!< RX data pointer. */
+ __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
+ __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
+ __I uint32_t RESERVED10;
+ __IO uint32_t TXDPTR; /*!< TX data pointer. */
+ __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
+ __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
+ __I uint32_t RESERVED11;
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t DEF; /*!< Default character. */
+ __I uint32_t RESERVED13[24];
+ __IO uint32_t ORC; /*!< Over-read character. */
+ __I uint32_t RESERVED14[654];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI master with easyDMA 1. (SPIM)
+ */
+
+typedef struct { /*!< SPIM Structure */
+ __I uint32_t RESERVED0[4];
+ __O uint32_t TASKS_START; /*!< Start SPI transaction. */
+ __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
+ __I uint32_t RESERVED1;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
+ __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
+ __I uint32_t RESERVED2[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
+ __I uint32_t RESERVED6[10];
+ __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
+ __I uint32_t RESERVED7[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
+ __I uint32_t RESERVED8[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED9[125];
+ __IO uint32_t ENABLE; /*!< Enable SPIM. */
+ __I uint32_t RESERVED10;
+ SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
+ __I uint32_t RESERVED11[4];
+ __IO uint32_t FREQUENCY; /*!< SPI frequency. */
+ __I uint32_t RESERVED12[3];
+ SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED13;
+ SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED15[26];
+ __IO uint32_t ORC; /*!< Over-read character. */
+ __I uint32_t RESERVED16[654];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIOTE ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GPIO tasks and events. (GPIOTE)
+ */
+
+typedef struct { /*!< GPIOTE Structure */
+ __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
+ __I uint32_t RESERVED0[60];
+ __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
+ __I uint32_t RESERVED1[27];
+ __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
+ __I uint32_t RESERVED2[97];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[129];
+ __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
+ __I uint32_t RESERVED4[695];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog to digital converter. (ADC)
+ */
+
+typedef struct { /*!< ADC Structure */
+ __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
+ __O uint32_t TASKS_STOP; /*!< Stop ADC. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[61];
+ __I uint32_t BUSY; /*!< ADC busy register. */
+ __I uint32_t RESERVED3[63];
+ __IO uint32_t ENABLE; /*!< ADC enable. */
+ __IO uint32_t CONFIG; /*!< ADC configuration register. */
+ __I uint32_t RESULT; /*!< Result of ADC conversion. */
+ __I uint32_t RESERVED4[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ TIMER ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Timer 0. (TIMER)
+ */
+
+typedef struct { /*!< TIMER Structure */
+ __O uint32_t TASKS_START; /*!< Start Timer. */
+ __O uint32_t TASKS_STOP; /*!< Stop Timer. */
+ __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
+ __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
+ __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
+ __I uint32_t RESERVED0[11];
+ __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
+ __I uint32_t RESERVED1[60];
+ __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
+ __I uint32_t RESERVED2[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
+ __I uint32_t RESERVED3[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED4[126];
+ __IO uint32_t MODE; /*!< Timer Mode selection. */
+ __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
+ clock frequency is divided by 2^SCALE. */
+ __I uint32_t RESERVED6[11];
+ __IO uint32_t CC[4]; /*!< Capture/compare registers. */
+ __I uint32_t RESERVED7[683];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Real time counter 0. (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+ __O uint32_t TASKS_START; /*!< Start RTC Counter. */
+ __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
+ __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
+ __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
+ __I uint32_t RESERVED0[60];
+ __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
+ __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
+ __I uint32_t RESERVED1[14];
+ __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
+ __I uint32_t RESERVED2[109];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[13];
+ __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
+ __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
+ the value of EVTEN. */
+ __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
+ gives the value of EVTEN. */
+ __I uint32_t RESERVED4[110];
+ __I uint32_t COUNTER; /*!< Current COUNTER value. */
+ __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+ Must be written when RTC is STOPed. */
+ __I uint32_t RESERVED5[13];
+ __IO uint32_t CC[4]; /*!< Capture/compare registers. */
+ __I uint32_t RESERVED6[683];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ TEMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Temperature Sensor. (TEMP)
+ */
+
+typedef struct { /*!< TEMP Structure */
+ __O uint32_t TASKS_START; /*!< Start temperature measurement. */
+ __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[127];
+ __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
+ __I uint32_t RESERVED3[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================ RNG ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Random Number Generator. (RNG)
+ */
+
+typedef struct { /*!< RNG Structure */
+ __O uint32_t TASKS_START; /*!< Start the random number generator. */
+ __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
+ __I uint32_t RESERVED1[63];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
+ __I uint32_t RESERVED3[126];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t VALUE; /*!< RNG random number. */
+ __I uint32_t RESERVED4[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================ ECB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AES ECB Mode Encryption. (ECB)
+ */
+
+typedef struct { /*!< ECB Structure */
+ __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
+ will not initiate a new encryption and the ERRORECB event will
+ be triggered. */
+ __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
+ this will will trigger the ERRORECB event. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
+ __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
+ error. */
+ __I uint32_t RESERVED1[127];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
+ __I uint32_t RESERVED3[701];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================ AAR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Accelerated Address Resolver. (AAR)
+ */
+
+typedef struct { /*!< AAR Structure */
+ __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
+ data structure. */
+ __I uint32_t RESERVED0;
+ __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
+ __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
+ __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t STATUS; /*!< Resolution status. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< Enable AAR. */
+ __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
+ __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 3 bytes must be reserved. */
+ __I uint32_t RESERVED6[697];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================ CCM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AES CCM Mode Encryption. (CCM)
+ */
+
+typedef struct { /*!< CCM Structure */
+ __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
+ itself when completed. */
+ __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
+ completed. */
+ __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
+ __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
+ __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< CCM enable. */
+ __IO uint32_t MODE; /*!< Operation mode. */
+ __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
+ __IO uint32_t INPTR; /*!< Pointer to the input packet. */
+ __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 43 bytes must be reserved. */
+ __I uint32_t RESERVED5[697];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================ WDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Watchdog Timer. (WDT)
+ */
+
+typedef struct { /*!< WDT Structure */
+ __O uint32_t TASKS_START; /*!< Start the watchdog. */
+ __I uint32_t RESERVED0[63];
+ __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[61];
+ __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
+ __I uint32_t REQSTATUS; /*!< Request status. */
+ __I uint32_t RESERVED3[63];
+ __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
+ __IO uint32_t RREN; /*!< Reload request enable. */
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED4[60];
+ __O uint32_t RR[8]; /*!< Reload requests registers. */
+ __I uint32_t RESERVED5[631];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================ QDEC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Rotary decoder. (QDEC)
+ */
+
+typedef struct { /*!< QDEC Structure */
+ __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
+ __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
+ __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
+ and clears the ACC registers. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
+ __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
+ ACC register different than zero. */
+ __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[125];
+ __IO uint32_t ENABLE; /*!< Enable the QDEC. */
+ __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
+ __IO uint32_t SAMPLEPER; /*!< Sample period. */
+ __I int32_t SAMPLE; /*!< Motion sample value. */
+ __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
+ __I int32_t ACC; /*!< Accumulated valid transitions register. */
+ __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
+ task. */
+ __IO uint32_t PSELLED; /*!< Pin select for LED output. */
+ __IO uint32_t PSELA; /*!< Pin select for phase A input. */
+ __IO uint32_t PSELB; /*!< Pin select for phase B input. */
+ __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
+ __I uint32_t RESERVED4[5];
+ __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
+ __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
+ __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
+ task. */
+ __I uint32_t RESERVED5[684];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================ LPCOMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Low power comparator. (LPCOMP)
+ */
+
+typedef struct { /*!< LPCOMP Structure */
+ __O uint32_t TASKS_START; /*!< Start the comparator. */
+ __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
+ __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
+ __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
+ __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
+ __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
+ __I uint32_t RESERVED1[60];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t RESULT; /*!< Result of last compare. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
+ __IO uint32_t PSEL; /*!< Input pin select. */
+ __IO uint32_t REFSEL; /*!< Reference select. */
+ __IO uint32_t EXTREFSEL; /*!< External reference select. */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
+ __I uint32_t RESERVED6[694];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================ SWI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SW Interrupts. (SWI)
+ */
+
+typedef struct { /*!< SWI Structure */
+ __I uint32_t UNUSED; /*!< Unused. */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================ NVMC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Non Volatile Memory Controller. (NVMC)
+ */
+
+typedef struct { /*!< NVMC Structure */
+ __I uint32_t RESERVED0[256];
+ __I uint32_t READY; /*!< Ready flag. */
+ __I uint32_t RESERVED1[64];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+
+ union {
+ __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
+ __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
+ };
+ __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
+
+ union {
+ __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
+ __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
+ };
+ __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================ PPI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief PPI controller. (PPI)
+ */
+
+typedef struct { /*!< PPI Structure */
+ PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
+ __I uint32_t RESERVED0[312];
+ __IO uint32_t CHEN; /*!< Channel enable. */
+ __IO uint32_t CHENSET; /*!< Channel enable set. */
+ __IO uint32_t CHENCLR; /*!< Channel enable clear. */
+ __I uint32_t RESERVED1;
+ PPI_CH_Type CH[16]; /*!< PPI Channel. */
+ __I uint32_t RESERVED2[156];
+ __IO uint32_t CHG[4]; /*!< Channel group configuration. */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================ FICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Factory Information Configuration. (FICR)
+ */
+
+typedef struct { /*!< FICR Structure */
+ __I uint32_t RESERVED0[4];
+ __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
+ __I uint32_t CODESIZE; /*!< Code memory size in pages. */
+ __I uint32_t RESERVED1[4];
+ __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
+ __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
+ __I uint32_t RESERVED2;
+ __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
+
+ union {
+ __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
+ kept for backward compatinility purposes. Use SIZERAMBLOCKS
+ instead. */
+ __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
+ };
+ __I uint32_t RESERVED3[5];
+ __I uint32_t CONFIGID; /*!< Configuration identifier. */
+ __I uint32_t DEVICEID[2]; /*!< Device identifier. */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t ER[4]; /*!< Encryption root. */
+ __I uint32_t IR[4]; /*!< Identity root. */
+ __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
+ __I uint32_t DEVICEADDR[2]; /*!< Device address. */
+ __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
+ __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+ mode. */
+ __I uint32_t RESERVED5[10];
+ __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
+ mode. */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================ UICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief User Information Configuration. (UICR)
+ */
+
+typedef struct { /*!< UICR Structure */
+ __IO uint32_t CLENR0; /*!< Length of code region 0. */
+ __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
+ __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
+ __I uint32_t RESERVED0;
+ __I uint32_t FWID; /*!< Firmware ID. */
+
+ union {
+ __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
+ __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
+ };
+ __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
+ __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General purpose input and output. (GPIO)
+ */
+
+typedef struct { /*!< GPIO Structure */
+ __I uint32_t RESERVED0[321];
+ __IO uint32_t OUT; /*!< Write GPIO port. */
+ __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
+ __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
+ __I uint32_t IN; /*!< Read GPIO port. */
+ __IO uint32_t DIR; /*!< Direction of GPIO pins. */
+ __IO uint32_t DIRSET; /*!< DIR set register. */
+ __IO uint32_t DIRCLR; /*!< DIR clear register. */
+ __I uint32_t RESERVED1[120];
+ __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
+} NRF_GPIO_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_MPU_BASE 0x40000000UL
+#define NRF_PU_BASE 0x40000000UL
+#define NRF_AMLI_BASE 0x40000000UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_SPI0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_SPI1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
+#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_SPIM1_BASE 0x40004000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_ADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
+#define NRF_LPCOMP_BASE 0x40013000UL
+#define NRF_SWI_BASE 0x40014000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_GPIO_BASE 0x50000000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
+#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
+#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
+#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
+#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
+#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
+#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
+#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
+#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
+#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
+#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
+#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
+#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
+#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf51 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* nrf51_H */
+
diff --git a/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h b/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h new file mode 100644 index 0000000..0ab4598 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h @@ -0,0 +1,7088 @@ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef __NRF51_BITS_H +#define __NRF51_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver. */ + +/* Register: AAR_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on RESOLVED event. */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: AAR_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on RESOLVED event. */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status. */ + +/* Bits 3..0 : The IRK used last time an address was resolved. */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR. */ + +/* Bits 1..0 : Enable AAR. */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ +#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ + +/* Register: AAR_NIRK */ +/* Description: Number of Identity root Keys in the IRK data structure. */ + +/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: ADC */ +/* Description: Analog to digital converter. */ + +/* Register: ADC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ADC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on END event. */ +#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ADC_BUSY */ +/* Description: ADC busy register. */ + +/* Bit 0 : ADC busy register. */ +#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ +#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ +#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ +#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ + +/* Register: ADC_ENABLE */ +/* Description: ADC enable. */ + +/* Bits 1..0 : ADC enable. */ +#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ +#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ + +/* Register: ADC_CONFIG */ +/* Description: ADC configuration register. */ + +/* Bits 17..16 : ADC external reference pin selection. */ +#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ + +/* Bits 15..8 : ADC analog pin selection. */ +#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ +#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ + +/* Bits 6..5 : ADC reference selection. */ +#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ +#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ +#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ +#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ +#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ + +/* Bits 4..2 : ADC input selection. */ +#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ +#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ +#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ + +/* Bits 1..0 : ADC resolution. */ +#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ +#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ +#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ +#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ +#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ + +/* Register: ADC_RESULT */ +/* Description: Result of ADC conversion. */ + +/* Bits 9..0 : Result of ADC conversion. */ +#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + +/* Register: ADC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: AMLI */ +/* Description: AHB Multi-Layer Interface. */ + +/* Register: AMLI_RAMPRI_CPU0 */ +/* Description: Configurable priority configuration register for CPU0. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_SPIS1 */ +/* Description: Configurable priority configuration register for SPIS1. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_RADIO */ +/* Description: Configurable priority configuration register for RADIO. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_ECB */ +/* Description: Configurable priority configuration register for ECB. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_CCM */ +/* Description: Configurable priority configuration register for CCM. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_AAR */ +/* Description: Configurable priority configuration register for AAR. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption. */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts for the CCM. */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: CCM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ERROR event. */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ENDCRYPT event. */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDKSGEN event. */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CCM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ERROR event. */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ENDCRYPT event. */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CCM_MICSTATUS */ +/* Description: CCM RX MIC check result. */ + +/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ + +/* Register: CCM_ENABLE */ +/* Description: CCM enable. */ + +/* Bits 1..0 : CCM enable. */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ +#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ + +/* Register: CCM_MODE */ +/* Description: Operation mode. */ + +/* Bit 0 : CCM mode operation. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ + +/* Register: CCM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control. */ + +/* Register: CLOCK_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 4 : Enable interrupt on CTTO event. */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on DONE event. */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 4 : Disable interrupt on CTTO event. */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on DONE event. */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: High frequency clock status. */ + +/* Bit 16 : State for the HFCLK. */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ + +/* Bit 0 : Active clock source for the HF clock. */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: Low frequency clock status. */ + +/* Bit 16 : State for the LF clock. */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ + +/* Bits 1..0 : Active clock source for the LF clock. */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK clock. */ + +/* Bits 1..0 : Clock source. */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval. */ + +/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_XTALFREQ */ +/* Description: Crystal frequency. */ + +/* Bits 7..0 : External Xtal frequency selection. */ +#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption. */ + +/* Register: ECB_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 1 : Enable interrupt on ERRORECB event. */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDECB event. */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ECB_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 1 : Disable interrupt on ERRORECB event. */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDECB event. */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ECB_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration. */ + +/* Register: FICR_PPFC */ +/* Description: Pre-programmed factory code present. */ + +/* Bits 7..0 : Pre-programmed factory code present. */ +#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ +#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ +#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ +#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ + +/* Register: FICR_CONFIGID */ +/* Description: Configuration identifier. */ + +/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ +#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ +#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ + +/* Bits 15..0 : Hardware Identification Number. */ +#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ +#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type. */ + +/* Bit 0 : Device address type. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ + +/* Register: FICR_OVERRIDEEN */ +/* Description: Radio calibration override enable. */ + +/* Bit 3 : Override default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ + +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + + +/* Peripheral: GPIO */ +/* Description: General purpose input and output. */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register. */ + +/* Bit 31 : Set as output pin 31. */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ + +/* Bit 30 : Set as output pin 30. */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ + +/* Bit 29 : Set as output pin 29. */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ + +/* Bit 28 : Set as output pin 28. */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ + +/* Bit 27 : Set as output pin 27. */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ + +/* Bit 26 : Set as output pin 26. */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ + +/* Bit 25 : Set as output pin 25. */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ + +/* Bit 24 : Set as output pin 24. */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ + +/* Bit 23 : Set as output pin 23. */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ + +/* Bit 22 : Set as output pin 22. */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ + +/* Bit 21 : Set as output pin 21. */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ + +/* Bit 20 : Set as output pin 20. */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ + +/* Bit 19 : Set as output pin 19. */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ + +/* Bit 18 : Set as output pin 18. */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ + +/* Bit 17 : Set as output pin 17. */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ + +/* Bit 16 : Set as output pin 16. */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ + +/* Bit 15 : Set as output pin 15. */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ + +/* Bit 14 : Set as output pin 14. */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ + +/* Bit 13 : Set as output pin 13. */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ + +/* Bit 12 : Set as output pin 12. */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ + +/* Bit 11 : Set as output pin 11. */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ + +/* Bit 10 : Set as output pin 10. */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ + +/* Bit 9 : Set as output pin 9. */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ + +/* Bit 8 : Set as output pin 8. */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ + +/* Bit 7 : Set as output pin 7. */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ + +/* Bit 6 : Set as output pin 6. */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ + +/* Bit 5 : Set as output pin 5. */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ + +/* Bit 4 : Set as output pin 4. */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ + +/* Bit 3 : Set as output pin 3. */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ + +/* Bit 2 : Set as output pin 2. */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ + +/* Bit 1 : Set as output pin 1. */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ + +/* Bit 0 : Set as output pin 0. */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register. */ + +/* Bit 31 : Set as input pin 31. */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 30 : Set as input pin 30. */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 29 : Set as input pin 29. */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 28 : Set as input pin 28. */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 27 : Set as input pin 27. */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 26 : Set as input pin 26. */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 25 : Set as input pin 25. */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 24 : Set as input pin 24. */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 23 : Set as input pin 23. */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 22 : Set as input pin 22. */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 21 : Set as input pin 21. */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 20 : Set as input pin 20. */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 19 : Set as input pin 19. */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 18 : Set as input pin 18. */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 17 : Set as input pin 17. */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 16 : Set as input pin 16. */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 15 : Set as input pin 15. */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 14 : Set as input pin 14. */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 13 : Set as input pin 13. */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 12 : Set as input pin 12. */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 11 : Set as input pin 11. */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 10 : Set as input pin 10. */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 9 : Set as input pin 9. */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 8 : Set as input pin 8. */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 7 : Set as input pin 7. */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 6 : Set as input pin 6. */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 5 : Set as input pin 5. */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 4 : Set as input pin 4. */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 3 : Set as input pin 3. */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 2 : Set as input pin 2. */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 1 : Set as input pin 1. */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 0 : Set as input pin 0. */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Configuration of GPIO pins. */ + +/* Bits 17..16 : Pin sensing mechanism. */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ +#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ + +/* Bits 10..8 : Drive configuration. */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ + +/* Bits 3..2 : Pull-up or -down configuration. */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ +#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ +#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ + +/* Bit 1 : Connect or disconnect input path. */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ + +/* Bit 0 : Pin direction. */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO tasks and events. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 31 : Enable interrupt on PORT event. */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on IN[3] event. */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on IN[2] event. */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on IN[1] event. */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on IN[0] event. */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 31 : Disable interrupt on PORT event. */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on IN[3] event. */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on IN[2] event. */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on IN[1] event. */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on IN[0] event. */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Channel configuration registers. */ + +/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ + +/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ + +/* Bits 12..8 : Pin select. */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ +#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ + +/* Register: GPIOTE_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low power comparator. */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcuts for the LPCOMP. */ + +/* Bit 4 : Shortcut between CROSS event and STOP task. */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between UP event and STOP task. */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DOWN event and STOP task. */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between RADY event and STOP task. */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 3 : Enable interrupt on CROSS event. */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on UP event. */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on DOWN event. */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 3 : Disable interrupt on CROSS event. */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on UP event. */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on DOWN event. */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: LPCOMP_RESULT */ +/* Description: Result of last compare. */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable the LPCOMP. */ + +/* Bits 1..0 : Enable or disable LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select. */ + +/* Bits 2..0 : Analog input pin select. */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select. */ + +/* Bits 2..0 : Reference select. */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select. */ + +/* Bit 0 : External analog reference pin selection. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration. */ + +/* Bits 1..0 : Analog detect configuration. */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ + +/* Register: LPCOMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: MPU */ +/* Description: Memory Protection Unit. */ + +/* Register: MPU_PERR0 */ +/* Description: Configuration of peripherals in mpu regions. */ + +/* Bit 31 : PPI region configuration. */ +#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ +#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ +#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 30 : NVMC region configuration. */ +#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ +#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ +#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 18 : QDEC region configuration. */ +#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ +#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ +#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 17 : RTC1 region configuration. */ +#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ +#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ +#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 16 : WDT region configuration. */ +#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ +#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ +#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 15 : CCM and AAR region configuration. */ +#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 14 : ECB region configuration. */ +#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ +#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ +#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 13 : RNG region configuration. */ +#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ +#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ +#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 12 : TEMP region configuration. */ +#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ +#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ +#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 11 : RTC0 region configuration. */ +#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ +#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ +#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 10 : TIMER2 region configuration. */ +#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ +#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ +#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 9 : TIMER1 region configuration. */ +#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ +#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ +#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 8 : TIMER0 region configuration. */ +#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ +#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ +#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 7 : ADC region configuration. */ +#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ +#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ +#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 6 : GPIOTE region configuration. */ +#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 4 : SPI1 and TWI1 region configuration. */ +#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 3 : SPI0 and TWI0 region configuration. */ +#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 2 : UART0 region configuration. */ +#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ +#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ +#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 1 : RADIO region configuration. */ +#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ +#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ +#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 0 : POWER_CLOCK region configuration. */ +#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Register: MPU_PROTENSET0 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 31. */ +#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 30. */ +#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 29. */ +#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 28. */ +#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 27. */ +#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 26. */ +#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 25. */ +#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 24. */ +#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 23. */ +#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 22. */ +#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 21. */ +#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 20. */ +#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 19. */ +#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 18. */ +#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 17. */ +#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 16. */ +#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 15. */ +#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 14. */ +#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 13. */ +#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 12. */ +#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 11. */ +#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 10. */ +#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 9. */ +#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 8. */ +#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 7. */ +#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 6. */ +#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 5. */ +#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 4. */ +#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 3. */ +#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 2. */ +#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 1. */ +#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 0. */ +#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_PROTENSET1 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 63. */ +#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 62. */ +#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 61. */ +#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 60. */ +#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 59. */ +#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 58. */ +#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 57. */ +#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 56. */ +#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 55. */ +#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 54. */ +#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 53. */ +#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 52. */ +#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 51. */ +#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 50. */ +#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 49. */ +#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 48. */ +#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 47. */ +#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 46. */ +#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 45. */ +#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 44. */ +#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 43. */ +#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 42. */ +#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 41. */ +#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 40. */ +#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 39. */ +#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 38. */ +#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 37. */ +#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 36. */ +#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 35. */ +#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 34. */ +#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 33. */ +#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 32. */ +#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_DISABLEINDEBUG */ +/* Description: Disable erase and write protection mechanism in debug mode. */ + +/* Bit 0 : Disable protection mechanism in debug mode. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ + +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller. */ + +/* Register: NVMC_READY */ +/* Description: Ready flag. */ + +/* Bit 0 : NVMC ready. */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register. */ + +/* Bits 1..0 : Program write enable. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ +#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ +#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory. */ + +/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for start erasing User Information Congfiguration Registers. */ + +/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ + + +/* Peripheral: POWER */ +/* Description: Power Control. */ + +/* Register: POWER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on POFWARN event. */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: POWER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on POFWARN event. */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason. */ + +/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 3 : Reset from CPU lock-up detected. */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ + +/* Bit 1 : Reset from watchdog detected. */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ + +/* Bit 0 : Reset from pin-reset detected. */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System off register. */ + +/* Bit 0 : Enter system off mode. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ + +/* Register: POWER_POFCON */ +/* Description: Power failure configuration. */ + +/* Bits 2..1 : Set threshold level. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ +#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ +#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ +#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ + +/* Bit 0 : Power failure comparator enable. */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register. This register is a retained register. */ + +/* Bits 7..0 : General purpose retention register. */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 1 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ + +/* Bit 16 : RAM block 0 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ + +/* Bit 1 : RAM block 1 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ + +/* Bit 0 : RAM block 0 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ + +/* Register: POWER_RESET */ +/* Description: Pin reset functionality configuration register. This register is a retained register. */ + +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ +#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ +#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ +#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ +#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ + +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + +/* Register: POWER_DCDCEN */ +/* Description: DCDC converter enable configuration register. */ + +/* Bit 0 : Enable DCDC converter. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ + +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + + +/* Peripheral: PPI */ +/* Description: PPI controller. */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear. */ + +/* Bit 31 : Disable PPI channel 31. */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 30 : Disable PPI channel 30. */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 29 : Disable PPI channel 29. */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 28 : Disable PPI channel 28. */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 27 : Disable PPI channel 27. */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 26 : Disable PPI channel 26. */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 25 : Disable PPI channel 25. */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 24 : Disable PPI channel 24. */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 23 : Disable PPI channel 23. */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 22 : Disable PPI channel 22. */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 21 : Disable PPI channel 21. */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 20 : Disable PPI channel 20. */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 15 : Disable PPI channel 15. */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 14 : Disable PPI channel 14. */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 13 : Disable PPI channel 13. */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 12 : Disable PPI channel 12. */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 11 : Disable PPI channel 11. */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 10 : Disable PPI channel 10. */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 9 : Disable PPI channel 9. */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 8 : Disable PPI channel 8. */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 7 : Disable PPI channel 7. */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 6 : Disable PPI channel 6. */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 5 : Disable PPI channel 5. */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 4 : Disable PPI channel 4. */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 3 : Disable PPI channel 3. */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 2 : Disable PPI channel 2. */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 1 : Disable PPI channel 1. */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 0 : Disable PPI channel 0. */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ + +/* Register: PPI_CHG */ +/* Description: Channel group configuration. */ + +/* Bit 31 : Include CH31 in channel group. */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ + +/* Bit 30 : Include CH30 in channel group. */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ + +/* Bit 29 : Include CH29 in channel group. */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ + +/* Bit 28 : Include CH28 in channel group. */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ + +/* Bit 27 : Include CH27 in channel group. */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ + +/* Bit 26 : Include CH26 in channel group. */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ + +/* Bit 25 : Include CH25 in channel group. */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ + +/* Bit 24 : Include CH24 in channel group. */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ + +/* Bit 23 : Include CH23 in channel group. */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ + +/* Bit 22 : Include CH22 in channel group. */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ + +/* Bit 21 : Include CH21 in channel group. */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ + +/* Bit 20 : Include CH20 in channel group. */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ + +/* Bit 15 : Include CH15 in channel group. */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ + +/* Bit 14 : Include CH14 in channel group. */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ + +/* Bit 13 : Include CH13 in channel group. */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ + +/* Bit 12 : Include CH12 in channel group. */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ + +/* Bit 11 : Include CH11 in channel group. */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ + +/* Bit 10 : Include CH10 in channel group. */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ + +/* Bit 9 : Include CH9 in channel group. */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ + +/* Bit 8 : Include CH8 in channel group. */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ + +/* Bit 7 : Include CH7 in channel group. */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ + +/* Bit 6 : Include CH6 in channel group. */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ + +/* Bit 5 : Include CH5 in channel group. */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ + +/* Bit 4 : Include CH4 in channel group. */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ + +/* Bit 3 : Include CH3 in channel group. */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ + +/* Bit 2 : Include CH2 in channel group. */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ + +/* Bit 1 : Include CH1 in channel group. */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ + +/* Bit 0 : Include CH0 in channel group. */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ + + +/* Peripheral: PU */ +/* Description: Patch unit. */ + +/* Register: PU_PATCHADDR */ +/* Description: Relative address of patch instructions. */ + +/* Bits 24..0 : Relative address of patch instructions. */ +#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */ +#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */ + +/* Register: PU_PATCHEN */ +/* Description: Patch enable register. */ + +/* Bit 7 : Patch 7 enabled. */ +#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ +#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ +#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 6 : Patch 6 enabled. */ +#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ +#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ +#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 5 : Patch 5 enabled. */ +#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ +#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ +#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 4 : Patch 4 enabled. */ +#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ +#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ +#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 3 : Patch 3 enabled. */ +#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ +#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ +#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 2 : Patch 2 enabled. */ +#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ +#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ +#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 1 : Patch 1 enabled. */ +#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ +#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ +#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */ + +/* Bit 0 : Patch 0 enabled. */ +#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ +#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ +#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */ + +/* Register: PU_PATCHENSET */ +/* Description: Patch enable register. */ + +/* Bit 7 : Patch 7 enabled. */ +#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ +#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ +#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 6 : Patch 6 enabled. */ +#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ +#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ +#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 5 : Patch 5 enabled. */ +#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ +#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ +#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 4 : Patch 4 enabled. */ +#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ +#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ +#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 3 : Patch 3 enabled. */ +#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ +#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ +#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 2 : Patch 2 enabled. */ +#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ +#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ +#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 1 : Patch 1 enabled. */ +#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ +#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ +#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */ + +/* Bit 0 : Patch 0 enabled. */ +#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ +#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ +#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */ + +/* Register: PU_PATCHENCLR */ +/* Description: Patch disable register. */ + +/* Bit 7 : Patch 7 enabled. */ +#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ +#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ +#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 6 : Patch 6 enabled. */ +#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ +#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ +#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 5 : Patch 5 enabled. */ +#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ +#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ +#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 4 : Patch 4 enabled. */ +#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ +#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ +#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 3 : Patch 3 enabled. */ +#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ +#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ +#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 2 : Patch 2 enabled. */ +#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ +#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ +#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 1 : Patch 1 enabled. */ +#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ +#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ +#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */ + +/* Bit 0 : Patch 0 enabled. */ +#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ +#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ +#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */ +#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */ +#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */ + + +/* Peripheral: QDEC */ +/* Description: Rotary decoder. */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts for the QDEC. */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: QDEC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ACCOF event. */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on REPORTRDY event. */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on SAMPLERDY event. */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: QDEC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ACCOF event. */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on REPORTRDY event. */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on SAMPLERDY event. */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the QDEC. */ + +/* Bit 0 : Enable or disable QDEC. */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity. */ + +/* Bit 0 : LED output pin polarity. */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period. */ + +/* Bits 2..0 : Sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value. */ + +/* Bits 31..0 : Last sample taken in compliment to 2. */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to generate an EVENT_REPORTRDY. */ + +/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable debouncer input filters. */ + +/* Bit 0 : Enable debounce input filters. */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time LED is switched ON before the sample. */ + +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Accumulated double (error) transitions register. */ + +/* Bits 3..0 : Accumulated double (error) transitions. */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ + +/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + +/* Register: QDEC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RADIO */ +/* Description: The radio. */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts for the radio. */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 5 : Shortcut between END event and START task. */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between END event and DISABLE task. */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and START task. */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RADIO_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on BCMATCH event. */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on RSSIEND event. */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on DEVMISS event. */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 5 : Enable interrupt on DEVMATCH event. */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on DISABLED event. */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on END event. */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on PAYLOAD event. */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ADDRESS event. */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RADIO_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on BCMATCH event. */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on RSSIEND event. */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on DEVMISS event. */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 5 : Disable interrupt on DEVMATCH event. */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on DISABLED event. */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on END event. */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on PAYLOAD event. */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ADDRESS event. */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status of received packet. */ + +/* Bit 0 : CRC status of received packet. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ + +/* Register: RADIO_CD */ +/* Description: Carrier detect. */ + +/* Bit 0 : Carrier detect. */ +#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ +#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address. */ + +/* Bits 2..0 : Logical address in which previous packet was received. */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: Received CRC. */ + +/* Bits 23..0 : CRC field of previously received packet. */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index. */ + +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency. */ + +/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power. */ + +/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation. */ + +/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration 0. */ + +/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration 1. */ + +/* Bit 25 : Packet whitening enable. */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ + +/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0 to 3. */ + +/* Bits 31..24 : Address prefix 3. Decision point: START task. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. Decision point: START task. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. Decision point: START task. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. Decision point: START task. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4 to 7. */ + +/* Bits 31..24 : Address prefix 7. Decision point: START task. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. Decision point: START task. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. Decision point: START task. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. Decision point: START task. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select. */ + +/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select. */ + +/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration. */ + +/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length. Decision point: START task. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial. */ + +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value. */ + +/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TEST */ +/* Description: Test features enable register. */ + +/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ + +/* Bit 0 : Constant carrier. Decision point: TXEN task. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in microseconds. */ + +/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample. */ + +/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state. */ + +/* Bits 3..0 : Current radio state. */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ +#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ +#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ +#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ +#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ +#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ +#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ +#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ +#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value. */ + +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_DAP */ +/* Description: Device address prefix. */ + +/* Bits 15..0 : Device address prefix. */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration. */ + +/* Bit 15 : TxAdd for device address 7. */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6. */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5. */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4. */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3. */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2. */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1. */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0. */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7. */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ + +/* Bit 6 : Enable or disable device address matching using device address 6. */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ + +/* Bit 5 : Enable or disable device address matching using device address 5. */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ + +/* Bit 4 : Enable or disable device address matching using device address 4. */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ + +/* Bit 3 : Enable or disable device address matching using device address 3. */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ + +/* Bit 2 : Enable or disable device address matching using device address 2. */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ + +/* Bit 1 : Enable or disable device address matching using device address 1. */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ + +/* Bit 0 : Enable or disable device address matching using device address 0. */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ + +/* Register: RADIO_OVERRIDE0 */ +/* Description: Trim value override register 0. */ + +/* Bits 31..0 : Trim value override 0. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ + +/* Register: RADIO_OVERRIDE1 */ +/* Description: Trim value override register 1. */ + +/* Bits 31..0 : Trim value override 1. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ + +/* Register: RADIO_OVERRIDE2 */ +/* Description: Trim value override register 2. */ + +/* Bits 31..0 : Trim value override 2. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ + +/* Register: RADIO_OVERRIDE3 */ +/* Description: Trim value override register 3. */ + +/* Bits 31..0 : Trim value override 3. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ + +/* Register: RADIO_OVERRIDE4 */ +/* Description: Trim value override register 4. */ + +/* Bit 31 : Enable or disable override of default trim values. */ +#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ +#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ + +/* Bits 27..0 : Trim value override 4. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator. */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts for the RNG. */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RNG_INTENSET */ +/* Description: Interrupt enable set register */ + +/* Bit 0 : Enable interrupt on VALRDY event. */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RNG_INTENCLR */ +/* Description: Interrupt enable clear register */ + +/* Bit 0 : Disable interrupt on VALRDY event. */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 0 : Digital error correction enable. */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ + +/* Register: RNG_VALUE */ +/* Description: RNG random number. */ + +/* Bits 7..0 : Generated random number. */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + +/* Register: RNG_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0. */ + +/* Register: RTC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] event. */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] event. */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] event. */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] event. */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on OVRFLW event. */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on TICK event. */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RTC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] event. */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] event. */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] event. */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] event. */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on OVRFLW event. */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on TICK event. */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RTC_EVTEN */ +/* Description: Configures event enable routing to PPI for each RTC event. */ + +/* Bit 19 : COMPARE[3] event enable. */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 18 : COMPARE[2] event enable. */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 17 : COMPARE[1] event enable. */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 16 : COMPARE[0] event enable. */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 1 : OVRFLW event enable. */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 0 : TICK event enable. */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ + +/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ + +/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ + +/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ + +/* Bit 1 : Enable routing to PPI of OVRFLW event. */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ + +/* Bit 0 : Enable routing to PPI of TICK event. */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 1 : Disable routing to PPI of OVRFLW event. */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 0 : Disable routing to PPI of TICK event. */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value. */ + +/* Bits 23..0 : Counter value. */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ + +/* Bits 11..0 : RTC PRESCALER value. */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Capture/compare registers. */ + +/* Bits 23..0 : Compare value. */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + +/* Register: RTC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPI */ +/* Description: SPI master 0. */ + +/* Register: SPI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on READY event. */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI. */ + +/* Bits 2..0 : Enable or disable SPI. */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ +#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ + +/* Register: SPI_RXD */ +/* Description: RX data. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TX data. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI data rate. */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts for SPIM. */ + +/* Bit 17 : Shortcut between END event and START task. */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on END event. */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on END event. */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPIS */ +/* Description: SPI slave 1. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts for SPIS. */ + +/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIS_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on ACQUIRED event. */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on END event. */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIS_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on ACQUIRED event. */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on END event. */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status. */ + +/* Bits 1..0 : Semaphore status. */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction. */ + +/* Bit 1 : RX buffer overflow detected, and prevented. */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ + +/* Bit 0 : TX buffer overread detected, and prevented. */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPIS. */ + +/* Bits 2..0 : Enable or disable SPIS. */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ +#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ + +/* Register: SPIS_MAXRX */ +/* Description: Maximum number of bytes in the receive buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ +#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ +#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ + +/* Register: SPIS_AMOUNTRX */ +/* Description: Number of bytes received in last granted transaction. */ + +/* Bits 7..0 : Number of bytes received in last granted transaction. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ + +/* Register: SPIS_MAXTX */ +/* Description: Maximum number of bytes in the transmit buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ +#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ +#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ + +/* Register: SPIS_AMOUNTTX */ +/* Description: Number of bytes transmitted in last granted transaction. */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIS_DEF */ +/* Description: Default character. */ + +/* Bits 7..0 : Default character. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIS_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor. */ + +/* Register: TEMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on DATARDY event. */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TEMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on DATARDY event. */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TEMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TIMER */ +/* Description: Timer 0. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts for Timer. */ + +/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TIMER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TIMER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TIMER_MODE */ +/* Description: Timer Mode selection. */ + +/* Bit 0 : Select Normal or Counter mode. */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ + +/* Register: TIMER_BITMODE */ +/* Description: Sets timer behaviour. */ + +/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ + +/* Register: TIMER_PRESCALER */ +/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ + +/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TWI */ +/* Description: Two-wire interface master 0. */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts for TWI. */ + +/* Bit 1 : Shortcut between BB event and the STOP task. */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TWI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 14 : Enable interrupt on BB event. */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXDSENT event. */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TWI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 14 : Disable interrupt on BB event. */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXDSENT event. */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXDREADY event. */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TWI_ERRORSRC */ +/* Description: Two-wire error source. Write error field to 1 to clear error. */ + +/* Bit 2 : NACK received after sending a data byte. */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : NACK received after sending the address. */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: TWI_ENABLE */ +/* Description: Enable two-wire master. */ + +/* Bits 2..0 : Enable or disable W2M */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ +#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ + +/* Register: TWI_RXD */ +/* Description: RX data register. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TX data register. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: Two-wire frequency. */ + +/* Bits 31..0 : Two-wire master clock frequency. */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the two-wire transfer. */ + +/* Bits 6..0 : Two-wire address. */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter. */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts for UART. */ + +/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CTS event and the STARTRX task. */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: UART_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 17 : Enable interrupt on RXTO event. */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXRDY event. */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on RXRDY event. */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on NCTS event. */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on CTS event. */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: UART_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 17 : Disable interrupt on RXTO event. */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXRDY event. */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXRDY event. */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on NCTS event. */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on CTS event. */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source. Write error field to 1 to clear error. */ + +/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART and acquire IOs. */ + +/* Bits 2..0 : Enable or disable UART and acquire IOs. */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ +#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ + +/* Register: UART_RXD */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ + +/* Bits 7..0 : RX data from previous transfer. Double buffered. */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data for transfer. */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: UART Baudrate. */ + +/* Bits 31..0 : UART baudrate. */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control register. */ + +/* Bits 3..1 : Include parity bit. */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ +#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ + +/* Bit 0 : Hardware flow control. */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ + +/* Register: UART_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration. */ + +/* Register: UICR_RBPCONF */ +/* Description: Readback protection configuration. */ + +/* Bits 15..8 : Readback protect all code in the device. */ +#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ +#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ + +/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ +#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ +#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ +#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ + +/* Register: UICR_XTALFREQ */ +/* Description: Reset value for CLOCK XTALFREQ register. */ + +/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ +#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ +#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ + +/* Register: UICR_FWID */ +/* Description: Firmware ID. */ + +/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ +#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ +#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer. */ + +/* Register: WDT_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on TIMEOUT event. */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: WDT_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on TIMEOUT event. */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Watchdog running status. */ + +/* Bit 0 : Watchdog running status. */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status. */ + +/* Bit 7 : Request status for RR[7]. */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ + +/* Bit 6 : Request status for RR[6]. */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ + +/* Bit 5 : Request status for RR[5]. */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ + +/* Bit 4 : Request status for RR[4]. */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ + +/* Bit 3 : Request status for RR[3]. */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ + +/* Bit 2 : Request status for RR[2]. */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ + +/* Bit 1 : Request status for RR[1]. */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ + +/* Bit 0 : Request status for RR[0]. */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ + +/* Register: WDT_RREN */ +/* Description: Reload request enable. */ + +/* Bit 7 : Enable or disable RR[7] register. */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ + +/* Bit 6 : Enable or disable RR[6] register. */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ + +/* Bit 5 : Enable or disable RR[5] register. */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ + +/* Bit 4 : Enable or disable RR[4] register. */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ + +/* Bit 3 : Enable or disable RR[3] register. */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ + +/* Bit 2 : Enable or disable RR[2] register. */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ + +/* Bit 1 : Enable or disable RR[1] register. */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ + +/* Bit 0 : Enable or disable RR[0] register. */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ + +/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ + +/* Register: WDT_RR */ +/* Description: Reload requests registers. */ + +/* Bits 31..0 : Reload register. */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ + +/* Register: WDT_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/os/hal/ports/NRF51/NRF51822/pal_lld.c b/os/hal/ports/NRF51/NRF51822/pal_lld.c new file mode 100644 index 0000000..69fc9fe --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/pal_lld.c @@ -0,0 +1,158 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file pal_lld.c
+ * @brief NRF51822 PAL subsystem low level driver source.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
+{
+ (void)port;
+ osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
+
+ switch (mode) {
+ case PAL_MODE_RESET:
+ case PAL_MODE_UNCONNECTED:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ case PAL_MODE_INPUT:
+ case PAL_MODE_INPUT_ANALOG:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ case PAL_MODE_INPUT_PULLUP:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ case PAL_MODE_INPUT_PULLDOWN:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ case PAL_MODE_OUTPUT_PUSHPULL:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ case PAL_MODE_OUTPUT_OPENDRAIN:
+ NRF_GPIO->PIN_CNF[pad] =
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
+ (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+ (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ break;
+ default:
+ osalDbgAssert(FALSE, "invalid pal mode");
+ break;
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief NRF51 I/O ports configuration.
+ *
+ * @param[in] config the NRF51 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config)
+{
+ uint8_t i;
+
+ for (i = 0; i < TOTAL_GPIO_PADS; i++) {
+ pal_lld_setpadmode(IOPORT1, i, config->pads[i]);
+ }
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode)
+{
+ uint8_t i;
+
+ for (i = 0; i < TOTAL_GPIO_PADS; i++, mask >>= 1) {
+ if (mask & 1) {
+ pal_lld_setpadmode(port, i, mode);
+ }
+ }
+}
+
+#endif /* HAL_USE_PAL == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/NRF51/NRF51822/pal_lld.h b/os/hal/ports/NRF51/NRF51822/pal_lld.h new file mode 100644 index 0000000..d2f0dfb --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/pal_lld.h @@ -0,0 +1,308 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file pal_lld.h
+ * @brief NRF51822 PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+#define TOTAL_GPIO_PADS 32
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ uint32_t pads[TOTAL_GPIO_PADS];
+} PALConfig;
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32U
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFFU)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint8_t iomode_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef NRF_GPIO_Type *ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief First I/O port identifier.
+ * @details Low level drivers can define multiple ports, it is suggested to
+ * use this naming convention.
+ */
+#define IOPORT1 NRF_GPIO
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) (NRF_GPIO->IN)
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) (NRF_GPIO->OUT)
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) (NRF_GPIO->OUT = (bits))
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) (NRF_GPIO->OUTSET = (bits))
+
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) (NRF_GPIO->OUTCLR = (bits))
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) \
+ ((NRF_GPIO->IN & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) \
+ do { \
+ (void)port; \
+ if (bit == PAL_HIGH) \
+ NRF_GPIO->OUTSET = ((uint32_t) 1 << pad); \
+ else \
+ NRF_GPIO->OUTCLR = ((uint32_t) 1 << pad); \
+ } while (false)
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) (NRF_GPIO->OUTSET = (uint32_t) 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) (NRF_GPIO->OUTCLR = (uint32_t) 1 << (pad))
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) \
+ do { \
+ uint8_t bit = (NRF_GPIO->IN >> (pad)) & 1; \
+ if (bit) \
+ NRF_GPIO->OUTCLR = 1 << (pad); \
+ else \
+ NRF_GPIO->OUTSET = 1 << (pad); \
+ } while (0)
+
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode) _pal_lld_setpadmode(port, pad, mode)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+ void _pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL == TRUE */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/NRF51/NRF51822/platform.mk b/os/hal/ports/NRF51/NRF51822/platform.mk new file mode 100644 index 0000000..10aad23 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/platform.mk @@ -0,0 +1,10 @@ +# List of all the NRF51x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS}/community/os/hal/ports/NRF51/NRF51822/hal_lld.c \ + ${CHIBIOS}/community/os/hal/ports/NRF51/NRF51822/pal_lld.c \ + ${CHIBIOS}/community/os/hal/ports/NRF51/NRF51822/serial_lld.c \ + ${CHIBIOS}/community/os/hal/ports/NRF51/NRF51822/st_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS}/community/os/hal/ports/NRF51/NRF51822 diff --git a/os/hal/ports/NRF51/NRF51822/serial_lld.c b/os/hal/ports/NRF51/NRF51822/serial_lld.c new file mode 100644 index 0000000..1783b92 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/serial_lld.c @@ -0,0 +1,240 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file serial_lld.c
+ * @brief NRF51822 serial subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
+
+#include "nrf51.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define INVALID_BAUDRATE 0xFFFFFFFF
+#define INVALID_PIN 0xFF
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if (NRF51_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ .speed = 38400,
+ .tx_pin = INVALID_PIN,
+ .rx_pin = INVALID_PIN,
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*
+ * @brief Maps a baudrate speed to a BAUDRATE register value.
+ */
+static uint32_t regval_from_baudrate(uint32_t speed)
+{
+ switch (speed) {
+ case 1200: return 0x0004F000;
+ case 2400: return 0x0009D000;
+ case 4800: return 0x0013B000;
+ case 9600: return 0x00275000;
+ case 14400: return 0x003B0000;
+ case 19200: return 0x004EA000;
+ case 28800: return 0x0075F000;
+ case 38400: return 0x009D5000;
+ case 57600: return 0x00EBF000;
+ case 76800: return 0x013A9000;
+ case 115200: return 0x01D7E000;
+ case 230400: return 0x03AFB000;
+ case 250000: return 0x04000000;
+ case 460800: return 0x075F7000;
+ case 921600: return 0x0EBEDFA4;
+ case 1000000: return 0x10000000;
+ }
+ return INVALID_BAUDRATE;
+}
+
+
+/**
+ * @brief Driver output notification.
+ */
+#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+
+ msg_t b = oqGetI(&SD1.oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(&SD1, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ SD1.thread = chThdGetSelfX();
+ NRF_UART0->TXD = b;
+ chEvtWaitAny((eventmask_t) 1);
+}
+#endif
+
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector48) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (NRF_UART0->EVENTS_RXDRDY) {
+ NRF_UART0->EVENTS_RXDRDY = 0;
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&SD1.iqueue))
+ chnAddFlagsI(&SD1, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&SD1.iqueue, NRF_UART0->RXD) < Q_OK)
+ chnAddFlagsI(&SD1, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (NRF_UART0->EVENTS_TXDRDY) {
+ NRF_UART0->EVENTS_TXDRDY = 0;
+ osalSysLockFromISR();
+ chEvtSignalI(SD1.thread, (eventmask_t) 1);
+ osalSysUnlockFromISR();
+ }
+
+ /* TODO: Error handling for EVENTS_ERROR */
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if NRF51_SERIAL_USE_UART0 == TRUE
+ sdObjectInit(&SD1, NULL, notify1);
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL) {
+ config = &default_config;
+ }
+
+ if (sdp->state == SD_STOP) {
+
+#if NRF51_SERIAL_USE_UART0 == TRUE
+ if (sdp == &SD1) {
+ uint32_t regval;
+
+ /* TODO: Add support for CTS/RTS! */
+
+ /* Configure PINs */
+ NRF_UART0->PSELRTS = ~0;
+ NRF_UART0->PSELCTS = ~0;
+ if (config->tx_pin != INVALID_PIN) {
+ palSetPadMode(IOPORT1, config->tx_pin, PAL_MODE_OUTPUT_PUSHPULL);
+ NRF_UART0->PSELTXD = config->tx_pin;
+ }
+ if (config->rx_pin != INVALID_PIN) {
+ palSetPadMode(IOPORT1, config->rx_pin, PAL_MODE_INPUT);
+ NRF_UART0->PSELRXD = config->rx_pin;
+ }
+
+ regval = regval_from_baudrate(config->speed);
+ osalDbgAssert(regval != INVALID_BAUDRATE, "invalid baudrate speed");
+ NRF_UART0->BAUDRATE = regval;
+
+ /* Enable interrupts for RX, TX and ERROR */
+ NRF_UART0->INTENSET = 0x284;
+
+ NRF_UART0->EVENTS_RXDRDY = 0;
+ NRF_UART0->EVENTS_TXDRDY = 0;
+
+ nvicEnableVector(UART0_IRQn, 12);
+
+ NRF_UART0->ENABLE = 4;
+ NRF_UART0->TASKS_STARTRX = 1;
+ NRF_UART0->TASKS_STARTTX = 1;
+ }
+#endif
+
+ }
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+
+#if NRF51_SERIAL_USE_UART0 == TRUE
+ if (&SD1 == sdp) {
+ nvicDisableVector(UART0_IRQn);
+ }
+#endif
+
+ }
+}
+
+#endif /* HAL_USE_SERIAL == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/NRF51/NRF51822/serial_lld.h b/os/hal/ports/NRF51/NRF51822/serial_lld.h new file mode 100644 index 0000000..62f1302 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/serial_lld.h @@ -0,0 +1,122 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file serial_lld.h
+ * @brief NRF51822 serial subsystem low level driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(NRF51_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define NRF51_SERIAL_USE_UART0 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief NRF51 Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note This structure content is architecture dependent, each driver
+ * implementation defines its own version and the custom static
+ * initializers.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t speed;
+ /* End of the mandatory fields.*/
+ uint8_t tx_pin;
+ uint8_t rx_pin;
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ thread_t *thread;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (NRF51_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL == TRUE */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/NRF51/NRF51822/st_lld.c b/os/hal/ports/NRF51/NRF51822/st_lld.c new file mode 100644 index 0000000..526db35 --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/st_lld.c @@ -0,0 +1,115 @@ +/*
+ ChibiOS - Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file st_lld.c
+ * @brief NRF51822 ST subsystem low level driver source.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear timer compare event */
+ if (NRF_TIMER0->EVENTS_COMPARE[0] != 0)
+ NRF_TIMER0->EVENTS_COMPARE[0] = 0;
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ NRF_TIMER0->TASKS_CLEAR = 1;
+
+ /*
+ * Using 32-bit mode with prescaler 16 configures this
+ * timer with a 1MHz clock.
+ */
+ NRF_TIMER0->BITMODE = 3;
+ NRF_TIMER0->PRESCALER = 4;
+
+ /*
+ * Configure timer 0 compare capture 0 to generate interrupt
+ * and clear timer value when event is generated.
+ */
+ NRF_TIMER0->CC[0] = (1000000 / OSAL_ST_FREQUENCY) - 1;
+ NRF_TIMER0->SHORTS = 1;
+ NRF_TIMER0->INTENSET = 0x10000;
+
+ nvicEnableVector(TIMER0_IRQn, 8);
+
+ /* Start timer */
+ NRF_TIMER0->TASKS_START = 1;
+#endif
+
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/NRF51/NRF51822/st_lld.h b/os/hal/ports/NRF51/NRF51822/st_lld.h new file mode 100644 index 0000000..2e0672e --- /dev/null +++ b/os/hal/ports/NRF51/NRF51822/st_lld.h @@ -0,0 +1,141 @@ +/*
+ ChibiOS - Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file st_lld.h
+ * @brief NRF51822 ST subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] abstime the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t abstime) {
+
+ (void)abstime;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] abstime the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t abstime) {
+
+ (void)abstime;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c new file mode 100644 index 0000000..75643d6 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c @@ -0,0 +1,3130 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file stm32_dma2d.c
+ * @brief DMA2D/Chrom-ART driver.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#include "stm32_dma2d.h"
+
+#if STM32_DMA2D_USE_DMA2D || defined(__DOXYGEN__)
+
+/* Ignore annoying warning messages for actually safe code.*/
+#if defined(__GNUC__) && !defined(__DOXYGEN__)
+#pragma GCC diagnostic ignored "-Wtype-limits"
+#endif
+
+/**
+ * @addtogroup dma2d
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief DMA2DD1 driver identifier.*/
+DMA2DDriver DMA2DD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Bits per pixel lookup table.
+ */
+static const uint8_t dma2d_bpp[DMA2D_MAX_PIXFMT_ID + 1] = {
+ 32, /* DMA2D_FMT_ARGB8888 */
+ 24, /* DMA2D_FMT_RGB888 */
+ 16, /* DMA2D_FMT_RGB565 */
+ 16, /* DMA2D_FMT_ARGB1555 */
+ 16, /* DMA2D_FMT_ARGB4444 */
+ 8, /* DMA2D_FMT_L8 */
+ 8, /* DMA2D_FMT_AL44 */
+ 16, /* DMA2D_FMT_AL88 */
+ 4, /* DMA2D_FMT_L4 */
+ 8, /* DMA2D_FMT_A8 */
+ 4 /* DMA2D_FMT_A4 */
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @name DMA2D interrupt handlers
+ * @{
+ */
+
+/**
+ * @brief DMA2D global interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
+
+ DMA2DDriver *const dma2dp = &DMA2DD1;
+ bool job_done = false;
+ thread_t *tp = NULL;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Handle Configuration Error ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_CEIF) && (DMA2D->CR & DMA2D_CR_CEIE)) {
+ if (dma2dp->config->cfgerr_isr != NULL)
+ dma2dp->config->cfgerr_isr(dma2dp);
+ job_done = true;
+ DMA2D->IFCR |= DMA2D_IFSR_CCEIF;
+ }
+
+ /* Handle CLUT (Palette) Transfer Complete ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_CTCIF) && (DMA2D->CR & DMA2D_CR_CTCIE)) {
+ if (dma2dp->config->paltrfdone_isr != NULL)
+ dma2dp->config->paltrfdone_isr(dma2dp);
+ job_done = true;
+ DMA2D->IFCR |= DMA2D_IFSR_CCTCIF;
+ }
+
+ /* Handle CLUT (Palette) Access Error ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_CAEIF) && (DMA2D->CR & DMA2D_CR_CAEIE)) {
+ if (dma2dp->config->palacserr_isr != NULL)
+ dma2dp->config->palacserr_isr(dma2dp);
+ job_done = true;
+ DMA2D->IFCR |= DMA2D_IFSR_CCAEIF;
+ }
+
+ /* Handle Transfer Watermark ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_TWIF) && (DMA2D->CR & DMA2D_CR_TWIE)) {
+ if (dma2dp->config->trfwmark_isr != NULL)
+ dma2dp->config->trfwmark_isr(dma2dp);
+ DMA2D->IFCR |= DMA2D_IFSR_CTWIF;
+ }
+
+ /* Handle Transfer Complete ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_TCIF) && (DMA2D->CR & DMA2D_CR_TCIE)) {
+ if (dma2dp->config->trfdone_isr != NULL)
+ dma2dp->config->trfdone_isr(dma2dp);
+ job_done = true;
+ DMA2D->IFCR |= DMA2D_IFSR_CTCIF;
+ }
+
+ /* Handle Transfer Error ISR.*/
+ if ((DMA2D->ISR & DMA2D_ISR_TEIF) && (DMA2D->CR & DMA2D_CR_TEIE)) {
+ if (dma2dp->config->trferr_isr != NULL)
+ dma2dp->config->trferr_isr(dma2dp);
+ job_done = true;
+ DMA2D->IFCR |= DMA2D_IFSR_CTEIF;
+ }
+
+ if (job_done) {
+ osalSysLockFromISR();
+ osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state");
+
+ #if DMA2D_USE_WAIT
+ /* Wake the waiting thread up.*/
+ if (dma2dp->thread != NULL) {
+ tp = dma2dp->thread;
+ dma2dp->thread = NULL;
+ tp->p_u.rdymsg = MSG_OK;
+ chSchReadyI(tp);
+ }
+ #endif /* DMA2D_USE_WAIT */
+
+ dma2dp->state = DMA2D_READY;
+ osalSysUnlockFromISR();
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D driver-specific methods
+ * @{
+ */
+
+/**
+ * @brief DMA2D Driver initialization.
+ * @details Initializes the DMA2D subsystem and chosen drivers. Should be
+ * called at board initialization.
+ *
+ * @init
+ */
+void dma2dInit(void) {
+
+ /* Reset the DMA2D hardware module.*/
+ rccResetDMA2D();
+
+ /* Enable the DMA2D clock.*/
+ rccEnableDMA2D(false);
+
+ /* Driver struct initialization.*/
+ dma2dObjectInit(&DMA2DD1);
+ DMA2DD1.state = DMA2D_STOP;
+}
+
+/**
+ * @brief Initializes the standard part of a @p DMA2DDriver structure.
+ *
+ * @param[out] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @init
+ */
+void dma2dObjectInit(DMA2DDriver *dma2dp) {
+
+ osalDbgCheck(dma2dp == &DMA2DD1);
+
+ dma2dp->state = DMA2D_UNINIT;
+ dma2dp->config = NULL;
+#if DMA2D_USE_WAIT
+ dma2dp->thread = NULL;
+#endif /* DMA2D_USE_WAIT */
+#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxObjectInit(&dma2dp->lock);
+#else
+ chSemObjectInit(&dma2dp->lock, 1);
+#endif
+#endif /* (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) */
+}
+
+/**
+ * @brief Get the driver state.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @retun driver state
+ *
+ * @iclass
+ */
+dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheckClassI();
+
+ return dma2dp->state;
+}
+
+/**
+ * @brief Get the driver state.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @retun driver state
+ *
+ * @api
+ */
+dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp) {
+
+ dma2d_state_t state;
+ chSysLock();
+ state = dma2dGetStateI(dma2dp);
+ chSysUnlock();
+ return state;
+}
+
+/**
+ * @brief Configures and activates the DMA2D peripheral.
+ * @pre DMA2D is stopped.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] configp pointer to the @p DMA2DConfig object
+ *
+ * @api
+ */
+void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp) {
+
+ chSysLock();
+
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(configp != NULL);
+ osalDbgAssert(dma2dp->state == DMA2D_STOP, "invalid state");
+
+ dma2dp->config = configp;
+
+ /* Turn off the controller and its interrupts.*/
+ DMA2D->CR = 0;
+
+ /* Enable interrupts, except Line Watermark.*/
+ nvicEnableVector(STM32_DMA2D_NUMBER, STM32_DMA2D_IRQ_PRIORITY);
+
+ DMA2D->CR = (DMA2D_CR_CEIE | DMA2D_CR_CTCIE | DMA2D_CR_CAEIE |
+ DMA2D_CR_TCIE | DMA2D_CR_TEIE);
+
+ dma2dp->state = DMA2D_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Deactivates the DMA2D peripheral.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dStop(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "invalid state");
+#if DMA2D_USE_WAIT
+ osalDbgAssert(dma2dp->thread == NULL, "still waiting");
+#endif /* DMA2D_USE_WAIT */
+
+ dma2dp->state = DMA2D_STOP;
+ chSysUnlock();
+}
+
+#if DMA2D_USE_MUTUAL_EXCLUSION
+
+/**
+ * @brief Gains exclusive access to the DMA2D module.
+ * @details This function tries to gain ownership to the DMA2D module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @sclass
+ */
+void dma2dAcquireBusS(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxLockS(&dma2dp->lock);
+#else
+ chSemWaitS(&dma2dp->lock);
+#endif
+}
+
+/**
+ * @brief Gains exclusive access to the DMA2D module.
+ * @details This function tries to gain ownership to the DMA2D module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dAcquireBus(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dAcquireBusS(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Releases exclusive access to the DMA2D module.
+ * @pre In order to use this function the option
+ * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @sclass
+ */
+void dma2dReleaseBusS(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxUnlockS(&dma2dp->lock);
+#else
+ chSemSignalI(&dma2dp->lock);
+#endif
+}
+
+/**
+ * @brief Releases exclusive access to the DMA2D module.
+ * @pre In order to use this function the option
+ * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dReleaseBus(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dReleaseBusS(dma2dp);
+ chSysUnlock();
+}
+
+#endif /* DMA2D_USE_MUTUAL_EXCLUSION */
+
+/** @} */
+
+/**
+ * @name DMA2D global methods
+ * @{
+ */
+
+/**
+ * @brief Get watermark position.
+ * @details Gets the watermark line position.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return watermark line position
+ *
+ * @iclass
+ */
+uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (uint16_t)(DMA2D->LWR & DMA2D_LWR_LW);
+}
+
+/**
+ * @brief Get watermark position.
+ * @details Gets the watermark line position.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return watermark line position
+ *
+ * @api
+ */
+uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp) {
+
+ uint16_t line;
+ chSysLock();
+ line = dma2dGetWatermarkPosI(dma2dp);
+ chSysUnlock();
+ return line;
+}
+
+/**
+ * @brief Set watermark position.
+ * @details Sets the watermark line position.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] line watermark line position
+ *
+ * @iclass
+ */
+void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->LWR = ((DMA2D->LWR & ~DMA2D_LWR_LW) |
+ ((uint32_t)line & DMA2D_LWR_LW));
+}
+
+/**
+ * @brief Set watermark position.
+ * @details Sets the watermark line position.
+ * @note The interrupt is invoked after the last pixel of the watermark line
+ * is written.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] line watermark line position
+ *
+ * @iclass
+ */
+void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line) {
+
+ chSysLock();
+ dma2dSetWatermarkPosI(dma2dp, line);
+ chSysUnlock();
+}
+
+/**
+ * @brief Watermark interrupt enabled.
+ * @details Tells whether the watermark interrupt is enabled.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (DMA2D->CR & DMA2D_CR_TWIE) != 0;
+}
+
+/**
+ * @brief Watermark interrupt enabled.
+ * @details Tells whether the watermark interrupt is enabled.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp) {
+
+ bool enabled;
+ chSysLock();
+ enabled = dma2dIsWatermarkEnabledI(dma2dp);
+ chSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable watermark interrupt.
+ * @details Enables the watermark interrupt. The interrupt is invoked after the
+ * last pixel of the watermark line is written to the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dEnableWatermarkI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ DMA2D->CR |= DMA2D_CR_TWIE;
+}
+
+/**
+ * @brief Enable watermark interrupt.
+ * @details Enables the watermark interrupt. The interrupt is invoked after the
+ * last pixel of the watermark line is written to the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dEnableWatermark(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dEnableWatermarkI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Disable watermark interrupt.
+ * @details Disables the watermark interrupt.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dDisableWatermarkI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ DMA2D->CR &= ~DMA2D_CR_TWIE;
+}
+
+/**
+ * @brief Disable watermark interrupt.
+ * @details Disables the watermark interrupt.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dDisableWatermark(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dDisableWatermarkI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get dead time cycles.
+ * @details Gets the minimum dead time DMA2D clock cycles between DMA2D
+ * transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return dead time, in DMA2D clock cycles
+ *
+ * @iclass
+ */
+uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (DMA2D->AMTCR & DMA2D_AMTCR_DT) >> 8;
+}
+
+/**
+ * @brief Get dead time cycles.
+ * @details Gets the minimum dead time DMA2D clock cycles between DMA2D
+ * transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return dead time, in DMA2D clock cycles
+ *
+ * @api
+ */
+uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp) {
+
+ uint32_t cycles;
+ chSysLock();
+ cycles = dma2dGetDeadTimeI(dma2dp);
+ chSysUnlock();
+ return cycles;
+}
+
+/**
+ * @brief Set dead time cycles.
+ * @details Sets the minimum dead time DMA2D clock cycles between DMA2D
+ * transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cycles dead time, in DMA2D clock cycles
+ *
+ * @iclass
+ */
+void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(cycles <= DMA2D_MAX_DEADTIME_CYCLES, "bounds");
+ (void)dma2dp;
+
+ DMA2D->AMTCR = ((DMA2D->AMTCR & ~DMA2D_AMTCR_DT) |
+ ((cycles << 8) & DMA2D_AMTCR_DT));
+}
+
+/**
+ * @brief Set dead time cycles.
+ * @details Sets the minimum dead time DMA2D clock cycles between DMA2D
+ * transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cycles dead time, in DMA2D clock cycles
+ *
+ * @api
+ */
+void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles) {
+
+ chSysLock();
+ dma2dSetDeadTimeI(dma2dp, cycles);
+ chSysUnlock();
+}
+
+/**
+ * @brief Dead time enabled.
+ * @details Tells whether the dead time between DMA2D transactions is enabled.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (DMA2D->AMTCR & DMA2D_AMTCR_EN) != 0;
+}
+
+/**
+ * @brief Dead time enabled.
+ * @details Tells whether the dead time between DMA2D transactions is enabled.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp) {
+
+ bool enabled;
+ chSysLock();
+ enabled = dma2dIsDeadTimeEnabledI(dma2dp);
+ chSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable dead time.
+ * @details Enables the dead time between DMA2D transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ DMA2D->AMTCR |= DMA2D_AMTCR_EN;
+}
+
+/**
+ * @brief Enable dead time.
+ * @details Enables the dead time between DMA2D transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dEnableDeadTime(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dEnableDeadTimeI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Disable dead time.
+ * @details Disables the dead time between DMA2D transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ DMA2D->AMTCR &= ~DMA2D_AMTCR_EN;
+}
+
+/**
+ * @brief Disable dead time.
+ * @details Disables the dead time between DMA2D transactions.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dDisableDeadTime(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dDisableDeadTimeI(dma2dp);
+ chSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D job (transaction) methods
+ * @{
+ */
+
+/**
+ * @brief Get job mode.
+ * @details Gets the job mode.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return job mode
+ *
+ * @iclass
+ */
+dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_jobmode_t)(DMA2D->CR & DMA2D_CR_MODE);
+}
+
+/**
+ * @brief Get job mode.
+ * @details Gets the job mode.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return job mode
+ *
+ * @api
+ */
+dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp) {
+
+ dma2d_jobmode_t mode;
+ chSysLock();
+ mode = dma2dJobGetModeI(dma2dp);
+ chSysUnlock();
+ return mode;
+}
+
+/**
+ * @brief Set job mode.
+ * @details Sets the job mode.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode job mode
+ *
+ * @iclass
+ */
+void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert((mode & ~DMA2D_CR_MODE) == 0, "bounds");
+ (void)dma2dp;
+
+ DMA2D->CR = ((DMA2D->CR & ~DMA2D_CR_MODE) |
+ ((uint32_t)mode & DMA2D_CR_MODE));
+}
+
+/**
+ * @brief Set job mode.
+ * @details Sets the job mode.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode job mode
+ *
+ * @api
+ */
+void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) {
+
+ chSysLock();
+ dma2dJobSetModeI(dma2dp, mode);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get job size.
+ * @details Gets the job size.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] widthp pointer to the job width, in pixels
+ * @param[out] heightp pointer to the job height, in pixels
+ *
+ * @iclass
+ */
+void dma2dJobGetSizeI(DMA2DDriver *dma2dp,
+ uint16_t *widthp, uint16_t *heightp) {
+
+ uint32_t r;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(widthp != NULL);
+ osalDbgCheck(heightp != NULL);
+ (void)dma2dp;
+
+ r = DMA2D->NLR;
+ *widthp = (uint16_t)((r & DMA2D_NLR_PL) >> 16);
+ *heightp = (uint16_t)((r & DMA2D_NLR_NL) >> 0);
+}
+
+/**
+ * @brief Get job size.
+ * @details Gets the job size.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] widthp pointer to the job width, in pixels
+ * @param[out] heightp pointer to the job height, in pixels
+ *
+ * @api
+ */
+void dma2dJobGetSize(DMA2DDriver *dma2dp,
+ uint16_t *widthp, uint16_t *heightp) {
+
+ chSysLock();
+ dma2dJobGetSizeI(dma2dp, widthp, heightp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set job size.
+ * @details Sets the job size.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] widthp job width, in pixels
+ * @param[in] heightp job height, in pixels
+ *
+ * @iclass
+ */
+void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(width <= DMA2D_MAX_WIDTH, "bounds");
+ osalDbgAssert(height <= DMA2D_MAX_HEIGHT, "bounds");
+ (void)dma2dp;
+
+ DMA2D->NLR = ((((uint32_t)width << 16) & DMA2D_NLR_PL) |
+ (((uint32_t)height << 0) & DMA2D_NLR_NL));
+}
+
+/**
+ * @brief Set job size.
+ * @details Sets the job size.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] widthp job width, in pixels
+ * @param[in] heightp job height, in pixels
+ *
+ * @api
+ */
+void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) {
+
+ chSysLock();
+ dma2dJobSetSizeI(dma2dp, width, height);
+ chSysUnlock();
+}
+
+/**
+ * @brief Job executing.
+ * @details Tells whether a job (transaction) is active or paused.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return executing
+ *
+ * @iclass
+ */
+bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+
+ return dma2dp->state > DMA2D_READY;
+}
+
+/**
+ * @brief Job executing.
+ * @details Tells whether a job (transaction) is active or paused.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return executing
+ *
+ * @api
+ */
+bool dma2dJobIsExecuting(DMA2DDriver *dma2dp) {
+
+ bool executing;
+ chSysLock();
+ executing = dma2dJobIsExecutingI(dma2dp);
+ chSysUnlock();
+ return executing;
+}
+
+/**
+ * @brief Start job.
+ * @details The job is started, and the DMA2D is set to active.
+ * @note Should there be invalid parameters, the appropriate interrupt
+ * handler will be invoked, and the DMA2D set back to ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dJobStartI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+
+ dma2dp->state = DMA2D_ACTIVE;
+ DMA2D->CR |= DMA2D_CR_START;
+}
+
+/**
+ * @brief Start job.
+ * @details The job is started, and the DMA2D is set to active.
+ * @note Should there be invalid parameters, the appropriate interrupt
+ * handler will be invoked, and the DMA2D set back to ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dJobStart(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dJobStartI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Execute job.
+ * @details Starts the job and waits for its completion, synchronously.
+ * @note Should there be invalid parameters, the appropriate interrupt
+ * handler will be invoked, and the DMA2D set back to ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @sclass
+ */
+void dma2dJobExecuteS(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+
+ dma2dJobStartI(dma2dp);
+#if DMA2D_USE_WAIT
+ dma2dp->thread = chThdGetSelfX();
+ chSchGoSleepS(CH_STATE_SUSPENDED);
+#else
+ while (DMA2D->CR & DMA2D_CR_START)
+ chSchDoYieldS();
+#endif
+}
+
+/**
+ * @brief Execute job.
+ * @details Starts the job and waits for its completion, synchronously.
+ * @note Should there be invalid parameters, the appropriate interrupt
+ * handler will be invoked, and the DMA2D set back to ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dJobExecute(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dJobExecuteS(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspend current job.
+ * @details Suspends the current job. The driver is set to a paused state.
+ * @pre There is an active job.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dJobSuspendI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0);
+ osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state");
+
+ dma2dp->state = DMA2D_PAUSED;
+ DMA2D->CR |= DMA2D_CR_SUSP;
+}
+
+/**
+ * @brief Suspend current job.
+ * @details Suspends the current job. The driver is set to a paused state.
+ * @pre There is an active job.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dJobSuspend(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dJobSuspendI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Resume current job.
+ * @details Resumes the current job.
+ * @pre There is a paused job.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dJobResumeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) != 0);
+ osalDbgAssert(dma2dp->state == DMA2D_PAUSED, "invalid state");
+
+ dma2dp->state = DMA2D_ACTIVE;
+ DMA2D->CR &= ~DMA2D_CR_SUSP;
+}
+
+/**
+ * @brief Resume current job.
+ * @details Resumes the current job.
+ * @pre There is a paused job.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dJobResume(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dJobResumeI(dma2dp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Abort current job.
+ * @details Abots the current job (if any), and the driver becomes ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @iclass
+ */
+void dma2dJobAbortI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0);
+ osalDbgAssert(dma2dp->state >= DMA2D_READY, "invalid state");
+
+ dma2dp->state = DMA2D_READY;
+ DMA2D->CR |= DMA2D_CR_ABORT;
+}
+
+/**
+ * @brief Abort current job.
+ * @details Abots the current job (if any), and the driver becomes ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @api
+ */
+void dma2dJobAbort(DMA2DDriver *dma2dp) {
+
+ chSysLock();
+ dma2dJobAbortI(dma2dp);
+ chSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D background layer methods
+ * @{
+ */
+
+/**
+ * @brief Get background layer buffer address.
+ * @details Gets the buffer address of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @iclass
+ */
+void *dma2dBgGetAddressI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (void *)DMA2D->BGMAR;
+}
+
+/**
+ * @brief Get background layer buffer address.
+ * @details Gets the buffer address of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @api
+ */
+void *dma2dBgGetAddress(DMA2DDriver *dma2dp) {
+
+ void *bufferp;
+ chSysLock();
+ bufferp = dma2dBgGetAddressI(dma2dp);
+ chSysUnlock();
+ return bufferp;
+}
+
+/**
+ * @brief Set background layer buffer address.
+ * @details Sets the buffer address of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @iclass
+ */
+void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(dma2dIsAligned(bufferp, dma2dBgGetPixelFormatI(dma2dp)));
+ (void)dma2dp;
+
+ DMA2D->BGMAR = (uint32_t)bufferp;
+}
+
+/**
+ * @brief Set background layer buffer address.
+ * @details Sets the buffer address of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @api
+ */
+void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp) {
+
+ chSysLock();
+ dma2dBgSetAddressI(dma2dp, bufferp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer wrap offset.
+ * @details Gets the buffer line wrap offset of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @iclass
+ */
+size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (size_t)(DMA2D->BGOR & DMA2D_BGOR_LO);
+}
+
+/**
+ * @brief Get background layer wrap offset.
+ * @details Gets the buffer line wrap offset of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @api
+ */
+size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp) {
+
+ size_t offset;
+ chSysLock();
+ offset = dma2dBgGetWrapOffsetI(dma2dp);
+ chSysUnlock();
+ return offset;
+}
+
+/**
+ * @brief Set background layer wrap offset.
+ * @details Sets the buffer line wrap offset of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @iclass
+ */
+void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds");
+ (void)dma2dp;
+
+ DMA2D->BGOR = ((DMA2D->BGOR & ~DMA2D_BGOR_LO) |
+ ((uint32_t)offset & DMA2D_BGOR_LO));
+}
+
+/**
+ * @brief Set background layer wrap offset.
+ * @details Sets the buffer line wrap offset of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @api
+ */
+void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) {
+
+ chSysLock();
+ dma2dBgSetWrapOffsetI(dma2dp, offset);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer constant alpha.
+ * @details Gets the constant alpha component of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @iclass
+ */
+uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (uint8_t)((DMA2D->BGPFCCR & DMA2D_BGPFCCR_ALPHA) >> 24);
+}
+
+/**
+ * @brief Get background layer constant alpha.
+ * @details Gets the constant alpha component of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @api
+ */
+uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp) {
+
+ uint8_t a;
+ chSysLock();
+ a = dma2dBgGetConstantAlphaI(dma2dp);
+ chSysUnlock();
+ return a;
+}
+
+/**
+ * @brief Set background layer constant alpha.
+ * @details Sets the constant alpha component of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @iclass
+ */
+void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_ALPHA) |
+ (((uint32_t)a << 24) & DMA2D_BGPFCCR_ALPHA));
+}
+
+/**
+ * @brief Set background layer constant alpha.
+ * @details Sets the constant alpha component of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @api
+ */
+void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) {
+
+ chSysLock();
+ dma2dBgSetConstantAlphaI(dma2dp, a);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer alpha mode.
+ * @details Gets the alpha mode of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return alpha mode
+ *
+ * @iclass
+ */
+dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_amode_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_AM);
+}
+
+/**
+ * @brief Get background layer alpha mode.
+ * @details Gets the alpha mode of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return alpha mode
+ *
+ * @api
+ */
+dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp) {
+
+ dma2d_amode_t mode;
+ chSysLock();
+ mode = dma2dBgGetAlphaModeI(dma2dp);
+ chSysUnlock();
+ return mode;
+}
+
+/**
+ * @brief Set background layer alpha mode.
+ * @details Sets the alpha mode of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode alpha mode
+ *
+ * @iclass
+ */
+void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert((mode & ~DMA2D_BGPFCCR_AM) == 0, "bounds");
+ osalDbgAssert((mode & DMA2D_BGPFCCR_AM) != DMA2D_BGPFCCR_AM, "bounds");
+ (void)dma2dp;
+
+ DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_AM) |
+ ((uint32_t)mode & DMA2D_BGPFCCR_AM));
+}
+
+/**
+ * @brief Set background layer alpha mode.
+ * @details Sets the alpha mode of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode alpha mode
+ *
+ * @api
+ */
+void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) {
+
+ chSysLock();
+ dma2dBgSetAlphaModeI(dma2dp, mode);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer pixel format.
+ * @details Gets the pixel format of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @iclass
+ */
+dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_pixfmt_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_CM);
+}
+
+/**
+ * @brief Get background layer pixel format.
+ * @details Gets the pixel format of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @api
+ */
+dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp) {
+
+ dma2d_pixfmt_t fmt;
+ chSysLock();
+ fmt = dma2dBgGetPixelFormatI(dma2dp);
+ chSysUnlock();
+ return fmt;
+}
+
+/**
+ * @brief Set background layer pixel format.
+ * @details Sets the pixel format of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @iclass
+ */
+void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds");
+ (void)dma2dp;
+
+ DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_CM) |
+ ((uint32_t)fmt & DMA2D_BGPFCCR_CM));
+}
+
+/**
+ * @brief Set background layer pixel format.
+ * @details Sets the pixel format of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @api
+ */
+void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ chSysLock();
+ dma2dBgSetPixelFormatI(dma2dp, fmt);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer default color.
+ * @details Gets the default color of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @iclass
+ */
+dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_color_t)(DMA2D->BGCOLR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get background layer default color.
+ * @details Gets the default color of the background layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @api
+ */
+dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp) {
+
+ dma2d_color_t c;
+ chSysLock();
+ c = dma2dBgGetDefaultColorI(dma2dp);
+ chSysUnlock();
+ return c;
+}
+
+/**
+ * @brief Set background layer default color.
+ * @details Sets the default color of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @iclass
+ */
+void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->BGCOLR = (uint32_t)c & 0x00FFFFFF;
+}
+
+/**
+ * @brief Set background layer default color.
+ * @details Sets the default color of the background layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @api
+ */
+void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ chSysLock();
+ dma2dBgSetDefaultColorI(dma2dp, c);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer palette specifications.
+ * @details Gets the palette specifications of the background layer.
+ * @note The palette colors pointer is actually addressed to a @p volatile
+ * memory zone.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] palettep pointer to the palette specifications
+ *
+ * @iclass
+ */
+void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) {
+
+ uint32_t r;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(palettep != NULL);
+ (void)dma2dp;
+
+ r = DMA2D->BGPFCCR;
+ palettep->colorsp = (const void *)DMA2D->BGCLUT;
+ palettep->length = (uint16_t)((r & DMA2D_BGPFCCR_CS) >> 8) + 1;
+ palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_BGPFCCR_CCM) >> 4);
+}
+
+/**
+ * @brief Get background layer palette specifications.
+ * @details Gets the palette specifications of the background layer.
+ * @note The palette colors pointer is actually addressed to a @p volatile
+ * memory zone.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] palettep pointer to the palette specifications
+ *
+ * @api
+ */
+void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) {
+
+ chSysLock();
+ dma2dBgGetPaletteI(dma2dp, palettep);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set background layer palette specifications.
+ * @details Sets the palette specifications of the background layer.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] palettep pointer to the palette specifications
+ *
+ * @sclass
+ */
+void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(palettep != NULL);
+ osalDbgCheck(palettep->colorsp != NULL);
+ osalDbgAssert(palettep->length > 0, "bounds");
+ osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds");
+ osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) ||
+ (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format");
+
+ DMA2D->BGCMAR = (uint32_t)palettep->colorsp;
+ DMA2D->BGPFCCR = (
+ (DMA2D->BGPFCCR & ~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM)) |
+ ((((uint32_t)palettep->length - 1) << 8) & DMA2D_BGPFCCR_CS) |
+ ((uint32_t)palettep->fmt << 4)
+ );
+
+ dma2dp->state = DMA2D_ACTIVE;
+ DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START;
+
+#if DMA2D_USE_WAIT
+ dma2dp->thread = chThdGetSelfX();
+ chSchGoSleepS(CH_STATE_SUSPENDED);
+#else
+ while (DMA2D->BGPFCCR & DMA2D_BGPFCCR_START)
+ chSchDoYieldS();
+#endif /* DMA2D_USE_WAIT */
+}
+
+/**
+ * @brief Set background layer palette specifications.
+ * @details Sets the palette specifications of the background layer.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] palettep pointer to the palette specifications
+ *
+ * @api
+ */
+void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) {
+
+ chSysLock();
+ dma2dBgSetPaletteS(dma2dp, palettep);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get background layer specifications.
+ * @details Gets the background layer specifications at once.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(cfgp != NULL);
+
+ cfgp->bufferp = dma2dBgGetAddressI(dma2dp);
+ cfgp->wrap_offset = dma2dBgGetWrapOffsetI(dma2dp);
+ cfgp->fmt = dma2dBgGetPixelFormatI(dma2dp);
+ cfgp->def_color = dma2dBgGetDefaultColorI(dma2dp);
+ cfgp->const_alpha = dma2dBgGetConstantAlphaI(dma2dp);
+ if (cfgp->palettep != NULL)
+ dma2dBgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep);
+}
+
+/**
+ * @brief Get background layer specifications.
+ * @details Gets the background layer specifications at once.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dBgGetLayerI(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set background layer specifications.
+ * @details Sets the background layer specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @sclass
+ */
+void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(cfgp != NULL);
+
+ dma2dBgSetAddressI(dma2dp, cfgp->bufferp);
+ dma2dBgSetWrapOffsetI(dma2dp, cfgp->wrap_offset);
+ dma2dBgSetPixelFormatI(dma2dp, cfgp->fmt);
+ dma2dBgSetDefaultColorI(dma2dp, cfgp->def_color);
+ dma2dBgSetConstantAlphaI(dma2dp, cfgp->const_alpha);
+ if (cfgp->palettep != NULL)
+ dma2dBgSetPaletteS(dma2dp, cfgp->palettep);
+}
+
+/**
+ * @brief Set background layer specifications.
+ * @details Sets the background layer specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dBgSetConfigS(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D foreground layer methods
+ * @{
+ */
+
+/**
+ * @brief Get foreground layer buffer address.
+ * @details Gets the buffer address of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @iclass
+ */
+void *dma2dFgGetAddressI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (void *)DMA2D->FGMAR;
+}
+
+/**
+ * @brief Get foreground layer buffer address.
+ * @details Gets the buffer address of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @api
+ */
+void *dma2dFgGetAddress(DMA2DDriver *dma2dp) {
+
+ void *bufferp;
+ chSysLock();
+ bufferp = dma2dFgGetAddressI(dma2dp);
+ chSysUnlock();
+ return bufferp;
+}
+
+/**
+ * @brief Set foreground layer buffer address.
+ * @details Sets the buffer address of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @iclass
+ */
+void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(dma2dIsAligned(bufferp, dma2dFgGetPixelFormatI(dma2dp)));
+ (void)dma2dp;
+
+ DMA2D->FGMAR = (uint32_t)bufferp;
+}
+
+/**
+ * @brief Set foreground layer buffer address.
+ * @details Sets the buffer address of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @api
+ */
+void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp) {
+
+ chSysLock();
+ dma2dFgSetAddressI(dma2dp, bufferp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer wrap offset.
+ * @details Gets the buffer line wrap offset of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @iclass
+ */
+size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (size_t)(DMA2D->FGOR & DMA2D_FGOR_LO);
+}
+
+/**
+ * @brief Get foreground layer wrap offset.
+ * @details Gets the buffer line wrap offset of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @api
+ */
+size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp) {
+
+ size_t offset;
+ chSysLock();
+ offset = dma2dFgGetWrapOffsetI(dma2dp);
+ chSysUnlock();
+ return offset;
+}
+
+/**
+ * @brief Set foreground layer wrap offset.
+ * @details Sets the buffer line wrap offset of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @iclass
+ */
+void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds");
+ (void)dma2dp;
+
+ DMA2D->FGOR = ((DMA2D->FGOR & ~DMA2D_FGOR_LO) |
+ ((uint32_t)offset & DMA2D_FGOR_LO));
+}
+
+/**
+ * @brief Set foreground layer wrap offset.
+ * @details Sets the buffer line wrap offset of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @api
+ */
+void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) {
+
+ chSysLock();
+ dma2dFgSetWrapOffsetI(dma2dp, offset);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer constant alpha.
+ * @details Gets the constant alpha component of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @iclass
+ */
+uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (uint8_t)((DMA2D->FGPFCCR & DMA2D_FGPFCCR_ALPHA) >> 24);
+}
+
+/**
+ * @brief Get foreground layer constant alpha.
+ * @details Gets the constant alpha component of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @api
+ */
+uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp) {
+
+ uint8_t a;
+ chSysLock();
+ a = dma2dFgGetConstantAlphaI(dma2dp);
+ chSysUnlock();
+ return a;
+}
+
+/**
+ * @brief Set foreground layer constant alpha.
+ * @details Sets the constant alpha component of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @iclass
+ */
+void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_ALPHA) |
+ (((uint32_t)a << 24) & DMA2D_FGPFCCR_ALPHA));
+}
+
+/**
+ * @brief Set foreground layer constant alpha.
+ * @details Sets the constant alpha component of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @api
+ */
+void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) {
+
+ chSysLock();
+ dma2dFgSetConstantAlphaI(dma2dp, a);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer alpha mode.
+ * @details Gets the alpha mode of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return alpha mode
+ *
+ * @iclass
+ */
+dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_amode_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_AM);
+}
+
+/**
+ * @brief Get foreground layer alpha mode.
+ * @details Gets the alpha mode of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return alpha mode
+ *
+ * @api
+ */
+dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp) {
+
+ dma2d_amode_t mode;
+ chSysLock();
+ mode = dma2dFgGetAlphaModeI(dma2dp);
+ chSysUnlock();
+ return mode;
+}
+
+/**
+ * @brief Set foreground layer alpha mode.
+ * @details Sets the alpha mode of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode alpha mode
+ *
+ * @iclass
+ */
+void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert((mode & ~DMA2D_FGPFCCR_AM) == 0, "bounds");
+ osalDbgAssert((mode & DMA2D_FGPFCCR_AM) != DMA2D_FGPFCCR_AM, "bounds");
+ (void)dma2dp;
+
+ DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_AM) |
+ ((uint32_t)mode & DMA2D_FGPFCCR_AM));
+}
+
+/**
+ * @brief Set foreground layer alpha mode.
+ * @details Sets the alpha mode of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] mode alpha mode
+ *
+ * @api
+ */
+void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) {
+
+ chSysLock();
+ dma2dFgSetAlphaModeI(dma2dp, mode);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer pixel format.
+ * @details Gets the pixel format of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @iclass
+ */
+dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_pixfmt_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_CM);
+}
+
+/**
+ * @brief Get foreground layer pixel format.
+ * @details Gets the pixel format of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @api
+ */
+dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp) {
+
+ dma2d_pixfmt_t fmt;
+ chSysLock();
+ fmt = dma2dFgGetPixelFormatI(dma2dp);
+ chSysUnlock();
+ return fmt;
+}
+
+/**
+ * @brief Set foreground layer pixel format.
+ * @details Sets the pixel format of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @iclass
+ */
+void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds");
+ (void)dma2dp;
+
+ DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_CM) |
+ ((uint32_t)fmt & DMA2D_FGPFCCR_CM));
+}
+
+/**
+ * @brief Set foreground layer pixel format.
+ * @details Sets the pixel format of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @api
+ */
+void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ chSysLock();
+ dma2dFgSetPixelFormatI(dma2dp, fmt);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer default color.
+ * @details Gets the default color of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @iclass
+ */
+dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_color_t)(DMA2D->FGCOLR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get foreground layer default color.
+ * @details Gets the default color of the foreground layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @api
+ */
+dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp) {
+
+ dma2d_color_t c;
+ chSysLock();
+ c = dma2dFgGetDefaultColorI(dma2dp);
+ chSysUnlock();
+ return c;
+}
+
+/**
+ * @brief Set foreground layer default color.
+ * @details Sets the default color of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @iclass
+ */
+void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->FGCOLR = (uint32_t)c & 0x00FFFFFF;
+}
+
+/**
+ * @brief Set foreground layer default color.
+ * @details Sets the default color of the foreground layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @api
+ */
+void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ chSysLock();
+ dma2dFgSetDefaultColorI(dma2dp, c);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer palette specifications.
+ * @details Gets the palette specifications of the foreground layer.
+ * @note The palette colors pointer is actually addressed to a @p volatile
+ * memory zone.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] palettep pointer to the palette specifications
+ *
+ * @iclass
+ */
+void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) {
+
+ uint32_t r;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(palettep != NULL);
+ (void)dma2dp;
+
+ r = DMA2D->FGPFCCR;
+ palettep->colorsp = (const void *)DMA2D->FGCLUT;
+ palettep->length = (uint16_t)((r & DMA2D_FGPFCCR_CS) >> 8) + 1;
+ palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_FGPFCCR_CCM) >> 4);
+}
+
+/**
+ * @brief Get foreground layer palette specifications.
+ * @details Gets the palette specifications of the foreground layer.
+ * @note The palette colors pointer is actually addressed to a @p volatile
+ * memory zone.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] palettep pointer to the palette specifications
+ *
+ * @api
+ */
+void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) {
+
+ chSysLock();
+ dma2dFgGetPaletteI(dma2dp, palettep);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer palette specifications.
+ * @details Sets the palette specifications of the foreground layer.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] palettep pointer to the palette specifications
+ *
+ * @sclass
+ */
+void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(palettep != NULL);
+ osalDbgCheck(palettep->colorsp != NULL);
+ osalDbgAssert(palettep->length > 0, "bounds");
+ osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds");
+ osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) ||
+ (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format");
+
+ DMA2D->FGCMAR = (uint32_t)palettep->colorsp;
+ DMA2D->FGPFCCR = (
+ (DMA2D->FGPFCCR & ~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM)) |
+ ((((uint32_t)palettep->length - 1) << 8) & DMA2D_FGPFCCR_CS) |
+ ((uint32_t)palettep->fmt << 4)
+ );
+
+ dma2dp->state = DMA2D_ACTIVE;
+ DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START;
+
+#if DMA2D_USE_WAIT
+ dma2dp->thread = chThdGetSelfX();
+ chSchGoSleepS(CH_STATE_SUSPENDED);
+#else
+ while (DMA2D->FGPFCCR & DMA2D_FGPFCCR_START)
+ chSchDoYieldS();
+#endif /* DMA2D_USE_WAIT */
+}
+
+/**
+ * @brief Set foreground layer palette specifications.
+ * @details Sets the palette specifications of the foreground layer.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] palettep pointer to the palette specifications
+ *
+ * @api
+ */
+void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) {
+
+ chSysLock();
+ dma2dFgSetPaletteS(dma2dp, palettep);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer specifications.
+ * @details Gets the foreground layer specifications at once.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(cfgp != NULL);
+
+ cfgp->bufferp = dma2dFgGetAddressI(dma2dp);
+ cfgp->wrap_offset = dma2dFgGetWrapOffsetI(dma2dp);
+ cfgp->fmt = dma2dFgGetPixelFormatI(dma2dp);
+ cfgp->def_color = dma2dFgGetDefaultColorI(dma2dp);
+ cfgp->const_alpha = dma2dFgGetConstantAlphaI(dma2dp);
+ if (cfgp->palettep != NULL)
+ dma2dFgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep);
+}
+
+/**
+ * @brief Get foreground layer specifications.
+ * @details Gets the foreground layer specifications at once.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dFgGetLayerI(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer specifications.
+ * @details Sets the foreground layer specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @sclass
+ */
+void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(cfgp != NULL);
+
+ dma2dFgSetAddressI(dma2dp, cfgp->bufferp);
+ dma2dFgSetWrapOffsetI(dma2dp, cfgp->wrap_offset);
+ dma2dFgSetPixelFormatI(dma2dp, cfgp->fmt);
+ dma2dFgSetDefaultColorI(dma2dp, cfgp->def_color);
+ dma2dFgSetConstantAlphaI(dma2dp, cfgp->const_alpha);
+ if (cfgp->palettep != NULL)
+ dma2dFgSetPaletteS(dma2dp, cfgp->palettep);
+}
+
+/**
+ * @brief Set foreground layer specifications.
+ * @details Sets the foreground layer specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ * @note This function should not be called while the DMA2D is already
+ * executing a job, otherwise the appropriate error interrupt might be
+ * invoked.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dFgSetConfigS(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D output layer methods
+ * @{
+ */
+
+/**
+ * @brief Get output layer buffer address.
+ * @details Gets the buffer address of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @iclass
+ */
+void *dma2dOutGetAddressI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (void *)DMA2D->OMAR;
+}
+
+/**
+ * @brief Get output layer buffer address.
+ * @details Gets the buffer address of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return buffer address
+ *
+ * @api
+ */
+void *dma2dOutGetAddress(DMA2DDriver *dma2dp) {
+
+ void *bufferp;
+ chSysLock();
+ bufferp = dma2dOutGetAddressI(dma2dp);
+ chSysUnlock();
+ return bufferp;
+}
+
+/**
+ * @brief Set output layer buffer address.
+ * @details Sets the buffer address of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @iclass
+ */
+void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(dma2dIsAligned(bufferp, dma2dOutGetPixelFormatI(dma2dp)));
+ (void)dma2dp;
+
+ DMA2D->OMAR = (uint32_t)bufferp;
+}
+
+/**
+ * @brief Set output layer buffer address.
+ * @details Sets the buffer address of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] bufferp buffer address
+ *
+ * @api
+ */
+void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp) {
+
+ chSysLock();
+ dma2dOutSetAddressI(dma2dp, bufferp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get output layer wrap offset.
+ * @details Gets the buffer line wrap offset of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @iclass
+ */
+size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (size_t)(DMA2D->OOR & DMA2D_OOR_LO);
+}
+
+/**
+ * @brief Get output layer wrap offset.
+ * @details Gets the buffer line wrap offset of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return wrap offset, in pixels
+ *
+ * @api
+ */
+size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp) {
+
+ size_t offset;
+ chSysLock();
+ offset = dma2dOutGetWrapOffsetI(dma2dp);
+ chSysUnlock();
+ return offset;
+}
+
+/**
+ * @brief Set output layer wrap offset.
+ * @details Sets the buffer line wrap offset of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @iclass
+ */
+void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds");
+ (void)dma2dp;
+
+ DMA2D->OOR = ((DMA2D->OOR & ~DMA2D_OOR_LO) |
+ ((uint32_t)offset & DMA2D_OOR_LO));
+}
+
+/**
+ * @brief Set output layer wrap offset.
+ * @details Sets the buffer line wrap offset of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] offset wrap offset, in pixels
+ *
+ * @api
+ */
+void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) {
+
+ chSysLock();
+ dma2dOutSetWrapOffsetI(dma2dp, offset);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get output layer pixel format.
+ * @details Gets the pixel format of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @iclass
+ */
+dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_pixfmt_t)(DMA2D->OPFCCR & DMA2D_OPFCCR_CM);
+}
+
+/**
+ * @brief Get output layer pixel format.
+ * @details Gets the pixel format of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return pixel format
+ *
+ * @api
+ */
+dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp) {
+
+ dma2d_pixfmt_t fmt;
+ chSysLock();
+ fmt = dma2dOutGetPixelFormatI(dma2dp);
+ chSysUnlock();
+ return fmt;
+}
+
+/**
+ * @brief Set output layer pixel format.
+ * @details Sets the pixel format of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @iclass
+ */
+void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgAssert(fmt <= DMA2D_MAX_OUTPIXFMT_ID, "bounds");
+ (void)dma2dp;
+
+ DMA2D->OPFCCR = ((DMA2D->OPFCCR & ~DMA2D_OPFCCR_CM) |
+ ((uint32_t)fmt & DMA2D_OPFCCR_CM));
+}
+
+/**
+ * @brief Set output layer pixel format.
+ * @details Sets the pixel format of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] fmt pixel format
+ *
+ * @api
+ */
+void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) {
+
+ chSysLock();
+ dma2dOutSetPixelFormatI(dma2dp, fmt);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get output layer default color.
+ * @details Gets the default color of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, chosen output format
+ *
+ * @iclass
+ */
+dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ (void)dma2dp;
+
+ return (dma2d_color_t)(DMA2D->OCOLR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get output layer default color.
+ * @details Gets the default color of the output layer.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ *
+ * @return default color, chosen output format
+ *
+ * @api
+ */
+dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp) {
+
+ dma2d_color_t c;
+ chSysLock();
+ c = dma2dOutGetDefaultColorI(dma2dp);
+ chSysUnlock();
+ return c;
+}
+
+/**
+ * @brief Set output layer default color.
+ * @details Sets the default color of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, chosen output format
+ *
+ * @iclass
+ */
+void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ (void)dma2dp;
+
+ DMA2D->OCOLR = (uint32_t)c & 0x00FFFFFF;
+}
+
+/**
+ * @brief Set output layer default color.
+ * @details Sets the default color of the output layer.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] c default color, chosen output format
+ *
+ * @api
+ */
+void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) {
+
+ chSysLock();
+ dma2dOutSetDefaultColorI(dma2dp, c);
+ chSysUnlock();
+}
+
+/**
+ * @brief Get output layer specifications.
+ * @details Gets the output layer specifications at once.
+ * @note Constant alpha and palette specifications are ignored.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgCheck(cfgp != NULL);
+
+ cfgp->bufferp = dma2dOutGetAddressI(dma2dp);
+ cfgp->wrap_offset = dma2dOutGetWrapOffsetI(dma2dp);
+ cfgp->fmt = dma2dOutGetPixelFormatI(dma2dp);
+ cfgp->def_color = dma2dOutGetDefaultColorI(dma2dp);
+}
+
+/**
+ * @brief Get output layer specifications.
+ * @details Gets the output layer specifications at once.
+ * @note Constant alpha and palette specifications are ignored.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dOutGetLayerI(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Set output layer specifications.
+ * @details Sets the output layer specifications at once.
+ * @note Constant alpha and palette specifications are ignored.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(dma2dp == &DMA2DD1);
+ osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready");
+ osalDbgCheck(cfgp != NULL);
+
+ dma2dOutSetAddressI(dma2dp, cfgp->bufferp);
+ dma2dOutSetWrapOffsetI(dma2dp, cfgp->wrap_offset);
+ dma2dOutSetPixelFormatI(dma2dp, cfgp->fmt);
+ dma2dOutSetDefaultColorI(dma2dp, cfgp->def_color);
+}
+
+/**
+ * @brief Set output layer specifications.
+ * @details Sets the output layer specifications at once.
+ * @note Constant alpha and palette specifications are ignored.
+ * @pre DMA2D is ready.
+ *
+ * @param[in] dma2dp pointer to the @p DMA2DDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) {
+
+ chSysLock();
+ dma2dOutSetConfigI(dma2dp, cfgp);
+ chSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name DMA2D helper functions
+ * @{
+ */
+
+/**
+ * @brief Compute pixel address.
+ * @details Computes the buffer address of a pixel, given the buffer
+ * specifications.
+ *
+ * @param[in] originp buffer origin address
+ * @param[in] pitch buffer pitch, in bytes
+ * @param[in] fmt buffer pixel format
+ * @param[in] x horizontal pixel coordinate
+ * @param[in] y vertical pixel coordinate
+ *
+ * @return pixel address, constant data
+ *
+ * @api
+ */
+const void *dma2dComputeAddressConst(const void *originp, size_t pitch,
+ dma2d_pixfmt_t fmt,
+ uint16_t x, uint16_t y) {
+
+ osalDbgCheck(pitch > 0);
+
+ switch (fmt) {
+ case DMA2D_FMT_ARGB8888:
+ return (const void *)((uintptr_t)originp +
+ (uintptr_t)y * pitch + (uintptr_t)x * 4);
+ case DMA2D_FMT_RGB888:
+ return (const void *)((uintptr_t)originp +
+ (uintptr_t)y * pitch + (uintptr_t)x * 3);
+ case DMA2D_FMT_RGB565:
+ case DMA2D_FMT_ARGB1555:
+ case DMA2D_FMT_ARGB4444:
+ case DMA2D_FMT_AL88:
+ return (const void *)((uintptr_t)originp +
+ (uintptr_t)y * pitch + (uintptr_t)x * 2);
+ case DMA2D_FMT_L8:
+ case DMA2D_FMT_AL44:
+ case DMA2D_FMT_A8:
+ return (const void *)((uintptr_t)originp +
+ (uintptr_t)y * pitch + (uintptr_t)x);
+ case DMA2D_FMT_L4:
+ case DMA2D_FMT_A4:
+ osalDbgAssert((x & 1) == 0, "not aligned");
+ return (const void *)((uintptr_t)originp +
+ (uintptr_t)y * pitch + (uintptr_t)x / 2);
+ default:
+ osalDbgAssert(false, "invalid format");
+ return NULL;
+ }
+}
+
+/**
+ * @brief Address is aligned.
+ * @details Tells whether the address is aligned with the provided pixel format.
+ *
+ * @param[in] bufferp address
+ * @param[in] fmt pixel format
+ *
+ * @return address is aligned
+ *
+ * @api
+ */
+bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt) {
+
+ switch (fmt) {
+ case DMA2D_FMT_ARGB8888:
+ case DMA2D_FMT_RGB888:
+ return ((uintptr_t)bufferp & 3) == 0; /* 32-bit alignment.*/
+ case DMA2D_FMT_RGB565:
+ case DMA2D_FMT_ARGB1555:
+ case DMA2D_FMT_ARGB4444:
+ case DMA2D_FMT_AL88:
+ return ((uintptr_t)bufferp & 1) == 0; /* 16-bit alignment.*/
+ case DMA2D_FMT_L8:
+ case DMA2D_FMT_AL44:
+ case DMA2D_FMT_L4:
+ case DMA2D_FMT_A8:
+ case DMA2D_FMT_A4:
+ return true; /* 8-bit alignment.*/
+ default:
+ osalDbgAssert(false, "invalid format");
+ return false;
+ }
+}
+
+/**
+ * @brief Compute bits per pixel.
+ * @details Computes the bits per pixel for the specified pixel format.
+ *
+ * @param[in] fmt pixel format
+ *
+ * @retuen bits per pixel
+ *
+ * @api
+ */
+size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt) {
+
+ osalDbgAssert(fmt < DMA2D_MAX_PIXFMT_ID, "invalid format");
+
+ return (size_t)dma2d_bpp[(unsigned)fmt];
+}
+
+#if DMA2D_USE_SOFTWARE_CONVERSIONS || defined(__DOXYGEN__)
+
+/**
+ * @brief Convert from ARGB-8888.
+ * @details Converts an ARGB-8888 color to the specified pixel format.
+ *
+ * @param[in] c color, ARGB-8888
+ * @param[in] fmt target pixel format
+ *
+ * @return raw color value for the target pixel format, left
+ * padded with zeros.
+ *
+ * @api
+ */
+dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) {
+
+ switch (fmt) {
+ case DMA2D_FMT_ARGB8888: {
+ return c;
+ }
+ case DMA2D_FMT_RGB888: {
+ return (c & 0x00FFFFFF);
+ }
+ case DMA2D_FMT_RGB565: {
+ return (((c & 0x000000F8) >> ( 8 - 5)) |
+ ((c & 0x0000FC00) >> (16 - 11)) |
+ ((c & 0x00F80000) >> (24 - 16)));
+ }
+ case DMA2D_FMT_ARGB1555: {
+ return (((c & 0x000000F8) >> ( 8 - 5)) |
+ ((c & 0x0000F800) >> (16 - 10)) |
+ ((c & 0x00F80000) >> (24 - 15)) |
+ ((c & 0x80000000) >> (32 - 16)));
+ }
+ case DMA2D_FMT_ARGB4444: {
+ return (((c & 0x000000F0) >> ( 8 - 4)) |
+ ((c & 0x0000F000) >> (16 - 8)) |
+ ((c & 0x00F00000) >> (24 - 12)) |
+ ((c & 0xF0000000) >> (32 - 16)));
+ }
+ case DMA2D_FMT_L8: {
+ return (c & 0x000000FF);
+ }
+ case DMA2D_FMT_AL44: {
+ return (((c & 0x000000F0) >> ( 8 - 4)) |
+ ((c & 0xF0000000) >> (32 - 8)));
+ }
+ case DMA2D_FMT_AL88: {
+ return (((c & 0x000000FF) >> ( 8 - 8)) |
+ ((c & 0xFF000000) >> (32 - 16)));
+ }
+ case DMA2D_FMT_L4: {
+ return (c & 0x0000000F);
+ }
+ case DMA2D_FMT_A8: {
+ return ((c & 0xFF000000) >> (32 - 8));
+ }
+ case DMA2D_FMT_A4: {
+ return ((c & 0xF0000000) >> (32 - 4));
+ }
+ default:
+ osalDbgAssert(false, "invalid format");
+ return 0;
+ }
+}
+
+/**
+ * @brief Convert to ARGB-8888.
+ * @details Converts color of the specified pixel format to an ARGB-8888 color.
+ *
+ * @param[in] c color for the source pixel format, left padded with
+ * zeros.
+ * @param[in] fmt source pixel format
+ *
+ * @return color in ARGB-8888 format
+ *
+ * @api
+ */
+dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) {
+
+ switch (fmt) {
+ case DMA2D_FMT_ARGB8888: {
+ return c;
+ }
+ case DMA2D_FMT_RGB888: {
+ return ((c & 0x00FFFFFF) | 0xFF000000);
+ }
+ case DMA2D_FMT_RGB565: {
+ register dma2d_color_t output = 0xFF000000;
+ if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007);
+ if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300);
+ if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000);
+ return output;
+ }
+ case DMA2D_FMT_ARGB1555: {
+ register dma2d_color_t output = 0x00000000;
+ if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007);
+ if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700);
+ if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000);
+ if (c & 0x8000) output |= 0xFF000000;
+ return output;
+ }
+ case DMA2D_FMT_ARGB4444: {
+ register dma2d_color_t output = 0x00000000;
+ if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F);
+ if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00);
+ if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000);
+ if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000);
+ return output;
+ }
+ case DMA2D_FMT_L8: {
+ return (c & 0xFF) | 0xFF000000;
+ }
+ case DMA2D_FMT_AL44: {
+ register dma2d_color_t output = 0x00000000;
+ if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F);
+ if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000);
+ return output;
+ }
+ case DMA2D_FMT_AL88: {
+ return (((c & 0x00FF) << ( 8 - 8)) |
+ ((c & 0xFF00) << (32 - 16)));
+ }
+ case DMA2D_FMT_L4: {
+ return ((c & 0x0F) | 0xFF000000);
+ }
+ case DMA2D_FMT_A8: {
+ return ((c & 0xFF) << (32 - 8));
+ }
+ case DMA2D_FMT_A4: {
+ return ((c & 0x0F) << (32 - 4));
+ }
+ default:
+ osalDbgAssert(false, "invalid format");
+ return 0;
+ }
+}
+
+#endif /* DMA2D_NEED_CONVERSIONS */
+
+/** @} */
+
+/** @} */
+
+#endif /* STM32_DMA2D_USE_DMA2D */
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.h b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.h new file mode 100644 index 0000000..29efa71 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.h @@ -0,0 +1,664 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file stm32_dma2d.h
+ * @brief DMA2D/Chrom-ART driver.
+ *
+ * @addtogroup dma2d
+ * @{
+ */
+
+#ifndef _STM32_DMA2D_H_
+#define _STM32_DMA2D_H_
+
+/**
+ * @brief Using the DMA2D driver.
+ */
+#if !defined(STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__)
+#define STM32_DMA2D_USE_DMA2D (FALSE)
+#endif
+
+#if (TRUE == STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name DMA2D job modes
+ * @{
+ */
+#define DMA2D_JOB_COPY (0 << 16) /**< Copy, replace(FG only).*/
+#define DMA2D_JOB_CONVERT (1 << 16) /**< Copy, convert (FG + PFC).*/
+#define DMA2D_JOB_BLEND (2 << 16) /**< Copy, blend (FG + BG + PFC).*/
+#define DMA2D_JOB_CONST (3 << 16) /**< Default color only (FG REG).*/
+/** @} */
+
+/**
+ * @name DMA2D enable flag
+ * @{
+ */
+#define DMA2D_EF_ENABLE (1 << 0) /**< DMA2D enabled.*/
+#define DMA2D_EF_DITHER (1 << 16) /**< Dithering enabled.*/
+#define DMA2D_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/
+#define DMA2D_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/
+#define DMA2D_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/
+#define DMA2D_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/
+
+/** Enable flags mask. */
+#define DMA2D_EF_MASK \
+ (DMA2D_EF_ENABLE | DMA2D_EF_DITHER | DMA2D_EF_PIXCLK_INVERT | \
+ DMA2D_EF_DATAEN_HIGH | DMA2D_EF_VSYNC_HIGH | DMA2D_EF_HSYNC_HIGH)
+/** @} */
+
+/**
+ * @name DMA2D layer enable flags
+ * @{
+ */
+#define DMA2D_LEF_ENABLE (1 << 0) /**< Layer enabled*/
+#define DMA2D_LEF_KEYING (1 << 1) /**< Color keying enabled.*/
+#define DMA2D_LEF_PALETTE (1 << 4) /**< Palette enabled.*/
+
+/** Layer enable flag masks. */
+#define DMA2D_LEF_MASK \
+ (DMA2D_LEF_ENABLE | DMA2D_LEF_KEYING | DMA2D_LEF_PALETTE)
+/** @} */
+
+/**
+ * @name DMA2D pixel formats
+ * @{
+ */
+#define DMA2D_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/
+#define DMA2D_FMT_RGB888 (1) /**< RGB-888 format.*/
+#define DMA2D_FMT_RGB565 (2) /**< RGB-565 format.*/
+#define DMA2D_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/
+#define DMA2D_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/
+#define DMA2D_FMT_L8 (5) /**< L-8 format.*/
+#define DMA2D_FMT_AL44 (6) /**< AL-44 format.*/
+#define DMA2D_FMT_AL88 (7) /**< AL-88 format.*/
+#define DMA2D_FMT_L4 (8) /**< L-4 format.*/
+#define DMA2D_FMT_A8 (9) /**< A-8 format.*/
+#define DMA2D_FMT_A4 (10) /**< A-4 format.*/
+/** @} */
+
+/**
+ * @name DMA2D pixel format aliased raw masks
+ * @{
+ */
+#define DMA2D_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/
+#define DMA2D_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/
+#define DMA2D_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/
+#define DMA2D_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/
+#define DMA2D_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/
+#define DMA2D_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/
+#define DMA2D_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/
+#define DMA2D_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/
+#define DMA2D_XMASK_L4 (0x0000000F) /**< L-4 aliased mask.*/
+#define DMA2D_XMASK_A8 (0xFF000000) /**< A-8 aliased mask.*/
+#define DMA2D_XMASK_A4 (0xF0000000) /**< A-4 aliased mask.*/
+/** @} */
+
+/**
+ * @name DMA2D alpha modes
+ * @{
+ */
+#define DMA2D_ALPHA_KEEP (0x00000000) /**< Original alpha channel.*/
+#define DMA2D_ALPHA_REPLACE (0x00010000) /**< Replace with constant.*/
+#define DMA2D_ALPHA_MODULATE (0x00020000) /**< Modulate with constant.*/
+/** @} */
+
+/**
+ * @name DMA2D parameter bounds
+ * @{
+ */
+
+#define DMA2D_MIN_PIXFMT_ID (0) /**< Minimum pixel format ID.*/
+#define DMA2D_MAX_PIXFMT_ID (11) /**< Maximum pixel format ID.*/
+#define DMA2D_MIN_OUTPIXFMT_ID (0) /**< Minimum output pixel format ID.*/
+#define DMA2D_MAX_OUTPIXFMT_ID (4) /**< Maximum output pixel format ID.*/
+
+#define DMA2D_MAX_OFFSET ((1 << 14) - 1)
+
+#define DMA2D_MAX_PALETTE_LENGTH (256) /***/
+
+#define DMA2D_MAX_WIDTH ((1 << 14) - 1)
+#define DMA2D_MAX_HEIGHT ((1 << 16) - 1)
+
+#define DMA2D_MAX_WATERMARK_POS ((1 << 16) - 1)
+
+#define DMA2D_MAX_DEADTIME_CYCLES ((1 << 8) - 1)
+
+/** @} */
+
+/**
+ * @name DMA2D basic ARGB-8888 colors.
+ * @{
+ */
+/* Microsoft Windows default 16-color palette.*/
+#define DMA2D_COLOR_BLACK (0xFF000000)
+#define DMA2D_COLOR_MAROON (0xFF800000)
+#define DMA2D_COLOR_GREEN (0xFF008000)
+#define DMA2D_COLOR_OLIVE (0xFF808000)
+#define DMA2D_COLOR_NAVY (0xFF000080)
+#define DMA2D_COLOR_PURPLE (0xFF800080)
+#define DMA2D_COLOR_TEAL (0xFF008080)
+#define DMA2D_COLOR_SILVER (0xFFC0C0C0)
+#define DMA2D_COLOR_GRAY (0xFF808080)
+#define DMA2D_COLOR_RED (0xFFFF0000)
+#define DMA2D_COLOR_LIME (0xFF00FF00)
+#define DMA2D_COLOR_YELLOW (0xFFFFFF00)
+#define DMA2D_COLOR_BLUE (0xFF0000FF)
+#define DMA2D_COLOR_FUCHSIA (0xFFFF00FF)
+#define DMA2D_COLOR_AQUA (0xFF00FFFF)
+#define DMA2D_COLOR_WHITE (0xFFFFFFFF)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name DMA2D configuration options
+ * @{
+ */
+
+/**
+ * @brief DMA2D event interrupt priority level setting.
+ */
+#if !defined(STM32_DMA2D_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DMA2D_IRQ_PRIORITY (11)
+#endif
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(DMA2D_USE_WAIT) || defined(__DOXYGEN__)
+#define DMA2D_USE_WAIT (TRUE)
+#endif
+
+/**
+ * @brief Enables the @p dma2dAcquireBus() and @p dma2dReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(DMA2D_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define DMA2D_USE_MUTUAL_EXCLUSION (TRUE)
+#endif
+
+/**
+ * @brief Provides software color conversion functions.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
+#define DMA2D_USE_SOFTWARE_CONVERSIONS (TRUE)
+#endif
+
+/**
+ * @brief Enables checks for DMA2D functions.
+ * @note Disabling this option saves both code and data space.
+ * @note Disabling checks by ChibiOS will automatically disable DMA2D checks.
+ */
+#if !defined(DMA2D_USE_CHECKS) || defined(__DOXYGEN__)
+#define DMA2D_USE_CHECKS (TRUE)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (TRUE != STM32_HAS_DMA2D)
+#error "DMA2D must be present when using the DMA2D subsystem"
+#endif
+
+#if (TRUE != STM32_DMA2D_USE_DMA2D) && (TRUE != STM32_HAS_DMA2D)
+#error "DMA2D not present in the selected device"
+#endif
+
+#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
+#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES)
+#error "DMA2D_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* Complex types forwarding.*/
+typedef union dma2d_coloralias_t dma2d_coloralias_t;
+typedef struct dma2d_palcfg_t dma2d_palcfg_t;
+typedef struct dma2d_laycfg_t dma2d_layercfg_t;
+typedef struct DMA2DConfig DMA2DConfig;
+typedef enum dma2d_state_t dma2d_state_t;
+typedef struct DMA2DDriver DMA2DDriver;
+
+/**
+ * @name DMA2D Data types
+ * @{
+ */
+
+/**
+ * @brief DMA2D generic color.
+ */
+typedef uint32_t dma2d_color_t;
+
+/**
+ * @brief DMA2D color aliases.
+ * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B).
+ * Padding fields are prefixed with <tt>'x'</tt>, and should be clear
+ * (all 0) before compression and set (all 1) after expansion.
+ */
+typedef union dma2d_coloralias_t {
+ struct {
+ unsigned b : 8;
+ unsigned g : 8;
+ unsigned r : 8;
+ unsigned a : 8;
+ } argb8888; /**< Mapped ARGB-8888 bits.*/
+ struct {
+ unsigned b : 8;
+ unsigned g : 8;
+ unsigned r : 8;
+ unsigned xa : 8;
+ } rgb888; /**< Mapped RGB-888 bits.*/
+ struct {
+ unsigned xb : 3;
+ unsigned b : 5;
+ unsigned xg : 2;
+ unsigned g : 6;
+ unsigned xr : 3;
+ unsigned r : 5;
+ unsigned xa : 8;
+ } rgb565; /**< Mapped RGB-565 bits.*/
+ struct {
+ unsigned xb : 3;
+ unsigned b : 5;
+ unsigned xg : 3;
+ unsigned g : 5;
+ unsigned xr : 3;
+ unsigned r : 5;
+ unsigned xa : 7;
+ unsigned a : 1;
+ } argb1555; /**< Mapped ARGB-1555 values.*/
+ struct {
+ unsigned xb : 4;
+ unsigned b : 4;
+ unsigned xg : 4;
+ unsigned g : 4;
+ unsigned xr : 4;
+ unsigned r : 4;
+ unsigned xa : 4;
+ unsigned a : 4;
+ } argb4444; /**< Mapped ARGB-4444 values.*/
+ struct {
+ unsigned l : 8;
+ unsigned x : 16;
+ unsigned xa : 8;
+ } l8; /**< Mapped L-8 bits.*/
+ struct {
+ unsigned xl : 4;
+ unsigned l : 4;
+ unsigned x : 16;
+ unsigned xa : 4;
+ unsigned a : 4;
+ } al44; /**< Mapped AL-44 bits.*/
+ struct {
+ unsigned l : 8;
+ unsigned x : 16;
+ unsigned a : 8;
+ } al88; /**< Mapped AL-88 bits.*/
+ struct {
+ unsigned l : 4;
+ unsigned xl : 4;
+ unsigned x : 16;
+ unsigned xa : 8;
+ } l4; /**< Mapped L-4 bits.*/
+ struct {
+ unsigned x : 24;
+ unsigned a : 8;
+ } a8; /**< Mapped A-8 bits.*/
+ struct {
+ unsigned x : 24;
+ unsigned xa : 4;
+ unsigned a : 4;
+ } a4; /**< Mapped A-4 bits.*/
+ dma2d_color_t aliased; /**< Aliased raw bits.*/
+} dma2d_coloralias_t;
+
+/**
+ * @brief DMA2D job (transfer) mode.
+ */
+typedef uint32_t dma2d_jobmode_t;
+
+/**
+ * @brief DMA2D pixel format.
+ */
+typedef uint32_t dma2d_pixfmt_t;
+
+/**
+ * @brief DMA2D alpha mode.
+ */
+typedef uint32_t dma2d_amode_t;
+
+/**
+ * @brief DMA2D ISR callback.
+ */
+typedef void (*dma2d_isrcb_t)(DMA2DDriver *dma2dp);
+
+/**
+ * @brief DMA2D palette specifications.
+ */
+typedef struct dma2d_palcfg_t {
+ const void *colorsp; /**< Pointer to color entries.*/
+ uint16_t length; /**< Number of color entries.*/
+ dma2d_pixfmt_t fmt; /**< Format, RGB-888 or ARGB-8888.*/
+} dma2d_palcfg_t;
+
+/**
+ * @brief DMA2D layer specifications.
+ */
+typedef struct dma2d_layercfg_t {
+ void *bufferp; /**< Frame buffer address.*/
+ size_t wrap_offset; /**< Offset between lines, in pixels.*/
+ dma2d_pixfmt_t fmt; /**< Pixel format.*/
+ dma2d_color_t def_color; /**< Default color, RGB-888.*/
+ uint8_t const_alpha; /**< Constant alpha factor.*/
+ const dma2d_palcfg_t *palettep; /**< Palette specs, or @p NULL.*/
+} dma2d_laycfg_t;
+
+/**
+ * @brief DMA2D driver configuration.
+ */
+typedef struct DMA2DConfig {
+ /* ISR callbacks.*/
+ dma2d_isrcb_t cfgerr_isr; /**< Configuration error, or @p NULL.*/
+ dma2d_isrcb_t paltrfdone_isr; /**< Palette transfer done, or @p NULL.*/
+ dma2d_isrcb_t palacserr_isr; /**< Palette access error, or @p NULL.*/
+ dma2d_isrcb_t trfwmark_isr; /**< Transfer watermark, or @p NULL.*/
+ dma2d_isrcb_t trfdone_isr; /**< Transfer complete, or @p NULL.*/
+ dma2d_isrcb_t trferr_isr; /**< Transfer error, or @p NULL.*/
+} DMA2DConfig;
+
+/**
+ * @brief DMA2D driver state.
+ */
+typedef enum dma2d_state_t {
+ DMA2D_UNINIT = (0), /**< Not initialized.*/
+ DMA2D_STOP = (1), /**< Stopped.*/
+ DMA2D_READY = (2), /**< Ready.*/
+ DMA2D_ACTIVE = (3), /**< Executing commands.*/
+ DMA2D_PAUSED = (4), /**< Transfer suspended.*/
+} dma2d_state_t;
+
+/**
+ * @brief DMA2D driver.
+ */
+typedef struct DMA2DDriver {
+ dma2d_state_t state; /**< Driver state.*/
+ const DMA2DConfig *config; /**< Driver configuration.*/
+
+ /* Multithreading stuff.*/
+#if (TRUE == DMA2D_USE_WAIT) || defined(__DOXYGEN__)
+ thread_t *thread; /**< Waiting thread.*/
+#endif /* DMA2D_USE_WAIT */
+#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ mutex_t lock; /**< Multithreading lock.*/
+#elif (TRUE == CH_CFG_USE_SEMAPHORES)
+ semaphore_t lock; /**< Multithreading lock.*/
+#endif
+#endif /* DMA2D_USE_MUTUAL_EXCLUSION */
+} DMA2DDriver;
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Makes an ARGB-8888 value from byte components.
+ *
+ * @param[in] a alpha byte component
+ * @param[in] r red byte component
+ * @param[in] g green byte component
+ * @param[in] b blue byte component
+ *
+ * @return color in ARGB-8888 format
+ *
+ * @api
+ */
+#define dma2dMakeARGB8888(a, r, g, b) \
+ ((((dma2d_color_t)(a) & 0xFF) << 24) | \
+ (((dma2d_color_t)(r) & 0xFF) << 16) | \
+ (((dma2d_color_t)(g) & 0xFF) << 8) | \
+ (((dma2d_color_t)(b) & 0xFF) << 0))
+
+/**
+ * @brief Compute bytes per pixel.
+ * @details Computes the bytes per pixel for the specified pixel format.
+ * Rounds to the ceiling.
+ *
+ * @param[in] fmt pixel format
+ *
+ * @return bytes per pixel
+ *
+ * @api
+ */
+#define dma2dBytesPerPixel(fmt) \
+ ((dma2dBitsPerPixel(fmt) + 7) >> 3)
+
+/**
+ * @brief Compute pixel address.
+ * @details Computes the buffer address of a pixel, given the buffer
+ * specifications.
+ *
+ * @param[in] originp buffer origin address
+ * @param[in] pitch buffer pitch, in bytes
+ * @param[in] fmt buffer pixel format
+ * @param[in] x horizontal pixel coordinate
+ * @param[in] y vertical pixel coordinate
+ *
+ * @return pixel address
+ *
+ * @api
+ */
+#define dma2dComputeAddress(originp, pitch, fmt, x, y) \
+ ((void *)dma2dComputeAddressConst(originp, pitch, fmt, x, y))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern DMA2DDriver DMA2DD1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /* Driver methods.*/
+ void dma2dInit(void);
+ void dma2dObjectInit(DMA2DDriver *dma2dp);
+ dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp);
+ dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp);
+ void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp);
+ void dma2dStop(DMA2DDriver *dma2dp);
+#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
+ void dma2dAcquireBusS(DMA2DDriver *dma2dp);
+ void dma2dAcquireBus(DMA2DDriver *dma2dp);
+ void dma2dReleaseBusS(DMA2DDriver *dma2dp);
+ void dma2dReleaseBus(DMA2DDriver *dma2dp);
+#endif /* DMA2D_USE_MUTUAL_EXCLUSION */
+
+ /* Global methods.*/
+ uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp);
+ uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp);
+ void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line);
+ void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line);
+ bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp);
+ bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp);
+ void dma2dEnableWatermarkI(DMA2DDriver *dma2dp);
+ void dma2dEnableWatermark(DMA2DDriver *dma2dp);
+ void dma2dDisableWatermarkI(DMA2DDriver *dma2dp);
+ void dma2dDisableWatermark(DMA2DDriver *dma2dp);
+ uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp);
+ uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp);
+ void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles);
+ void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles);
+ bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp);
+ bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp);
+ void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp);
+ void dma2dEnableDeadTime(DMA2DDriver *dma2dp);
+ void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp);
+ void dma2dDisableDeadTime(DMA2DDriver *dma2dp);
+
+ /* Job methods.*/
+ dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp);
+ dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp);
+ void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode);
+ void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode);
+ void dma2dJobGetSizeI(DMA2DDriver *dma2dp,
+ uint16_t *widthp, uint16_t *heightp);
+ void dma2dJobGetSize(DMA2DDriver *dma2dp,
+ uint16_t *widthp, uint16_t *heightp);
+ void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height);
+ void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height);
+ bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp);
+ bool dma2dJobIsExecuting(DMA2DDriver *dma2dp);
+ void dma2dJobStartI(DMA2DDriver *dma2dp);
+ void dma2dJobStart(DMA2DDriver *dma2dp);
+ void dma2dJobExecuteS(DMA2DDriver *dma2dp);
+ void dma2dJobExecute(DMA2DDriver *dma2dp);
+ void dma2dJobSuspendI(DMA2DDriver *dma2dp);
+ void dma2dJobSuspend(DMA2DDriver *dma2dp);
+ void dma2dJobResumeI(DMA2DDriver *dma2dp);
+ void dma2dJobResume(DMA2DDriver *dma2dp);
+ void dma2dJobAbortI(DMA2DDriver *dma2dp);
+ void dma2dJobAbort(DMA2DDriver *dma2dp);
+
+ /* Background layer methods.*/
+ void *dma2dBgGetAddressI(DMA2DDriver *dma2dp);
+ void *dma2dBgGetAddress(DMA2DDriver *dma2dp);
+ void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
+ void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp);
+ size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp);
+ size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp);
+ void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
+ void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
+ uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp);
+ uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp);
+ void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a);
+ void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a);
+ dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp);
+ dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp);
+ void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode);
+ void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode);
+ dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp);
+ dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp);
+ void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp);
+ dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp);
+ void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
+ void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
+ void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
+ void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
+ void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+ void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+
+ /* Foreground layer methods.*/
+ void *dma2dFgGetAddressI(DMA2DDriver *dma2dp);
+ void *dma2dFgGetAddress(DMA2DDriver *dma2dp);
+ void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
+ void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp);
+ size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp);
+ size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp);
+ void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
+ void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
+ uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp);
+ uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp);
+ void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a);
+ void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a);
+ dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp);
+ dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp);
+ void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode);
+ void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode);
+ dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp);
+ dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp);
+ void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp);
+ dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp);
+ void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
+ void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
+ void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
+ void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
+ void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+ void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+
+ /* Output layer methods.*/
+ void *dma2dOutGetAddressI(DMA2DDriver *dma2dp);
+ void *dma2dOutGetAddress(DMA2DDriver *dma2dp);
+ void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
+ void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp);
+ size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp);
+ size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp);
+ void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
+ void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
+ dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp);
+ dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp);
+ void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
+ dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp);
+ dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp);
+ void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
+ void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
+ void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+ void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
+
+ /* Helper functions.*/
+ const void *dma2dComputeAddressConst(const void *originp, size_t pitch,
+ dma2d_pixfmt_t fmt,
+ uint16_t x, uint16_t y);
+ bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt);
+ size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt);
+#if (TRUE == DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
+ dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt);
+ dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt);
+#endif /* DMA2D_USE_SOFTWARE_CONVERSIONS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_DMA2D_USE_DMA2D */
+
+#endif /* _STM32_DMA2D_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c index 01f6183..63f4af1 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c @@ -24,7 +24,7 @@ #include "hal.h" #include "fsmc.h" -#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM || \ +#if (HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM) || \ defined(__DOXYGEN__) /*===========================================================================*/ @@ -119,7 +119,7 @@ void fsmc_init(void) { void fsmc_start(FSMCDriver *fsmcp) { osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), - "invalid state"); + "invalid state"); if (fsmcp->state == FSMC_STOP) { /* Enables the peripheral.*/ @@ -174,12 +174,12 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); #if STM32_NAND_USE_FSMC_NAND1 - if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK){ + if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); } #endif #if STM32_NAND_USE_FSMC_NAND2 - if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK){ + if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c index f6009dd..33b9e80 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c @@ -102,7 +102,7 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) { SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; /* Step 4: Insert delay (tipically 100uS).*/ - osalThreadSleepMilliseconds(100); + osalThreadSleepMilliseconds(1); /* Step 5: Configure a PALL (precharge all) command.*/ _sdram_wait_ready(); diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c index d187161..cd2f421 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c @@ -70,7 +70,7 @@ NANDDriver NANDD2; * * @notapi */ -static void wakeup_isr(NANDDriver *nandp){ +static void wakeup_isr(NANDDriver *nandp) { osalDbgCheck(nandp->thread != NULL); osalThreadResumeI(&nandp->thread, MSG_OK); @@ -91,7 +91,7 @@ static void nand_lld_suspend_thread(NANDDriver *nandp) { * * @param[in] nandp pointer to the @p NANDDriver object */ -static uint32_t calc_eccps(NANDDriver *nandp){ +static uint32_t calc_eccps(NANDDriver *nandp) { uint32_t i = 0; uint32_t eccps = nandp->config->page_data_size; @@ -148,7 +148,7 @@ static void nand_ready_isr_disable(NANDDriver *nandp) { * * @notapi */ -static void nand_isr_handler (NANDDriver *nandp){ +static void nand_isr_handler (NANDDriver *nandp) { osalSysLockFromISR(); @@ -252,6 +252,7 @@ void nand_lld_init(void) { NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA; NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD; NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR; + NANDD1.bb_map = NULL; #endif /* STM32_NAND_USE_FSMC_NAND1 */ #if STM32_NAND_USE_FSMC_NAND2 @@ -265,6 +266,7 @@ void nand_lld_init(void) { NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA; NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD; NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR; + NANDD2.bb_map = NULL; #endif /* STM32_NAND_USE_FSMC_NAND2 */ } @@ -332,8 +334,8 @@ void nand_lld_stop(NANDDriver *nandp) { * * @notapi */ -void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ +void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen, + uint8_t *addr, size_t addrlen, uint32_t *ecc){ nandp->state = NAND_READ; nandp->rxdata = data; @@ -381,7 +383,7 @@ void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, * @notapi */ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { nandp->state = NAND_WRITE; @@ -425,7 +427,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, * * @notapi */ -uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen){ +uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { nandp->state = NAND_ERASE; @@ -451,7 +453,7 @@ uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen){ * * @notapi */ -void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len){ +void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len) { size_t i = 0; for (i=0; i<len; i++) @@ -467,7 +469,7 @@ void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len){ * * @notapi */ -void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len){ +void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { size_t i = 0; for (i=0; i<len; i++) @@ -482,7 +484,7 @@ void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len){ * * @notapi */ -void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd){ +void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { nandp->map_cmd[0] = cmd; } diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h index f136df4..1d2edef 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h @@ -26,6 +26,7 @@ #define _NAND_LLD_H_ #include "fsmc.h" +#include "bitmap.h" #if HAL_USE_NAND || defined(__DOXYGEN__) @@ -167,7 +168,7 @@ typedef struct { /** * @brief Pointer to lower level driver. */ - FSMCDriver *fsmcp; + //const FSMCDriver *fsmcp; /** * @brief Number of erase blocks in NAND device. */ @@ -184,13 +185,6 @@ typedef struct { * @brief Number of pages in block. */ uint32_t pages_per_block; -#if NAND_USE_BAD_MAP - /** - * @brief Pointer to bad block map. - * @details One bit per block. Memory for map must be allocated by user. - */ - uint32_t *bb_map; -#endif /* NAND_USE_BAD_MAP */ /** * @brief Number of write cycles for row addressing. */ @@ -287,6 +281,11 @@ struct NANDDriver { * @brief Memory mapping for addresses. */ uint8_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; }; /*===========================================================================*/ @@ -311,14 +310,14 @@ extern "C" { void nand_lld_init(void); void nand_lld_start(NANDDriver *nandp); void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); uint8_t nand_lld_read_status(NANDDriver *nandp); #ifdef __cplusplus } diff --git a/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c new file mode 100644 index 0000000..72c9d06 --- /dev/null +++ b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c @@ -0,0 +1,3792 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file stm32_ltdc.c
+ * @brief LCD-TFT Controller Driver.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#include "stm32_ltdc.h"
+
+#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__)
+
+/* TODO: Check preconditions (e.g., LTDC is ready).*/
+
+/* Ignore annoying warning messages for actually safe code.*/
+#if defined(__GNUC__) && !defined(__DOXYGEN__)
+#pragma GCC diagnostic ignored "-Wtype-limits"
+#endif
+
+/**
+ * @addtogroup ltdc
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if !defined(LTDC_LxBFCR_BF) && !defined(__DOXYGEN__)
+#define LTDC_LxBFCR_BF (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief LTDC1 driver identifier.
+ */
+LTDCDriver LTDCD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Bits per pixel lookup table.
+ */
+static const uint8_t ltdc_bpp[LTDC_MAX_PIXFMT_ID + 1] = {
+ 32, /* LTDC_FMT_ARGB8888 */
+ 24, /* LTDC_FMT_RGB888 */
+ 16, /* LTDC_FMT_RGB565 */
+ 16, /* LTDC_FMT_ARGB1555 */
+ 16, /* LTDC_FMT_ARGB4444 */
+ 8, /* LTDC_FMT_L8 */
+ 8, /* LTDC_FMT_AL44 */
+ 16 /* LTDC_FMT_AL88 */
+};
+
+/**
+ * @brief Invalid frame.
+ */
+static const ltdc_frame_t ltdc_invalid_frame = {
+ NULL,
+ 1,
+ 1,
+ 1,
+ LTDC_FMT_L8
+};
+
+/**
+ * @brief Invalid window.
+ * @details Pixel size, located at the origin of the screen.
+ */
+static const ltdc_window_t ltdc_invalid_window = {
+ 0,
+ 1,
+ 0,
+ 1
+};
+
+/**
+ * @brief Default layer specifications.
+ */
+static const ltdc_laycfg_t ltdc_default_laycfg = {
+ <dc_invalid_frame,
+ <dc_invalid_window,
+ LTDC_COLOR_BLACK,
+ 0x00,
+ LTDC_COLOR_BLACK,
+ NULL,
+ 0,
+ LTDC_BLEND_FIX1_FIX2,
+ 0
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Forces LTDC register reload.
+ * @details Blocking function.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @sclass
+ * @notapi
+ */
+static void ltdc_force_reload_s(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(ltdcp == <DCD1);
+
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+ while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR))
+ chSchDoYieldS();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @name LTDC interrupt handlers
+ * @{
+ */
+
+/**
+ * @brief LTDC event interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_LTDC_EV_HANDLER) {
+
+ LTDCDriver *const ltdcp = <DCD1;
+ thread_t *tp = NULL;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Handle Line Interrupt ISR.*/
+ if ((LTDC->ISR & LTDC_ISR_LIF) && (LTDC->IER & LTDC_IER_LIE)) {
+ osalDbgAssert(ltdcp->config->line_isr != NULL, "invalid state");
+ ltdcp->config->line_isr(ltdcp);
+ LTDC->ICR |= LTDC_ICR_CLIF;
+ }
+
+ /* Handle Register Reload ISR.*/
+ if ((LTDC->ISR & LTDC_ISR_RRIF) && (LTDC->IER & LTDC_IER_RRIE)) {
+ if (ltdcp->config->rr_isr != NULL)
+ ltdcp->config->rr_isr(ltdcp);
+
+ osalSysLockFromISR();
+ osalDbgAssert(ltdcp->state == LTDC_ACTIVE, "invalid state");
+#if (TRUE == LTDC_USE_WAIT)
+ /* Wake the waiting thread up.*/
+ if (ltdcp->thread != NULL) {
+ tp = ltdcp->thread;
+ ltdcp->thread = NULL;
+ tp->p_u.rdymsg = MSG_OK;
+ chSchReadyI(tp);
+ }
+#endif /* LTDC_USE_WAIT */
+ ltdcp->state = LTDC_READY;
+ osalSysUnlockFromISR();
+
+ LTDC->ICR |= LTDC_ICR_CRRIF;
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief LTDC error interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_LTDC_ER_HANDLER) {
+
+ static LTDCDriver *const ltdcp = <DCD1;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Handle FIFO Underrun ISR.*/
+ if ((LTDC->ISR & LTDC_ISR_FUIF) && (LTDC->IER & LTDC_IER_FUIE)) {
+ osalDbgAssert(ltdcp->config->fuerr_isr != NULL, "invalid state");
+ ltdcp->config->fuerr_isr(ltdcp);
+ LTDC->ICR |= LTDC_ICR_CFUIF;
+ }
+
+ /* Handle Transfer Error ISR.*/
+ if ((LTDC->ISR & LTDC_ISR_TERRIF) && (LTDC->IER & LTDC_IER_TERRIE)) {
+ osalDbgAssert(ltdcp->config->terr_isr != NULL, "invalid state");
+ ltdcp->config->terr_isr(ltdcp);
+ LTDC->ICR |= LTDC_ICR_CTERRIF;
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/** @} */
+
+/**
+ * @name LTDC driver-specific methods
+ * @{
+ */
+
+/**
+ * @brief LTDC Driver initialization.
+ * @details Initializes the LTDC subsystem and chosen drivers. Should be
+ * called at board initialization.
+ *
+ * @init
+ */
+void ltdcInit(void) {
+
+ /* Reset the LTDC hardware module.*/
+ rccResetLTDC();
+
+ /* Enable the LTDC clock.*/
+ RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */
+ rccEnableLTDC(false);
+
+ /* Driver struct initialization.*/
+ ltdcObjectInit(<DCD1);
+ LTDCD1.state = LTDC_STOP;
+}
+
+/**
+ * @brief Initializes the standard part of a @p LTDCDriver structure.
+ *
+ * @param[out] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @init
+ */
+void ltdcObjectInit(LTDCDriver *ltdcp) {
+
+ osalDbgCheck(ltdcp == <DCD1);
+
+ ltdcp->state = LTDC_UNINIT;
+ ltdcp->config = NULL;
+ ltdcp->active_window = ltdc_invalid_window;
+#if (TRUE == LTDC_USE_WAIT)
+ ltdcp->thread = NULL;
+#endif /* LTDC_USE_WAIT */
+#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxObjectInit(<dcp->lock);
+#else
+ chSemObjectInit(<dcp->lock, 1);
+#endif
+#endif /* LTDC_USE_MUTUAL_EXCLUSION */
+}
+
+/**
+ * @brief Get the driver state.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @retun driver state
+ *
+ * @iclass
+ */
+ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+
+ return ltdcp->state;
+}
+
+/**
+ * @brief Get the driver state.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @retun driver state
+ *
+ * @api
+ */
+ltdc_state_t ltdcGetState(LTDCDriver *ltdcp) {
+
+ ltdc_state_t state;
+ osalSysLock();
+ state = ltdcGetStateI(ltdcp);
+ osalSysUnlock();
+ return state;
+}
+
+/**
+ * @brief Configures and activates the LTDC peripheral.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] configp pointer to the @p LTDCConfig object
+ *
+ * @api
+ */
+void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp) {
+
+ uint32_t hacc, vacc, flags;
+
+ osalSysLock();
+
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(configp != NULL);
+ osalDbgAssert(ltdcp->state == LTDC_STOP, "invalid state");
+
+ ltdcp->config = configp;
+
+ /* Turn off the controller and its interrupts.*/
+ LTDC->GCR = 0;
+ LTDC->IER = 0;
+ ltdc_force_reload_s(ltdcp);
+
+ /* Set synchronization params.*/
+ osalDbgAssert(configp->hsync_width >= LTDC_MIN_HSYNC_WIDTH, "bounds");
+ osalDbgAssert(configp->hsync_width <= LTDC_MAX_HSYNC_WIDTH, "bounds");
+ osalDbgAssert(configp->vsync_height >= LTDC_MIN_VSYNC_HEIGHT, "bounds");
+ osalDbgAssert(configp->vsync_height <= LTDC_MAX_VSYNC_HEIGHT, "bounds");
+
+ hacc = configp->hsync_width - 1;
+ vacc = configp->vsync_height - 1;
+
+ LTDC->SSCR = (((hacc << 16) & LTDC_SSCR_HSW) |
+ ((vacc << 0) & LTDC_SSCR_VSH));
+
+ /* Set accumulated back porch params.*/
+ osalDbgAssert(configp->hbp_width >= LTDC_MIN_HBP_WIDTH, "bounds");
+ osalDbgAssert(configp->hbp_width <= LTDC_MAX_HBP_WIDTH, "bounds");
+ osalDbgAssert(configp->vbp_height >= LTDC_MIN_VBP_HEIGHT, "bounds");
+ osalDbgAssert(configp->vbp_height <= LTDC_MAX_VBP_HEIGHT, "bounds");
+
+ hacc += configp->hbp_width;
+ vacc += configp->vbp_height;
+
+ osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_HBP_WIDTH, "bounds");
+ osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_HBP_WIDTH, "bounds");
+ osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_VBP_HEIGHT, "bounds");
+ osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_VBP_HEIGHT, "bounds");
+
+ LTDC->BPCR = (((hacc << 16) & LTDC_BPCR_AHBP) |
+ ((vacc << 0) & LTDC_BPCR_AVBP));
+
+ ltdcp->active_window.hstart = hacc + 1;
+ ltdcp->active_window.vstart = vacc + 1;
+
+ /* Set accumulated active params.*/
+ osalDbgAssert(configp->screen_width >= LTDC_MIN_SCREEN_WIDTH, "bounds");
+ osalDbgAssert(configp->screen_width <= LTDC_MAX_SCREEN_WIDTH, "bounds");
+ osalDbgAssert(configp->screen_height >= LTDC_MIN_SCREEN_HEIGHT, "bounds");
+ osalDbgAssert(configp->screen_height <= LTDC_MAX_SCREEN_HEIGHT, "bounds");
+
+ hacc += configp->screen_width;
+ vacc += configp->screen_height;
+
+ osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_ACTIVE_WIDTH, "bounds");
+ osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_ACTIVE_WIDTH, "bounds");
+ osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_ACTIVE_HEIGHT, "bounds");
+ osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_ACTIVE_HEIGHT, "bounds");
+
+ LTDC->AWCR = (((hacc << 16) & LTDC_AWCR_AAW) |
+ ((vacc << 0) & LTDC_AWCR_AAH));
+
+ ltdcp->active_window.hstop = hacc;
+ ltdcp->active_window.vstop = vacc;
+
+ /* Set accumulated total params.*/
+ osalDbgAssert(configp->hfp_width >= LTDC_MIN_HFP_WIDTH, "bounds");
+ osalDbgAssert(configp->hfp_width <= LTDC_MAX_HFP_WIDTH, "bounds");
+ osalDbgAssert(configp->vfp_height >= LTDC_MIN_VFP_HEIGHT, "bounds");
+ osalDbgAssert(configp->vfp_height <= LTDC_MAX_VFP_HEIGHT, "bounds");
+
+ hacc += configp->hfp_width;
+ vacc += configp->vfp_height;
+
+ osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_TOTAL_WIDTH, "bounds");
+ osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_TOTAL_WIDTH, "bounds");
+ osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_TOTAL_HEIGHT, "bounds");
+ osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_TOTAL_HEIGHT, "bounds");
+
+ LTDC->TWCR = (((hacc << 16) & LTDC_TWCR_TOTALW) |
+ ((vacc << 0) & LTDC_TWCR_TOTALH));
+
+ /* Set signal polarities and other flags.*/
+ ltdcSetEnableFlagsI(ltdcp, configp->flags & ~LTDC_EF_ENABLE);
+
+ /* Color settings.*/
+ ltdcSetClearColorI(ltdcp, configp->clear_color);
+
+ /* Load layer configurations.*/
+ ltdcBgSetConfigI(ltdcp, configp->bg_laycfg);
+ ltdcFgSetConfigI(ltdcp, configp->fg_laycfg);
+
+ /* Enable only the assigned interrupt service routines.*/
+ nvicEnableVector(STM32_LTDC_EV_NUMBER, STM32_LTDC_EV_IRQ_PRIORITY);
+ nvicEnableVector(STM32_LTDC_ER_NUMBER, STM32_LTDC_ER_IRQ_PRIORITY);
+
+ flags = LTDC_IER_RRIE;
+ if (configp->line_isr != NULL)
+ flags |= LTDC_IER_LIE;
+ if (configp->fuerr_isr != NULL)
+ flags |= LTDC_IER_FUIE;
+ if (configp->terr_isr != NULL)
+ flags |= LTDC_IER_TERRIE;
+ LTDC->IER = flags;
+
+ /* Apply settings.*/
+ ltdc_force_reload_s(ltdcp);
+
+ /* Turn on the controller.*/
+ LTDC->GCR |= LTDC_GCR_LTDCEN;
+ ltdc_force_reload_s(ltdcp);
+
+ ltdcp->state = LTDC_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the LTDC peripheral.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcStop(LTDCDriver *ltdcp) {
+
+ osalDbgCheck(ltdcp == <DCD1);
+
+ osalSysLock();
+ osalDbgAssert(ltdcp->state == LTDC_READY, "invalid state");
+
+ /* Turn off the controller and its interrupts.*/
+ LTDC->GCR &= ~LTDC_GCR_LTDCEN;
+ LTDC->IER = 0;
+#if (TRUE == LTDC_USE_WAIT)
+ ltdcReloadS(ltdcp, true);
+#else
+ ltdcStartReloadI(ltdcp, true);
+ while (ltdcIsReloadingI(ltdcp))
+ chSchDoYieldS();
+#endif /* LTDC_USE_WAIT */
+
+ ltdcp->state = LTDC_STOP;
+ osalSysUnlock();
+}
+
+#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
+
+/**
+ * @brief Gains exclusive access to the LTDC module.
+ * @details This function tries to gain ownership to the LTDC module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @sclass
+ */
+void ltdcAcquireBusS(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(ltdcp == <DCD1);
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxLockS(<dcp->lock);
+#else
+ chSemWaitS(<dcp->lock);
+#endif
+}
+
+/**
+ * @brief Gains exclusive access to the LTDC module.
+ * @details This function tries to gain ownership to the LTDC module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcAcquireBus(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcAcquireBusS(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Releases exclusive access to the LTDC module.
+ * @pre In order to use this function the option
+ * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @sclass
+ */
+void ltdcReleaseBusS(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(ltdcp == <DCD1);
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxUnlockS(<dcp->lock);
+#else
+ chSemSignalI(<dcp->lock);
+#endif
+}
+
+/**
+ * @brief Releases exclusive access to the LTDC module.
+ * @pre In order to use this function the option
+ * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcReleaseBus(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcReleaseBusS(ltdcp);
+ osalSysUnlock();
+}
+
+#endif /* LTDC_USE_MUTUAL_EXCLUSION */
+
+/** @} */
+
+/**
+ * @name LTDC global methods
+ * @{
+ */
+
+/**
+ * @brief Get enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_EF_*</tt> group at once.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @iclass
+ */
+ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return LTDC->GCR & LTDC_EF_MASK;
+}
+
+/**
+ * @brief Get enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_EF_*</tt> group at once.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @api
+ */
+ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp) {
+
+ ltdc_flags_t flags;
+ osalSysLock();
+ flags = ltdcGetEnableFlagsI(ltdcp);
+ osalSysUnlock();
+ return flags;
+}
+
+/**
+ * @brief Set enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_EF_*</tt> group at once.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @iclass
+ */
+void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->GCR = flags & LTDC_EF_MASK;
+}
+
+/**
+ * @brief Set enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_EF_*</tt> group at once.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @api
+ */
+void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalSysLock();
+ ltdcSetEnableFlagsI(ltdcp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Reloading shadow registers.
+ * @details Tells whether the LTDC is reloading shadow registers.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return reloading
+ *
+ * @iclass
+ */
+bool ltdcIsReloadingI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) != 0;
+}
+
+/**
+ * @brief Reloading shadow registers.
+ * @details Tells whether the LTDC is reloading shadow registers.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return reloading
+ *
+ * @api
+ */
+bool ltdcIsReloading(LTDCDriver *ltdcp) {
+
+ bool reloading;
+ osalSysLock();
+ reloading = ltdcIsReloadingI(ltdcp);
+ osalSysUnlock();
+ return reloading;
+}
+
+/**
+ * @brief Reload shadow registers.
+ * @details Starts reloading LTDC shadow registers, upon vsync or immediately.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] immediately reload immediately, not upon vsync
+ *
+ * @iclass
+ */
+void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgAssert(ltdcp->state == LTDC_READY, "not ready");
+ (void)ltdcp;
+
+ ltdcp->state = LTDC_ACTIVE;
+ if (immediately)
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+ else
+ LTDC->SRCR |= LTDC_SRCR_VBR;
+}
+
+/**
+ * @brief Reload shadow registers.
+ * @details Starts reloading LTDC shadow registers, upon vsync or immediately.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] immediately reload immediately, not upon vsync
+ *
+ * @api
+ */
+void ltdcStartReload(LTDCDriver *ltdcp, bool immediately) {
+
+ osalSysLock();
+ ltdcStartReloadI(ltdcp, immediately);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Reload shadow registers.
+ * @details Reloads LTDC shadow registers, upon vsync or immediately.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] immediately reload immediately, not upon vsync
+ *
+ * @sclass
+ */
+void ltdcReloadS(LTDCDriver *ltdcp, bool immediately) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(ltdcp == <DCD1);
+
+ ltdcStartReloadI(ltdcp, immediately);
+
+#if (TRUE == LTDC_USE_WAIT)
+ osalDbgAssert(ltdcp->thread == NULL, "already waiting");
+
+ if (immediately) {
+ while (LTDC->SRCR & LTDC_SRCR_IMR)
+ chSchDoYieldS();
+ ltdcp->state = LTDC_READY;
+ } else {
+ ltdcp->thread = chThdGetSelfX();
+ chSchGoSleepS(CH_STATE_SUSPENDED);
+ }
+#else
+ while (LTDC->SRCR & LTDC_SRCR_IMR)
+ chSchDoYieldS();
+ ltdcp->state = LTDC_READY;
+#endif
+}
+
+/**
+ * @brief Reload shadow registers.
+ * @details Reloads LTDC shadow registers, upon vsync or immediately.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] immediately reload immediately, not upon vsync
+ *
+ * @api
+ */
+void ltdcReload(LTDCDriver *ltdcp, bool immediately) {
+
+ osalSysLock();
+ ltdcReloadS(ltdcp, immediately);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Dithering enabled.
+ * @details Tells whether the dithering is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC->GCR & LTDC_GCR_DTEN) != 0;
+}
+
+/**
+ * @brief Dithering enabled.
+ * @details Tells whether the dithering is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcIsDitheringEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable dithering.
+ * @details Enables dithering capabilities for pixel formats with less than
+ * 8 bits per channel.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcEnableDitheringI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->GCR |= LTDC_GCR_DTEN;
+}
+
+/**
+ * @brief Enable dithering.
+ * @details Enables dithering capabilities for pixel formats with less than
+ * 8 bits per channel.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcEnableDithering(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcEnableDitheringI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable dithering.
+ * @details Disables dithering capabilities for pixel formats with less than
+ * 8 bits per channel.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcDisableDitheringI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->GCR &= ~LTDC_GCR_DTEN;
+}
+
+/**
+ * @brief Disable dithering.
+ * @details Disables dithering capabilities for pixel formats with less than
+ * 8 bits per channel.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcDisableDithering(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcDisableDitheringI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get clear screen color.
+ * @details Gets the clear screen (actual background) color.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return clear screen color, RGB-888
+ *
+ * @iclass
+ */
+ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_color_t)(LTDC->BCCR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get clear screen color.
+ * @details Gets the clear screen (actual background) color.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return clear screen color, RGB-888
+ *
+ * @api
+ */
+ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp) {
+
+ ltdc_color_t color;
+ osalSysLock();
+ color = ltdcGetClearColorI(ltdcp);
+ osalSysUnlock();
+ return color;
+}
+
+/**
+ * @brief Set clear screen color.
+ * @details Sets the clear screen (actual background) color.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c clear screen color, RGB-888
+ *
+ * @iclass
+ */
+void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (c & 0x00FFFFFF);
+}
+
+/**
+ * @brief Set clear screen color.
+ * @details Sets the clear screen (actual background) color.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c clear screen color, RGB-888
+ *
+ * @api
+ */
+void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcSetClearColorI(ltdcp, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get line interrupt position.
+ * @details Gets the line interrupt position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return line interrupt position
+ *
+ * @iclass
+ */
+uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (uint16_t)(LTDC->LIPCR & LTDC_LIPCR_LIPOS);
+}
+
+/**
+ * @brief Get line interrupt position.
+ * @details Gets the line interrupt position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return line interrupt position
+ *
+ * @api
+ */
+uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp) {
+
+ uint16_t line;
+ osalSysLock();
+ line = ltdcGetLineInterruptPosI(ltdcp);
+ osalSysUnlock();
+ return line;
+}
+
+/**
+ * @brief Set line interrupt position.
+ * @details Sets the line interrupt position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->LIPCR = ((LTDC->LIPCR & ~LTDC_LIPCR_LIPOS) |
+ ((uint32_t)line & LTDC_LIPCR_LIPOS));
+}
+
+/**
+ * @brief Set line interrupt position.
+ * @details Sets the line interrupt position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line) {
+
+ osalSysLock();
+ ltdcSetLineInterruptPosI(ltdcp, line);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Line interrupt enabled.
+ * @details Tells whether the line interrupt is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC->IER & LTDC_IER_LIE) != 0;
+}
+
+/**
+ * @brief Line interrupt enabled.
+ * @details Tells whether the line interrupt is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcIsLineInterruptEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable line interrupt.
+ * @details Enables line interrupt.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcEnableLineInterruptI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->IER |= LTDC_IER_LIE;
+}
+
+/**
+ * @brief Enable line interrupt.
+ * @details Enables line interrupt.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcEnableLineInterrupt(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcEnableLineInterruptI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable line interrupt.
+ * @details Disables line interrupt.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcDisableLineInterruptI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC->IER &= ~LTDC_IER_LIE;
+}
+
+/**
+ * @brief Disable line interrupt.
+ * @details Disables line interrupt.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcDisableLineInterrupt(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcDisableLineInterruptI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get current position.
+ * @details Gets the current position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] xp pointer to the destination horizontal coordinate
+ * @param[out] yp pointer to the destination vertical coordinate
+ *
+ * @iclass
+ */
+void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) {
+
+ const uint32_t r = LTDC->CPSR;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ *xp = (uint16_t)((r & LTDC_CPSR_CXPOS) >> 16);
+ *yp = (uint16_t)((r & LTDC_CPSR_CYPOS) >> 0);
+}
+
+/**
+ * @brief Get current position.
+ * @details Gets the current position.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] xp pointer to the destination horizontal coordinate
+ * @param[out] yp pointer to the destination vertical coordinate
+ *
+ * @api
+ */
+void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) {
+
+ osalSysLock();
+ ltdcGetCurrentPosI(ltdcp, xp, yp);
+ osalSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name LTDC background layer (layer 1) methods
+ * @{
+ */
+
+/**
+ * @brief Get background layer enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @iclass
+ */
+ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return LTDC_Layer1->CR & LTDC_LEF_MASK;
+}
+
+/**
+ * @brief Get background layer enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @api
+ */
+ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp) {
+
+ ltdc_flags_t flags;
+ osalSysLock();
+ flags = ltdcBgGetEnableFlagsI(ltdcp);
+ osalSysUnlock();
+ return flags;
+}
+
+/**
+ * @brief Set background layer enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @iclass
+ */
+void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR = ((LTDC_Layer1->CR & ~LTDC_LEF_MASK) |
+ ((uint32_t)flags & LTDC_LEF_MASK));
+}
+
+/**
+ * @brief Set background layer enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @api
+ */
+void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalSysLock();
+ ltdcBgSetEnableFlagsI(ltdcp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Background layer enabled.
+ * @details Tells whether the background layer (layer 1) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcBgIsEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer1->CR & ~LTDC_LxCR_LEN) != 0;
+}
+
+/**
+ * @brief Background layer enabled.
+ * @details Tells whether the background layer (layer 1) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcBgIsEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcBgIsEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Background layer enable.
+ * @details Enables the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgEnableI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR |= LTDC_LxCR_LEN;
+}
+
+/**
+ * @brief Background layer enable.
+ * @details Enables the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgEnable(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgEnableI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Background layer disable.
+ * @details Disables the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgDisableI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR &= ~LTDC_LxCR_LEN;
+}
+
+/**
+ * @brief Background layer disable.
+ * @details Disables the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgDisable(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgDisableI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Background layer palette enabled.
+ * @details Tells whether the background layer (layer 1) palette (color lookup
+ * table) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer1->CR & ~LTDC_LxCR_CLUTEN) != 0;
+}
+
+/**
+ * @brief Background layer palette enabled.
+ * @details Tells whether the background layer (layer 1) palette (color lookup
+ * table) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcBgIsPaletteEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable background layer palette.
+ * @details Enables the palette (color lookup table) of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgEnablePaletteI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR |= LTDC_LxCR_CLUTEN;
+}
+
+/**
+ * @brief Enable background layer palette.
+ * @details Enables the palette (color lookup table) of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgEnablePalette(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgEnablePaletteI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable background layer palette.
+ * @details Disables the palette (color lookup table) of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgDisablePaletteI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR &= ~LTDC_LxCR_CLUTEN;
+}
+
+/**
+ * @brief Disable background layer palette.
+ * @details Disables the palette (color lookup table) of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgDisablePalette(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgDisablePaletteI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer palette color.
+ * @details Sets the color of a palette (color lookup table) slot to the
+ * background layer (layer 1).
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] slot palette slot
+ * @param[in] c color, RGB-888
+ *
+ * @iclass
+ */
+void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state");
+ (void)ltdcp;
+
+ LTDC_Layer1->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set background layer palette color.
+ * @details Sets the color of a palette (color lookup table) slot to the
+ * background layer (layer 1).
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] slot palette slot
+ * @param[in] c color, RGB-888
+ *
+ * @api
+ */
+void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcBgSetPaletteColorI(ltdcp, slot, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer palette.
+ * @details Sets the entire palette color (color lookup table) slot.
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] colors array of palette colors, RGB-888
+ * @param[in] length number of palette colors
+ *
+ * @iclass
+ */
+void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length) {
+
+ uint16_t i;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck((colors == NULL) == (length == 0));
+ osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds");
+ osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state");
+ (void)ltdcp;
+
+ for (i = 0; i < length; ++i)
+ LTDC_Layer1->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set background layer palette.
+ * @details Sets the entire palette color (color lookup table) slot.
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] colors array of palette colors, RGB-888
+ * @param[in] length number of palette colors
+ *
+ * @api
+ */
+void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length) {
+
+ osalSysLock();
+ ltdcBgSetPaletteI(ltdcp, colors, length);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer pixel format.
+ * @details Gets the pixel format of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return pixel format
+ *
+ * @iclass
+ */
+ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_pixfmt_t)(LTDC_Layer1->PFCR & LTDC_LxPFCR_PF);
+}
+
+/**
+ * @brief Get background layer pixel format.
+ * @details Gets the pixel format of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return pixel format
+ *
+ * @api
+ */
+ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp) {
+
+ ltdc_pixfmt_t fmt;
+ osalSysLock();
+ fmt = ltdcBgGetPixelFormatI(ltdcp);
+ osalSysUnlock();
+ return fmt;
+}
+
+/**
+ * @brief Set background layer pixel format.
+ * @details Sets the pixel format of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] fmt pixel format
+ *
+ * @iclass
+ */
+void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds");
+ osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds");
+ (void)ltdcp;
+
+ LTDC_Layer1->PFCR = ((LTDC_Layer1->PFCR & ~LTDC_LxPFCR_PF) |
+ ((uint32_t)fmt & LTDC_LxPFCR_PF));
+}
+
+/**
+ * @brief Set background layer pixel format.
+ * @details Sets the pixel format of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] fmt pixel format
+ *
+ * @api
+ */
+void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) {
+
+ osalSysLock();
+ ltdcBgSetPixelFormatI(ltdcp, fmt);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Background layer color keying enabled.
+ * @details Tells whether the background layer (layer 1) has color keying
+ * enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer1->CR & ~LTDC_LxCR_COLKEN) != 0;
+}
+
+/**
+ * @brief Background layer color keying enabled.
+ * @details Tells whether the background layer (layer 1) has color keying
+ * enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcBgIsKeyingEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable background layer color keying.
+ * @details Enables color keying capabilities of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgEnableKeyingI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR |= LTDC_LxCR_COLKEN;
+}
+
+/**
+ * @brief Enable background layer color keying.
+ * @details Enables color keying capabilities of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgEnableKeying(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgEnableKeyingI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable background layer color keying.
+ * @details Disables color keying capabilities of the background layer (layer
+ * 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgDisableKeyingI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CR &= ~LTDC_LxCR_COLKEN;
+}
+
+/**
+ * @brief Disable background layer color keying.
+ * @details Disables color keying capabilities of the background layer (layer
+ * 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgDisableKeying(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgDisableKeyingI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer color key.
+ * @details Gets the color key of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return color key, RGB-888
+ *
+ * @iclass
+ */
+ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_color_t)(LTDC_Layer1->CKCR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get background layer color key.
+ * @details Gets the color key of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return color key, RGB-888
+ *
+ * @api
+ */
+ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp) {
+
+ ltdc_color_t color;
+ osalSysLock();
+ color = ltdcBgGetKeyingColorI(ltdcp);
+ osalSysUnlock();
+ return color;
+}
+
+/**
+ * @brief Set background layer color key.
+ * @details Sets the color key of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c color key, RGB-888
+ *
+ * @iclass
+ */
+void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CKCR = ((LTDC_Layer1->CKCR & ~0x00FFFFFF) |
+ ((uint32_t)c & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set background layer color key.
+ * @details Sets the color key of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c color key, RGB-888
+ *
+ * @api
+ */
+void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcBgSetKeyingColorI(ltdcp, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer constant alpha.
+ * @details Gets the constant alpha component of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @iclass
+ */
+uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (uint8_t)(LTDC_Layer1->CACR & LTDC_LxCACR_CONSTA);
+}
+
+/**
+ * @brief Get background layer constant alpha.
+ * @details Gets the constant alpha component of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @api
+ */
+uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp) {
+
+ uint8_t a;
+ osalSysLock();
+ a = ltdcBgGetConstantAlphaI(ltdcp);
+ osalSysUnlock();
+ return a;
+}
+
+/**
+ * @brief Set background layer constant alpha.
+ * @details Sets the constant alpha component of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @iclass
+ */
+void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CACR = ((LTDC_Layer1->CACR & ~LTDC_LxCACR_CONSTA) |
+ ((uint32_t)a & LTDC_LxCACR_CONSTA));
+}
+
+/**
+ * @brief Set background layer constant alpha.
+ * @details Sets the constant alpha component of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @api
+ */
+void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) {
+
+ osalSysLock();
+ ltdcBgSetConstantAlphaI(ltdcp, a);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer default color.
+ * @details Gets the default color of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @iclass
+ */
+ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_color_t)LTDC_Layer1->DCCR;
+}
+
+/**
+ * @brief Get background layer default color.
+ * @details Gets the default color of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @api
+ */
+ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp) {
+
+ ltdc_color_t color;
+ osalSysLock();
+ color = ltdcBgGetDefaultColorI(ltdcp);
+ osalSysUnlock();
+ return color;
+}
+
+/**
+ * @brief Set background layer default color.
+ * @details Sets the default color of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @iclass
+ */
+void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->DCCR = (uint32_t)c;
+}
+
+/**
+ * @brief Set background layer default color.
+ * @details Sets the default color of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @api
+ */
+void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcBgSetDefaultColorI(ltdcp, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer blending factors.
+ * @details Gets the blending factors of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return blending factors
+ *
+ * @iclass
+ */
+ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_blendf_t)(LTDC_Layer1->BFCR & LTDC_LxBFCR_BF);
+}
+
+/**
+ * @brief Get background layer blending factors.
+ * @details Gets the blending factors of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return blending factors
+ *
+ * @api
+ */
+ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp) {
+
+ ltdc_blendf_t bf;
+ osalSysLock();
+ bf = ltdcBgGetBlendingFactorsI(ltdcp);
+ osalSysUnlock();
+ return bf;
+}
+
+/**
+ * @brief Set background layer blending factors.
+ * @details Sets the blending factors of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] factors blending factors
+ *
+ * @iclass
+ */
+void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->BFCR = ((LTDC_Layer1->BFCR & ~LTDC_LxBFCR_BF) |
+ ((uint32_t)bf & LTDC_LxBFCR_BF));
+}
+
+/**
+ * @brief Set background layer blending factors.
+ * @details Sets the blending factors of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] factors blending factors
+ *
+ * @api
+ */
+void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) {
+
+ osalSysLock();
+ ltdcBgSetBlendingFactorsI(ltdcp, bf);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer window specs.
+ * @details Gets the window specifications of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] windowp pointer to the window specifications
+ *
+ * @iclass
+ */
+void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(windowp != NULL);
+ (void)ltdcp;
+
+ windowp->hstart =
+ (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0);
+ windowp->hstop =
+ (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16);
+ windowp->vstart =
+ (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0);
+ windowp->vstop =
+ (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16);
+}
+
+/**
+ * @brief Get background layer window specs.
+ * @details Gets the window specifications of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] windowp pointer to the window specifications
+ *
+ * @api
+ */
+void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) {
+
+ osalSysLock();
+ ltdcBgGetWindowI(ltdcp, windowp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer window specs.
+ * @details Sets the window specifications of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] windowp pointer to the window specifications
+ *
+ * @iclass
+ */
+void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) {
+
+ uint32_t start, stop;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(windowp != NULL);
+ (void)ltdcp;
+
+ osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds");
+ osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds");
+
+ /* Horizontal boundaries.*/
+ start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart;
+ stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart;
+
+ osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds");
+ osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds");
+
+ LTDC_Layer1->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) |
+ ((stop << 16) & LTDC_LxWHPCR_WHSPPOS));
+
+ /* Vertical boundaries.*/
+ start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart;
+ stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart;
+
+ osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds");
+ osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds");
+
+ LTDC_Layer1->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) |
+ ((stop << 16) & LTDC_LxWVPCR_WVSPPOS));
+}
+
+/**
+ * @brief Set background layer window specs.
+ * @details Sets the window specifications of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] windowp pointer to the window specifications
+ *
+ * @api
+ */
+void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) {
+
+ osalSysLock();
+ ltdcBgSetWindowI(ltdcp, windowp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer window as invalid.
+ * @details Sets the window specifications of the background layer (layer 1)
+ * so that the window is pixel sized at the screen origin.
+ * @note Useful before reconfiguring the frame specifications of the layer,
+ * to avoid errors.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp) {
+
+ ltdcBgSetWindowI(ltdcp, <dc_invalid_window);
+}
+
+/**
+ * @brief Set background layer window as invalid.
+ * @details Sets the window specifications of the background layer (layer 1)
+ * so that the window is pixel sized at the screen origin.
+ * @note Useful before reconfiguring the frame specifications of the layer,
+ * to avoid errors.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcBgSetWindowI(ltdcp, <dc_invalid_window);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer frame buffer specs.
+ * @details Gets the frame buffer specifications of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] framep pointer to the frame buffer specifications
+ *
+ * @iclass
+ */
+void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(framep != NULL);
+
+ framep->bufferp = (void *)(LTDC_Layer1->CFBAR & LTDC_LxCFBAR_CFBADD);
+ framep->pitch = (size_t)((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBP) >> 16);
+ framep->width = (uint16_t)(((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) /
+ ltdcBytesPerPixel(ltdcBgGetPixelFormatI(ltdcp)));
+ framep->height = (uint16_t)(LTDC_Layer1->CFBLNR & LTDC_LxCFBLNR_CFBLNBR);
+}
+
+/**
+ * @brief Get background layer frame buffer specs.
+ * @details Gets the frame buffer specifications of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] framep pointer to the frame buffer specifications
+ *
+ * @api
+ */
+void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) {
+
+ osalSysLock();
+ ltdcBgGetFrameI(ltdcp, framep);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer frame buffer specs.
+ * @details Sets the frame buffer specifications of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] framep pointer to the frame buffer specifications
+ *
+ * @iclass
+ */
+void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) {
+
+ size_t linesize;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(framep != NULL);
+
+ ltdcBgSetPixelFormatI(ltdcp, framep->fmt);
+
+ linesize = ltdcBytesPerPixel(framep->fmt) * framep->width;
+
+ osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds");
+ osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds");
+ osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds");
+ osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds");
+ osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds");
+ osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds");
+ osalDbgAssert(framep->pitch >= linesize, "bounds");
+
+ LTDC_Layer1->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD;
+ LTDC_Layer1->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) |
+ ((linesize + 3) & LTDC_LxCFBLR_CFBLL));
+ LTDC_Layer1->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR;
+}
+
+/**
+ * @brief Set background layer frame buffer specs.
+ * @details Sets the frame buffer specifications of the background layer
+ * (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] framep pointer to the frame buffer specifications
+ *
+ * @api
+ */
+void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) {
+
+ osalSysLock();
+ ltdcBgSetFrameI(ltdcp, framep);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer frame buffer address.
+ * @details Gets the frame buffer address of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return frame buffer address
+ *
+ * @iclass
+ */
+void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (void *)LTDC_Layer1->CFBAR;
+}
+
+/**
+ * @brief Get background layer frame buffer address.
+ * @details Gets the frame buffer address of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return frame buffer address
+ *
+ * @api
+ */
+void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp) {
+
+ void *bufferp;
+ osalSysLock();
+ bufferp = ltdcBgGetFrameAddressI(ltdcp);
+ osalSysUnlock();
+ return bufferp;
+}
+
+/**
+ * @brief Set background layer frame buffer address.
+ * @details Sets the frame buffer address of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] bufferp frame buffer address
+ *
+ * @iclass
+ */
+void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer1->CFBAR = (uint32_t)bufferp;
+}
+
+/**
+ * @brief Set background layer frame buffer address.
+ * @details Sets the frame buffer address of the background layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] bufferp frame buffer address
+ *
+ * @api
+ */
+void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) {
+
+ osalSysLock();
+ ltdcBgSetFrameAddressI(ltdcp, bufferp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get background layer specifications.
+ * @details Gets the background layer (layer 1) specifications at once.
+ * @note If palette specifications cannot be retrieved, they are set to
+ * @p NULL. This is not an error.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(cfgp != NULL);
+
+ ltdcBgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame);
+ ltdcBgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window);
+ cfgp->def_color = ltdcBgGetDefaultColorI(ltdcp);
+ cfgp->key_color = ltdcBgGetKeyingColorI(ltdcp);
+ cfgp->const_alpha = ltdcBgGetConstantAlphaI(ltdcp);
+ cfgp->blending = ltdcBgGetBlendingFactorsI(ltdcp);
+
+ cfgp->pal_colors = NULL;
+ cfgp->pal_length = 0;
+
+ cfgp->flags = ltdcBgGetEnableFlagsI(ltdcp);
+}
+
+/**
+ * @brief Get background layer specifications.
+ * @details Gets the background layer (layer 1) specifications at once.
+ * @note If palette specifications cannot be retrieved, they are set to
+ * @p NULL. This is not an error.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) {
+
+ osalSysLock();
+ ltdcBgGetLayerI(ltdcp, cfgp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set background layer specifications.
+ * @details Sets the background layer (layer 1) specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+
+ if (cfgp == NULL)
+ cfgp = <dc_default_laycfg;
+
+ osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0));
+
+ ltdcBgSetFrameI(ltdcp, cfgp->frame);
+ ltdcBgSetWindowI(ltdcp, cfgp->window);
+ ltdcBgSetDefaultColorI(ltdcp, cfgp->def_color);
+ ltdcBgSetKeyingColorI(ltdcp, cfgp->key_color);
+ ltdcBgSetConstantAlphaI(ltdcp, cfgp->const_alpha);
+ ltdcBgSetBlendingFactorsI(ltdcp, cfgp->blending);
+
+ if (cfgp->pal_length > 0)
+ ltdcBgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length);
+
+ ltdcBgSetEnableFlagsI(ltdcp, cfgp->flags);
+}
+
+/**
+ * @brief Set background layer specifications.
+ * @details Sets the background layer (layer 1) specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) {
+
+ osalSysLock();
+ ltdcBgSetConfigI(ltdcp, cfgp);
+ osalSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name LTDC foreground layer (layer 2) methods
+ * @{
+ */
+
+/**
+ * @brief Get foreground layer enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @iclass
+ */
+ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return LTDC_Layer2->CR & LTDC_LEF_MASK;
+}
+
+/**
+ * @brief Get foreground layer enabled flags.
+ * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled flags
+ *
+ * @api
+ */
+ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp) {
+
+ ltdc_flags_t flags;
+ osalSysLock();
+ flags = ltdcFgGetEnableFlagsI(ltdcp);
+ osalSysUnlock();
+ return flags;
+}
+
+/**
+ * @brief Set foreground layer enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @iclass
+ */
+void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR = ((LTDC_Layer2->CR & ~LTDC_LEF_MASK) |
+ ((uint32_t)flags & LTDC_LEF_MASK));
+}
+
+/**
+ * @brief Set foreground layer enabled flags.
+ * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once.
+ * Targeting the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] flags enabled flags
+ *
+ * @api
+ */
+void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) {
+
+ osalSysLock();
+ ltdcFgSetEnableFlagsI(ltdcp, flags);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Foreground layer enabled.
+ * @details Tells whether the foreground layer (layer 2) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcFgIsEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer2->CR & ~LTDC_LxCR_LEN) != 0;
+}
+
+/**
+ * @brief Foreground layer enabled.
+ * @details Tells whether the foreground layer (layer 2) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcFgIsEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcFgIsEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Foreground layer enable.
+ * @details Enables the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgEnableI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR |= LTDC_LxCR_LEN;
+}
+
+/**
+ * @brief Foreground layer enable.
+ * @details Enables the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgEnable(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgEnableI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Foreground layer disable.
+ * @details Disables the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgDisableI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR &= ~LTDC_LxCR_LEN;
+}
+
+/**
+ * @brief Foreground layer disable.
+ * @details Disables the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgDisable(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgDisableI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Foreground layer palette enabled.
+ * @details Tells whether the foreground layer (layer 2) palette (color lookup
+ * table) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer2->CR & ~LTDC_LxCR_CLUTEN) != 0;
+}
+
+/**
+ * @brief Foreground layer palette enabled.
+ * @details Tells whether the foreground layer (layer 2) palette (color lookup
+ * table) is enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcFgIsPaletteEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable foreground layer palette.
+ * @details Enables the palette (color lookup table) of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgEnablePaletteI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR |= LTDC_LxCR_CLUTEN;
+}
+
+/**
+ * @brief Enable foreground layer palette.
+ * @details Enables the palette (color lookup table) of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgEnablePalette(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgEnablePaletteI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable foreground layer palette.
+ * @details Disables the palette (color lookup table) of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgDisablePaletteI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR &= ~LTDC_LxCR_CLUTEN;
+}
+
+/**
+ * @brief Disable foreground layer palette.
+ * @details Disables the palette (color lookup table) of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgDisablePalette(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgDisablePaletteI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer palette color.
+ * @details Sets the color of a palette (color lookup table) slot to the
+ * foreground layer (layer 2).
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] slot palette slot
+ * @param[in] c color, RGB-888
+ *
+ * @iclass
+ */
+void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state");
+ (void)ltdcp;
+
+ LTDC_Layer2->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set foreground layer palette color.
+ * @details Sets the color of a palette (color lookup table) slot to the
+ * foreground layer (layer 2).
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] slot palette slot
+ * @param[in] c color, RGB-888
+ *
+ * @api
+ */
+void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcFgSetPaletteColorI(ltdcp, slot, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer palette.
+ * @details Sets the entire palette color (color lookup table) slot.
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] colors array of palette colors, RGB-888
+ * @param[in] length number of palette colors
+ *
+ * @iclass
+ */
+void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length) {
+
+ uint16_t i;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck((colors == NULL) == (length == 0));
+ osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds");
+ osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state");
+ (void)ltdcp;
+
+ for (i = 0; i < length; ++i)
+ LTDC_Layer2->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set foreground layer palette.
+ * @details Sets the entire palette color (color lookup table) slot.
+ * @pre The layer must be disabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] colors array of palette colors, RGB-888
+ * @param[in] length number of palette colors
+ *
+ * @api
+ */
+void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length) {
+
+ osalSysLock();
+ ltdcFgSetPaletteI(ltdcp, colors, length);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer pixel format.
+ * @details Gets the pixel format of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return pixel format
+ *
+ * @iclass
+ */
+ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_pixfmt_t)(LTDC_Layer2->PFCR & LTDC_LxPFCR_PF);
+}
+
+/**
+ * @brief Get foreground layer pixel format.
+ * @details Gets the pixel format of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return pixel format
+ *
+ * @api
+ */
+ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp) {
+
+ ltdc_pixfmt_t fmt;
+ osalSysLock();
+ fmt = ltdcFgGetPixelFormatI(ltdcp);
+ osalSysUnlock();
+ return fmt;
+}
+
+/**
+ * @brief Set foreground layer pixel format.
+ * @details Sets the pixel format of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] fmt pixel format
+ *
+ * @iclass
+ */
+void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds");
+ osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds");
+ (void)ltdcp;
+
+ LTDC_Layer2->PFCR = ((LTDC_Layer2->PFCR & ~LTDC_LxPFCR_PF) |
+ ((uint32_t)fmt & LTDC_LxPFCR_PF));
+}
+
+/**
+ * @brief Set foreground layer pixel format.
+ * @details Sets the pixel format of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] fmt pixel format
+ *
+ * @api
+ */
+void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) {
+
+ osalSysLock();
+ ltdcFgSetPixelFormatI(ltdcp, fmt);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Foreground layer color keying enabled.
+ * @details Tells whether the foreground layer (layer 2) has color keying
+ * enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @iclass
+ */
+bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (LTDC_Layer2->CR & ~LTDC_LxCR_COLKEN) != 0;
+}
+
+/**
+ * @brief Foreground layer color keying enabled.
+ * @details Tells whether the foreground layer (layer 2) has color keying
+ * enabled.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return enabled
+ *
+ * @api
+ */
+bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp) {
+
+ bool enabled;
+ osalSysLock();
+ enabled = ltdcFgIsKeyingEnabledI(ltdcp);
+ osalSysUnlock();
+ return enabled;
+}
+
+/**
+ * @brief Enable foreground layer color keying.
+ * @details Enables color keying capabilities of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgEnableKeyingI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR |= LTDC_LxCR_COLKEN;
+}
+
+/**
+ * @brief Enable foreground layer color keying.
+ * @details Enables color keying capabilities of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgEnableKeying(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgEnableKeyingI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disable foreground layer color keying.
+ * @details Disables color keying capabilities of the foreground layer (layer
+ * 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgDisableKeyingI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CR &= ~LTDC_LxCR_COLKEN;
+}
+
+/**
+ * @brief Disable foreground layer color keying.
+ * @details Disables color keying capabilities of the foreground layer (layer
+ * 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgDisableKeying(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgDisableKeyingI(ltdcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer color key.
+ * @details Gets the color key of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return color key, RGB-888
+ *
+ * @iclass
+ */
+ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_color_t)(LTDC_Layer2->CKCR & 0x00FFFFFF);
+}
+
+/**
+ * @brief Get foreground layer color key.
+ * @details Gets the color key of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return color key, RGB-888
+ *
+ * @api
+ */
+ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp) {
+
+ ltdc_color_t color;
+ osalSysLock();
+ color = ltdcFgGetKeyingColorI(ltdcp);
+ osalSysUnlock();
+ return color;
+}
+
+/**
+ * @brief Set foreground layer color key.
+ * @details Sets the color key of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c color key, RGB-888
+ *
+ * @iclass
+ */
+void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CKCR = ((LTDC_Layer2->CKCR & ~0x00FFFFFF) |
+ ((uint32_t)c & 0x00FFFFFF));
+}
+
+/**
+ * @brief Set foreground layer color key.
+ * @details Sets the color key of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c color key, RGB-888
+ *
+ * @api
+ */
+void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcFgSetKeyingColorI(ltdcp, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer constant alpha.
+ * @details Gets the constant alpha component of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @iclass
+ */
+uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (uint8_t)(LTDC_Layer2->CACR & LTDC_LxCACR_CONSTA);
+}
+
+/**
+ * @brief Get foreground layer constant alpha.
+ * @details Gets the constant alpha component of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return constant alpha component, A-8
+ *
+ * @api
+ */
+uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp) {
+
+ uint8_t a;
+ osalSysLock();
+ a = ltdcFgGetConstantAlphaI(ltdcp);
+ osalSysUnlock();
+ return a;
+}
+
+/**
+ * @brief Set foreground layer constant alpha.
+ * @details Sets the constant alpha component of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @iclass
+ */
+void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CACR = ((LTDC_Layer2->CACR & ~LTDC_LxCACR_CONSTA) |
+ ((uint32_t)a & LTDC_LxCACR_CONSTA));
+}
+
+/**
+ * @brief Set foreground layer constant alpha.
+ * @details Sets the constant alpha component of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] a constant alpha component, A-8
+ *
+ * @api
+ */
+void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) {
+
+ osalSysLock();
+ ltdcFgSetConstantAlphaI(ltdcp, a);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer default color.
+ * @details Gets the default color of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @iclass
+ */
+ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_color_t)LTDC_Layer2->DCCR;
+}
+
+/**
+ * @brief Get foreground layer default color.
+ * @details Gets the default color of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return default color, RGB-888
+ *
+ * @api
+ */
+ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp) {
+
+ ltdc_color_t color;
+ osalSysLock();
+ color = ltdcFgGetDefaultColorI(ltdcp);
+ osalSysUnlock();
+ return color;
+}
+
+/**
+ * @brief Set foreground layer default color.
+ * @details Sets the default color of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @iclass
+ */
+void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->DCCR = (uint32_t)c;
+}
+
+/**
+ * @brief Set foreground layer default color.
+ * @details Sets the default color of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] c default color, RGB-888
+ *
+ * @api
+ */
+void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) {
+
+ osalSysLock();
+ ltdcFgSetDefaultColorI(ltdcp, c);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer blending factors.
+ * @details Gets the blending factors of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return blending factors
+ *
+ * @iclass
+ */
+ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (ltdc_blendf_t)(LTDC_Layer2->BFCR & LTDC_LxBFCR_BF);
+}
+
+/**
+ * @brief Get foreground layer blending factors.
+ * @details Gets the blending factors of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return blending factors
+ *
+ * @api
+ */
+ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp) {
+
+ ltdc_blendf_t bf;
+ osalSysLock();
+ bf = ltdcFgGetBlendingFactorsI(ltdcp);
+ osalSysUnlock();
+ return bf;
+}
+
+/**
+ * @brief Set foreground layer blending factors.
+ * @details Sets the blending factors of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] factors blending factors
+ *
+ * @iclass
+ */
+void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->BFCR = ((LTDC_Layer2->BFCR & ~LTDC_LxBFCR_BF) |
+ ((uint32_t)bf & LTDC_LxBFCR_BF));
+}
+
+/**
+ * @brief Set foreground layer blending factors.
+ * @details Sets the blending factors of the foreground layer (layer 1).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] factors blending factors
+ *
+ * @api
+ */
+void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) {
+
+ osalSysLock();
+ ltdcFgSetBlendingFactorsI(ltdcp, bf);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer window specs.
+ * @details Gets the window specifications of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] windowp pointer to the window specifications
+ *
+ * @iclass
+ */
+void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(windowp != NULL);
+ (void)ltdcp;
+
+ windowp->hstart =
+ (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0);
+ windowp->hstop =
+ (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16);
+ windowp->vstart =
+ (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0);
+ windowp->vstop =
+ (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16);
+}
+
+/**
+ * @brief Get foreground layer window specs.
+ * @details Gets the window specifications of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] windowp pointer to the window specifications
+ *
+ * @api
+ */
+void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) {
+
+ osalSysLock();
+ ltdcFgGetWindowI(ltdcp, windowp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer window specs.
+ * @details Sets the window specifications of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] windowp pointer to the window specifications
+ *
+ * @iclass
+ */
+void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) {
+
+ uint32_t start, stop;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(windowp != NULL);
+ (void)ltdcp;
+
+ osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds");
+ osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds");
+
+ /* Horizontal boundaries.*/
+ start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart;
+ stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart;
+
+ osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds");
+ osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds");
+
+ LTDC_Layer2->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) |
+ ((stop << 16) & LTDC_LxWHPCR_WHSPPOS));
+
+ /* Vertical boundaries.*/
+ start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart;
+ stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart;
+
+ osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds");
+ osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds");
+
+ LTDC_Layer2->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) |
+ ((stop << 16) & LTDC_LxWVPCR_WVSPPOS));
+}
+
+/**
+ * @brief Set foreground layer window specs.
+ * @details Sets the window specifications of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] windowp pointer to the window specifications
+ *
+ * @api
+ */
+void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) {
+
+ osalSysLock();
+ ltdcFgSetWindowI(ltdcp, windowp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer window as invalid.
+ * @details Sets the window specifications of the foreground layer (layer 2)
+ * so that the window is pixel sized at the screen origin.
+ * @note Useful before reconfiguring the frame specifications of the layer,
+ * to avoid errors.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @iclass
+ */
+void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp) {
+
+ ltdcFgSetWindowI(ltdcp, <dc_invalid_window);
+}
+
+/**
+ * @brief Set foreground layer window as invalid.
+ * @details Sets the window specifications of the foreground layer (layer 2)
+ * so that the window is pixel sized at the screen origin.
+ * @note Useful before reconfiguring the frame specifications of the layer,
+ * to avoid errors.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @api
+ */
+void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp) {
+
+ osalSysLock();
+ ltdcFgSetWindowI(ltdcp, <dc_invalid_window);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer frame buffer specs.
+ * @details Gets the frame buffer specifications of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] framep pointer to the frame buffer specifications
+ *
+ * @iclass
+ */
+void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(framep != NULL);
+
+ framep->bufferp = (void *)(LTDC_Layer2->CFBAR & LTDC_LxCFBAR_CFBADD);
+ framep->pitch = (size_t)((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBP) >> 16);
+ framep->width = (uint16_t)(((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) /
+ ltdcBytesPerPixel(ltdcFgGetPixelFormatI(ltdcp)));
+ framep->height = (uint16_t)(LTDC_Layer2->CFBLNR & LTDC_LxCFBLNR_CFBLNBR);
+}
+
+/**
+ * @brief Get foreground layer frame buffer specs.
+ * @details Gets the frame buffer specifications of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] framep pointer to the frame buffer specifications
+ *
+ * @api
+ */
+void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) {
+
+ osalSysLock();
+ ltdcFgGetFrameI(ltdcp, framep);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer frame buffer specs.
+ * @details Sets the frame buffer specifications of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] framep pointer to the frame buffer specifications
+ *
+ * @iclass
+ */
+void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) {
+
+ size_t linesize;
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(framep != NULL);
+
+ ltdcFgSetPixelFormatI(ltdcp, framep->fmt);
+
+ linesize = ltdcBytesPerPixel(framep->fmt) * framep->width;
+
+ osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds");
+ osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds");
+ osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds");
+ osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds");
+ osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds");
+ osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds");
+ osalDbgAssert(framep->pitch >= linesize, "bounds");
+
+ LTDC_Layer2->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD;
+ LTDC_Layer2->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) |
+ ((linesize + 3) & LTDC_LxCFBLR_CFBLL));
+ LTDC_Layer2->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR;
+}
+
+/**
+ * @brief Set foreground layer frame buffer specs.
+ * @details Sets the frame buffer specifications of the foreground layer
+ * (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] framep pointer to the frame buffer specifications
+ *
+ * @api
+ */
+void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) {
+
+ osalSysLock();
+ ltdcFgSetFrameI(ltdcp, framep);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer frame buffer address.
+ * @details Gets the frame buffer address of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return frame buffer address
+ *
+ * @iclass
+ */
+void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ return (void *)LTDC_Layer2->CFBAR;
+}
+
+/**
+ * @brief Get foreground layer frame buffer address.
+ * @details Gets the frame buffer address of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ *
+ * @return frame buffer address
+ *
+ * @api
+ */
+void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp) {
+
+ void *bufferp;
+ osalSysLock();
+ bufferp = ltdcFgGetFrameAddressI(ltdcp);
+ osalSysUnlock();
+ return bufferp;
+}
+
+/**
+ * @brief Set foreground layer frame buffer address.
+ * @details Sets the frame buffer address of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] bufferp frame buffer address
+ *
+ * @iclass
+ */
+void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ (void)ltdcp;
+
+ LTDC_Layer2->CFBAR = (uint32_t)bufferp;
+}
+
+/**
+ * @brief Set foreground layer frame buffer address.
+ * @details Sets the frame buffer address of the foreground layer (layer 2).
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] bufferp frame buffer address
+ *
+ * @api
+ */
+void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) {
+
+ osalSysLock();
+ ltdcFgSetFrameAddressI(ltdcp, bufferp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Get foreground layer specifications.
+ * @details Gets the foreground layer (layer 2) specifications at once.
+ * @note If palette specifications cannot be retrieved, they are set to
+ * @p NULL. This is not an error.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+ osalDbgCheck(cfgp != NULL);
+
+ ltdcFgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame);
+ ltdcFgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window);
+ cfgp->def_color = ltdcFgGetDefaultColorI(ltdcp);
+ cfgp->key_color = ltdcFgGetKeyingColorI(ltdcp);
+ cfgp->const_alpha = ltdcFgGetConstantAlphaI(ltdcp);
+ cfgp->blending = ltdcFgGetBlendingFactorsI(ltdcp);
+
+ cfgp->pal_colors = NULL;
+ cfgp->pal_length = 0;
+
+ cfgp->flags = ltdcFgGetEnableFlagsI(ltdcp);
+}
+
+/**
+ * @brief Get foreground layer specifications.
+ * @details Gets the foreground layer (layer 2) specifications at once.
+ * @note If palette specifications cannot be retrieved, they are set to
+ * @p NULL. This is not an error.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[out] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) {
+
+ osalSysLock();
+ ltdcFgGetLayerI(ltdcp, cfgp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Set foreground layer specifications.
+ * @details Sets the foreground layer (layer 2) specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @iclass
+ */
+void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(ltdcp == <DCD1);
+
+ if (cfgp == NULL)
+ cfgp = <dc_default_laycfg;
+
+ osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0));
+
+ ltdcFgSetFrameI(ltdcp, cfgp->frame);
+ ltdcFgSetWindowI(ltdcp, cfgp->window);
+ ltdcFgSetDefaultColorI(ltdcp, cfgp->def_color);
+ ltdcFgSetKeyingColorI(ltdcp, cfgp->key_color);
+ ltdcFgSetConstantAlphaI(ltdcp, cfgp->const_alpha);
+ ltdcFgSetBlendingFactorsI(ltdcp, cfgp->blending);
+
+ if (cfgp->pal_length > 0)
+ ltdcFgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length);
+
+ ltdcFgSetEnableFlagsI(ltdcp, cfgp->flags);
+}
+
+/**
+ * @brief Set foreground layer specifications.
+ * @details Sets the foreground layer (layer 2) specifications at once.
+ * @note If the palette is unspecified, the layer palette is unmodified.
+ *
+ * @param[in] ltdcp pointer to the @p LTDCDriver object
+ * @param[in] cfgp pointer to the layer specifications
+ *
+ * @api
+ */
+void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) {
+
+ osalSysLock();
+ ltdcFgSetConfigI(ltdcp, cfgp);
+ osalSysUnlock();
+}
+
+/** @} */
+
+/**
+ * @name LTDC helper functions
+ */
+
+/**
+ * @brief Compute bits per pixel.
+ * @details Computes the bits per pixel for the specified pixel format.
+ *
+ * @param[in] fmt pixel format
+ *
+ * @retuen bits per pixel
+ *
+ * @api
+ */
+size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt) {
+
+ osalDbgAssert(fmt < LTDC_MAX_PIXFMT_ID, "invalid format");
+
+ return (size_t)ltdc_bpp[(unsigned)fmt];
+}
+
+#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
+
+/**
+ * @brief Convert from ARGB-8888.
+ * @details Converts an ARGB-8888 color to the specified pixel format.
+ *
+ * @param[in] c color, ARGB-8888
+ * @param[in] fmt target pixel format
+ *
+ * @return raw color value for the target pixel format, left
+ * padded with zeros.
+ *
+ * @api
+ */
+ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) {
+
+ switch (fmt) {
+ case LTDC_FMT_ARGB8888: {
+ return c;
+ }
+ case LTDC_FMT_RGB888: {
+ return (c & 0x00FFFFFF);
+ }
+ case LTDC_FMT_RGB565: {
+ return (((c & 0x000000F8) >> ( 8 - 5)) |
+ ((c & 0x0000FC00) >> (16 - 11)) |
+ ((c & 0x00F80000) >> (24 - 16)));
+ }
+ case LTDC_FMT_ARGB1555: {
+ return (((c & 0x000000F8) >> ( 8 - 5)) |
+ ((c & 0x0000F800) >> (16 - 10)) |
+ ((c & 0x00F80000) >> (24 - 15)) |
+ ((c & 0x80000000) >> (32 - 16)));
+ }
+ case LTDC_FMT_ARGB4444: {
+ return (((c & 0x000000F0) >> ( 8 - 4)) |
+ ((c & 0x0000F000) >> (16 - 8)) |
+ ((c & 0x00F00000) >> (24 - 12)) |
+ ((c & 0xF0000000) >> (32 - 16)));
+ }
+ case LTDC_FMT_L8: {
+ return (c & 0x000000FF);
+ }
+ case LTDC_FMT_AL44: {
+ return (((c & 0x000000F0) >> ( 8 - 4)) |
+ ((c & 0xF0000000) >> (32 - 8)));
+ }
+ case LTDC_FMT_AL88: {
+ return (((c & 0x000000FF) >> ( 8 - 8)) |
+ ((c & 0xFF000000) >> (32 - 16)));
+ }
+ default:
+ osalDbgAssert(false, "invalid format");
+ return 0;
+ }
+}
+
+/**
+ * @brief Convert to ARGB-8888.
+ * @details Converts color of the specified pixel format to an ARGB-8888 color.
+ *
+ * @param[in] c color for the source pixel format, left padded with
+ * zeros.
+ * @param[in] fmt source pixel format
+ *
+ * @return color in ARGB-8888 format
+ *
+ * @api
+ */
+ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) {
+
+ switch (fmt) {
+ case LTDC_FMT_ARGB8888: {
+ return c;
+ }
+ case LTDC_FMT_RGB888: {
+ return ((c & 0x00FFFFFF) | 0xFF000000);
+ }
+ case LTDC_FMT_RGB565: {
+ register ltdc_color_t output = 0xFF000000;
+ if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007);
+ if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300);
+ if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000);
+ return output;
+ }
+ case LTDC_FMT_ARGB1555: {
+ register ltdc_color_t output = 0x00000000;
+ if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007);
+ if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700);
+ if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000);
+ if (c & 0x8000) output |= 0xFF000000;
+ return output;
+ }
+ case LTDC_FMT_ARGB4444: {
+ register ltdc_color_t output = 0x00000000;
+ if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F);
+ if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00);
+ if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000);
+ if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000);
+ return output;
+ }
+ case LTDC_FMT_L8: {
+ return ((c & 0xFF) | 0xFF000000);
+ }
+ case LTDC_FMT_AL44: {
+ register ltdc_color_t output = 0x00000000;
+ if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F);
+ if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000);
+ return output;
+ }
+ case LTDC_FMT_AL88: {
+ return (((c & 0x00FF) << ( 8 - 8)) |
+ ((c & 0xFF00) << (32 - 16)));
+ }
+ default:
+ osalDbgAssert(false, "invalid format");
+ return 0;
+ }
+}
+
+#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */
+
+/** @} */
+
+/** @} */
+
+#endif /* STM32_LTDC_USE_LTDC */
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.h b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.h new file mode 100644 index 0000000..fdf1f5b --- /dev/null +++ b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.h @@ -0,0 +1,736 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file stm32_ltdc.h
+ * @brief LCD-TFT Controller Driver.
+ *
+ * @addtogroup ltdc
+ * @{
+ */
+
+#ifndef _STM32_LTDC_H_
+#define _STM32_LTDC_H_
+
+/**
+ * @brief Using the LTDC driver.
+ */
+#if !defined(STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__)
+#define STM32_LTDC_USE_LTDC (FALSE)
+#endif
+
+#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name LTDC enable flags
+ * @{
+ */
+#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/
+#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/
+#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/
+#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/
+#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/
+#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/
+
+#define LTDC_EF_MASK \
+ (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | \
+ LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH)
+/** @} */
+
+/**
+ * @name LTDC layer enable flags
+ * @{
+ */
+#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/
+#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/
+#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/
+
+#define LTDC_LEF_MASK \
+ (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE)
+/** @} */
+
+/**
+ * @name LTDC pixel formats
+ * @{
+ */
+#define LTDC_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/
+#define LTDC_FMT_RGB888 (1) /**< RGB-888 format.*/
+#define LTDC_FMT_RGB565 (2) /**< RGB-565 format.*/
+#define LTDC_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/
+#define LTDC_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/
+#define LTDC_FMT_L8 (5) /**< L-8 format.*/
+#define LTDC_FMT_AL44 (6) /**< AL-44 format.*/
+#define LTDC_FMT_AL88 (7) /**< AL-88 format.*/
+/** @} */
+
+/**
+ * @name LTDC pixel format aliased raw masks
+ * @{
+ */
+#define LTDC_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/
+#define LTDC_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/
+#define LTDC_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/
+#define LTDC_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/
+#define LTDC_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/
+#define LTDC_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/
+#define LTDC_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/
+#define LTDC_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/
+/** @} */
+
+/**
+ * @name LTDC blending factors
+ * @{
+ */
+#define LTDC_BLEND_FIX1_FIX2 (0x0405) /**< cnst1; 1 - cnst2 */
+#define LTDC_BLEND_FIX1_MOD2 (0x0407) /**< cnst1; 1 - a2 * cnst2 */
+#define LTDC_BLEND_MOD1_FIX2 (0x0605) /**< a1 * cnst1; 1 - cnst2 */
+#define LTDC_BLEND_MOD1_MOD2 (0x0607) /**< a1 * cnst1; 1 - a2 * cnst2 */
+/** @} */
+
+/**
+ * @name LTDC parameter bounds
+ * @{
+ */
+
+#define LTDC_MIN_SCREEN_WIDTH (1)
+#define LTDC_MIN_SCREEN_HEIGHT (1)
+#define LTDC_MAX_SCREEN_WIDTH (800)
+#define LTDC_MAX_SCREEN_HEIGHT (600)
+
+#define LTDC_MIN_HSYNC_WIDTH (1)
+#define LTDC_MIN_VSYNC_HEIGHT (1)
+#define LTDC_MAX_HSYNC_WIDTH (1 << 12)
+#define LTDC_MAX_VSYNC_HEIGHT (1 << 11)
+
+#define LTDC_MIN_HBP_WIDTH (0)
+#define LTDC_MIN_VBP_HEIGHT (0)
+#define LTDC_MAX_HBP_WIDTH (1 << 12)
+#define LTDC_MAX_VBP_HEIGHT (1 << 11)
+
+#define LTDC_MIN_ACC_HBP_WIDTH (1)
+#define LTDC_MIN_ACC_VBP_HEIGHT (1)
+#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12)
+#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11)
+
+#define LTDC_MIN_HFP_WIDTH (0)
+#define LTDC_MIN_VFP_HEIGHT (0)
+#define LTDC_MAX_HFP_WIDTH (1 << 12)
+#define LTDC_MAX_VFP_HEIGHT (1 << 11)
+
+#define LTDC_MIN_ACTIVE_WIDTH (0)
+#define LTDC_MIN_ACTIVE_HEIGHT (0)
+#define LTDC_MAX_ACTIVE_WIDTH (1 << 12)
+#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11)
+
+#define LTDC_MIN_ACC_ACTIVE_WIDTH (1)
+#define LTDC_MIN_ACC_ACTIVE_HEIGHT (1)
+#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12)
+#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11)
+
+#define LTDC_MIN_ACC_TOTAL_WIDTH (1)
+#define LTDC_MIN_ACC_TOTAL_HEIGHT (1)
+#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12)
+#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11)
+
+#define LTDC_MIN_LINE_INTERRUPT_POS (0)
+#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1)
+
+#define LTDC_MIN_WINDOW_HSTART (0)
+#define LTDC_MIN_WINDOW_HSTART (0)
+#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
+#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
+
+#define LTDC_MIN_WINDOW_VSTART (0)
+#define LTDC_MIN_WINDOW_VSTART (0)
+#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
+#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
+
+#define LTDC_MIN_FRAME_WIDTH_BYTES (0)
+#define LTDC_MIN_FRAME_HEIGHT_LINES (0)
+#define LTDC_MIN_FRAME_PITCH_BYTES (0)
+#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3)
+#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1)
+#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1)
+
+#define LTDC_MIN_PIXFMT_ID (0)
+#define LTDC_MAX_PIXFMT_ID (7)
+
+#define LTDC_MAX_PALETTE_LENGTH (256)
+
+/** @} */
+
+/**
+ * @name LTDC basic ARGB-8888 colors.
+ * @{
+ */
+/* Microsoft Windows default 16-color palette.*/
+#define LTDC_COLOR_BLACK (0xFF000000)
+#define LTDC_COLOR_MAROON (0xFF800000)
+#define LTDC_COLOR_GREEN (0xFF008000)
+#define LTDC_COLOR_OLIVE (0xFF808000)
+#define LTDC_COLOR_NAVY (0xFF000080)
+#define LTDC_COLOR_PURPLE (0xFF800080)
+#define LTDC_COLOR_TEAL (0xFF008080)
+#define LTDC_COLOR_SILVER (0xFFC0C0C0)
+#define LTDC_COLOR_GRAY (0xFF808080)
+#define LTDC_COLOR_RED (0xFFFF0000)
+#define LTDC_COLOR_LIME (0xFF00FF00)
+#define LTDC_COLOR_YELLOW (0xFFFFFF00)
+#define LTDC_COLOR_BLUE (0xFF0000FF)
+#define LTDC_COLOR_FUCHSIA (0xFFFF00FF)
+#define LTDC_COLOR_AQUA (0xFF00FFFF)
+#define LTDC_COLOR_WHITE (0xFFFFFFFF)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name LTDC configuration options
+ * @{
+ */
+
+/**
+ * @brief LTDC event interrupt priority level setting.
+ */
+#if !defined(STM32_LTDC_EV_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_LTDC_EV_IRQ_PRIORITY (11)
+#endif
+
+/**
+ * @brief LTDC error interrupt priority level setting.
+ */
+#if !defined(STM32_LTDC_ER_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_LTDC_ER_IRQ_PRIORITY (11)
+#endif
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(LTDC_USE_WAIT) || defined(__DOXYGEN__)
+#define LTDC_USE_WAIT (TRUE)
+#endif
+
+/**
+ * @brief Enables the @p ltdcAcquireBus() and @p ltdcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(LTDC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define LTDC_USE_MUTUAL_EXCLUSION (TRUE)
+#endif
+
+/**
+ * @brief Provides software color conversion functions.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
+#define LTDC_USE_SOFTWARE_CONVERSIONS (TRUE)
+#endif
+
+/**
+ * @brief Enables checks for LTDC functions.
+ * @note Disabling this option saves both code and data space.
+ * @note Disabling checks by ChibiOS will automatically disable LTDC checks.
+ */
+#if !defined(LTDC_USE_CHECKS) || defined(__DOXYGEN__)
+#define LTDC_USE_CHECKS (TRUE)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (TRUE != STM32_HAS_LTDC)
+#error "LTDC must be present when using the LTDC subsystem"
+#endif
+
+#if (TRUE == STM32_LTDC_USE_LTDC) && (TRUE != STM32_HAS_LTDC)
+#error "LTDC not present in the selected device"
+#endif
+
+#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
+#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES)
+#error "LTDC_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* Complex types forwarding.*/
+typedef union ltdc_coloralias_t ltdc_coloralias_t;
+typedef struct ltdc_window_t ltdc_window_t;
+typedef struct ltdc_frame_t ltdc_frame_t;
+typedef struct ltdc_laycfg_t ltdc_laycfg_t;
+typedef struct LTDCConfig LTDCConfig;
+typedef enum ltdc_state_t ltdc_state_t;
+typedef struct LTDCDriver LTDCDriver;
+
+/**
+ * @name LTDC Data types
+ * @{
+ */
+
+/**
+ * @brief LTDC generic color.
+ */
+typedef uint32_t ltdc_color_t;
+
+/**
+ * @brief LTDC color aliases.
+ * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B).
+ * Padding fields are prefixed with <tt>'x'</tt>, and should be clear
+ * (all 0) before compression and set (all 1) after expansion.
+ */
+typedef union ltdc_coloralias_t {
+ struct {
+ unsigned b : 8;
+ unsigned g : 8;
+ unsigned r : 8;
+ unsigned a : 8;
+ } argb8888; /**< Mapped ARGB-8888 bits.*/
+ struct {
+ unsigned b : 8;
+ unsigned g : 8;
+ unsigned r : 8;
+ unsigned xa : 8;
+ } rgb888; /**< Mapped RGB-888 bits.*/
+ struct {
+ unsigned xb : 3;
+ unsigned b : 5;
+ unsigned xg : 2;
+ unsigned g : 6;
+ unsigned xr : 3;
+ unsigned r : 5;
+ unsigned xa : 8;
+ } rgb565; /**< Mapped RGB-565 bits.*/
+ struct {
+ unsigned xb : 3;
+ unsigned b : 5;
+ unsigned xg : 3;
+ unsigned g : 5;
+ unsigned xr : 3;
+ unsigned r : 5;
+ unsigned xa : 7;
+ unsigned a : 1;
+ } argb1555; /**< Mapped ARGB-1555 values.*/
+ struct {
+ unsigned xb : 4;
+ unsigned b : 4;
+ unsigned xg : 4;
+ unsigned g : 4;
+ unsigned xr : 4;
+ unsigned r : 4;
+ unsigned xa : 4;
+ unsigned a : 4;
+ } argb4444; /**< Mapped ARGB-4444 values.*/
+ struct {
+ unsigned l : 8;
+ unsigned x : 16;
+ unsigned xa : 8;
+ } l8; /**< Mapped L-8 bits.*/
+ struct {
+ unsigned xl : 4;
+ unsigned l : 4;
+ unsigned x : 16;
+ unsigned xa : 4;
+ unsigned a : 4;
+ } al44; /**< Mapped AL-44 bits.*/
+ struct {
+ unsigned l : 8;
+ unsigned x : 16;
+ unsigned a : 8;
+ } al88; /**< Mapped AL-88 bits.*/
+ ltdc_color_t aliased; /**< Aliased raw bits.*/
+} ltdc_coloralias_t;
+
+/**
+ * @brief LTDC layer identifier.
+ */
+typedef uint32_t ltdc_layerid_t;
+
+/**
+ * @brief LTDC pixel format.
+ */
+typedef uint32_t ltdc_pixfmt_t;
+
+/**
+ * @brief LTDC blending factor.
+ */
+typedef uint32_t ltdc_blendf_t;
+
+/**
+ * @brief LTDC ISR callback.
+ */
+typedef void (*ltdc_isrcb_t)(LTDCDriver *ltdcp);
+
+/**
+ * @brief LTDC window specifications.
+ */
+typedef struct ltdc_window_t {
+ uint16_t hstart; /**< Horizontal start pixel (left).*/
+ uint16_t hstop; /**< Horizontal stop pixel (right).*/
+ uint16_t vstart; /**< Vertical start pixel (top).*/
+ uint16_t vstop; /**< Vertical stop pixel (bottom).*/
+} ltdc_window_t;
+
+/**
+ * @brief LTDC frame specifications.
+ */
+typedef struct ltdc_frame_t {
+ void *bufferp; /**< Frame buffer address.*/
+ uint16_t width; /**< Frame width, in pixels.*/
+ uint16_t height; /**< Frame height, in pixels.*/
+ size_t pitch; /**< Line pitch, in bytes.*/
+ ltdc_pixfmt_t fmt; /**< Pixel format.*/
+} ltdc_frame_t;
+
+/**
+ * @brief LTDC configuration flags.
+ */
+typedef uint8_t ltdc_flags_t;
+
+/**
+ * @brief LTDC startup layer configuration.
+ */
+typedef struct ltdc_laycfg_t {
+ const ltdc_frame_t *frame; /**< Frame buffer specifications.*/
+ const ltdc_window_t *window; /**< Window specifications.*/
+ ltdc_color_t def_color; /**< Default color, ARGB-8888.*/
+ uint8_t const_alpha; /**< Constant alpha factor.*/
+ ltdc_color_t key_color; /**< Color key.*/
+ const ltdc_color_t *pal_colors; /**< Palette colors, or @p NULL.*/
+ uint16_t pal_length; /**< Palette length, or @p 0.*/
+ ltdc_blendf_t blending; /**< Blending factors.*/
+ ltdc_flags_t flags; /**< Layer configuration flags.*/
+} ltdc_laycfg_t;
+
+/**
+ * @brief LTDC driver configuration.
+ */
+typedef struct LTDCConfig {
+ /* Display specifications.*/
+ uint16_t screen_width; /**< Screen pixel width.*/
+ uint16_t screen_height; /**< Screen pixel height.*/
+ uint16_t hsync_width; /**< Horizontal sync pixel width.*/
+ uint16_t vsync_height; /**< Vertical sync pixel height.*/
+ uint16_t hbp_width; /**< Horizontal back porch pixel width.*/
+ uint16_t vbp_height; /**< Vertical back porch pixel height.*/
+ uint16_t hfp_width; /**< Horizontal front porch pixel width.*/
+ uint16_t vfp_height; /**< Vertical front porch pixel height.*/
+ ltdc_flags_t flags; /**< Driver configuration flags.*/
+
+ /* ISR callbacks.*/
+ ltdc_isrcb_t line_isr; /**< Line Interrupt ISR, or @p NULL.*/
+ ltdc_isrcb_t rr_isr; /**< Register Reload ISR, or @p NULL.*/
+ ltdc_isrcb_t fuerr_isr; /**< FIFO Underrun ISR, or @p NULL.*/
+ ltdc_isrcb_t terr_isr; /**< Transfer Error ISR, or @p NULL.*/
+
+ /* Layer and color settings.*/
+ ltdc_color_t clear_color; /**< Clear screen color, RGB-888.*/
+ const ltdc_laycfg_t *bg_laycfg; /**< Background layer specs, or @p NULL.*/
+ const ltdc_laycfg_t *fg_laycfg; /**< Foreground layer specs, or @p NULL.*/
+} LTDCConfig;
+
+/**
+ * @brief LTDC driver state.
+ */
+typedef enum ltdc_state_t {
+ LTDC_UNINIT = (0), /**< Not initialized.*/
+ LTDC_STOP = (1), /**< Stopped.*/
+ LTDC_READY = (2), /**< Ready.*/
+ LTDC_ACTIVE = (3), /**< Executing commands.*/
+} ltdc_state_t;
+
+/**
+ * @brief LTDC driver.
+ */
+typedef struct LTDCDriver {
+ ltdc_state_t state; /**< Driver state.*/
+ const LTDCConfig *config; /**< Driver configuration.*/
+
+ /* Handy computations.*/
+ ltdc_window_t active_window; /**< Active window coordinates.*/
+
+ /* Multithreading stuff.*/
+#if (TRUE == LTDC_USE_WAIT) || defined(__DOXYGEN__)
+ thread_t *thread; /**< Waiting thread.*/
+#endif /* LTDC_USE_WAIT */
+#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ mutex_t lock; /**< Multithreading lock.*/
+#elif (TRUE == CH_CFG_USE_SEMAPHORES)
+ semaphore_t lock; /**< Multithreading lock.*/
+#endif
+#endif /* LTDC_USE_MUTUAL_EXCLUSION */
+} LTDCDriver;
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Makes an ARGB-8888 value from byte components.
+ *
+ * @param[in] a alpha byte component
+ * @param[in] r red byte component
+ * @param[in] g green byte component
+ * @param[in] b blue byte component
+ *
+ * @return color in ARGB-8888 format
+ *
+ * @api
+ */
+#define ltdcMakeARGB8888(a, r, g, b) \
+ ((((ltdc_color_t)(a) & 0xFF) << 24) | \
+ (((ltdc_color_t)(r) & 0xFF) << 16) | \
+ (((ltdc_color_t)(g) & 0xFF) << 8) | \
+ (((ltdc_color_t)(b) & 0xFF) << 0))
+
+/**
+ * @brief Compute bytes per pixel.
+ * @details Computes the bytes per pixel for the specified pixel format.
+ * Rounds to the ceiling.
+ *
+ * @param[in] fmt pixel format
+ *
+ * @return bytes per pixel
+ *
+ * @api
+ */
+#define ltdcBytesPerPixel(fmt) \
+ ((ltdcBitsPerPixel(fmt) + 7) >> 3)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern LTDCDriver LTDCD1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ /* Driver methods.*/
+ void ltdcInit(void);
+ void ltdcObjectInit(LTDCDriver *ltdcp);
+ ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp);
+ ltdc_state_t ltdcGetState(LTDCDriver *ltdcp);
+ void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp);
+ void ltdcStop(LTDCDriver *ltdcp);
+#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
+ void ltdcAcquireBusS(LTDCDriver *ltdcp);
+ void ltdcAcquireBus(LTDCDriver *ltdcp);
+ void ltdcReleaseBusS(LTDCDriver *ltdcp);
+ void ltdcReleaseBus(LTDCDriver *ltdcp);
+#endif /* LTDC_USE_MUTUAL_EXCLUSION */
+
+ /* Global methods.*/
+ ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp);
+ ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp);
+ void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ bool ltdcIsReloadingI(LTDCDriver *ltdcp);
+ bool ltdcIsReloading(LTDCDriver *ltdcp);
+ void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately);
+ void ltdcStartReload(LTDCDriver *ltdcp, bool immediately);
+ void ltdcReloadS(LTDCDriver *ltdcp, bool immediately);
+ void ltdcReload(LTDCDriver *ltdcp, bool immediately);
+ bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp);
+ bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp);
+ void ltdcEnableDitheringI(LTDCDriver *ltdcp);
+ void ltdcEnableDithering(LTDCDriver *ltdcp);
+ void ltdcDisableDitheringI(LTDCDriver *ltdcp);
+ void ltdcDisableDithering(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp);
+ void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c);
+ void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c);
+ uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp);
+ uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp);
+ void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line);
+ void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line);
+ bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp);
+ bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp);
+ void ltdcEnableLineInterruptI(LTDCDriver *ltdcp);
+ void ltdcEnableLineInterrupt(LTDCDriver *ltdcp);
+ void ltdcDisableLineInterruptI(LTDCDriver *ltdcp);
+ void ltdcDisableLineInterrupt(LTDCDriver *ltdcp);
+ void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
+ void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
+
+ /* Background layer methods.*/
+ ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp);
+ ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp);
+ void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ bool ltdcBgIsEnabledI(LTDCDriver *ltdcp);
+ bool ltdcBgIsEnabled(LTDCDriver *ltdcp);
+ void ltdcBgEnableI(LTDCDriver *ltdcp);
+ void ltdcBgEnable(LTDCDriver *ltdcp);
+ void ltdcBgDisableI(LTDCDriver *ltdcp);
+ void ltdcBgDisable(LTDCDriver *ltdcp);
+ bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp);
+ bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp);
+ void ltdcBgEnablePaletteI(LTDCDriver *ltdcp);
+ void ltdcBgEnablePalette(LTDCDriver *ltdcp);
+ void ltdcBgDisablePaletteI(LTDCDriver *ltdcp);
+ void ltdcBgDisablePalette(LTDCDriver *ltdcp);
+ void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
+ void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
+ void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length);
+ void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length);
+ ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp);
+ ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp);
+ void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
+ void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
+ bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp);
+ bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp);
+ void ltdcBgEnableKeyingI(LTDCDriver *ltdcp);
+ void ltdcBgEnableKeying(LTDCDriver *ltdcp);
+ void ltdcBgDisableKeyingI(LTDCDriver *ltdcp);
+ void ltdcBgDisableKeying(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp);
+ void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
+ void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
+ uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp);
+ uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp);
+ void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
+ void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
+ ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp);
+ void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
+ void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
+ ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp);
+ ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp);
+ void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
+ void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
+ void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
+ void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
+ void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
+ void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
+ void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp);
+ void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp);
+ void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
+ void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
+ void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
+ void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
+ void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp);
+ void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp);
+ void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
+ void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
+ void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
+ void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
+ void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
+ void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
+
+ /* Foreground layer methods.*/
+ ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp);
+ ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp);
+ void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
+ bool ltdcFgIsEnabledI(LTDCDriver *ltdcp);
+ bool ltdcFgIsEnabled(LTDCDriver *ltdcp);
+ void ltdcFgEnableI(LTDCDriver *ltdcp);
+ void ltdcFgEnable(LTDCDriver *ltdcp);
+ void ltdcFgDisableI(LTDCDriver *ltdcp);
+ void ltdcFgDisable(LTDCDriver *ltdcp);
+ bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp);
+ bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp);
+ void ltdcFgEnablePaletteI(LTDCDriver *ltdcp);
+ void ltdcFgEnablePalette(LTDCDriver *ltdcp);
+ void ltdcFgDisablePaletteI(LTDCDriver *ltdcp);
+ void ltdcFgDisablePalette(LTDCDriver *ltdcp);
+ void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
+ void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
+ void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length);
+ void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
+ uint16_t length);
+ ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp);
+ ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp);
+ void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
+ void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
+ bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp);
+ bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp);
+ void ltdcFgEnableKeyingI(LTDCDriver *ltdcp);
+ void ltdcFgEnableKeying(LTDCDriver *ltdcp);
+ void ltdcFgDisableKeyingI(LTDCDriver *ltdcp);
+ void ltdcFgDisableKeying(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp);
+ void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
+ void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
+ uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp);
+ uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp);
+ void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
+ void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
+ ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp);
+ ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp);
+ void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
+ void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
+ ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp);
+ ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp);
+ void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
+ void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
+ void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
+ void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
+ void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
+ void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
+ void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp);
+ void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp);
+ void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
+ void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
+ void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
+ void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
+ void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp);
+ void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp);
+ void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
+ void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
+ void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
+ void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
+ void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
+ void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
+
+ /* Helper functions.*/
+ size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt);
+#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
+ ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
+ ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
+#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_LTDC_USE_LTDC */
+
+#endif /* _STM32_LTDC_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c index ff62928..a3e6cbd 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c @@ -247,7 +247,7 @@ static eicucnt_t get_time_width(const EICUDriver *eicup, } /** - * @brief Returns both pulse period. + * @brief Returns pulse period. * @details The time is defined as number of ticks. * * @param[in] eicup Pointer to the EICUDriver object. @@ -949,7 +949,7 @@ void eicu_lld_start(EICUDriver *eicup) { rccResetTIM10(); nvicEnableVector(STM32_TIM10_NUMBER, STM32_EICU_TIM10_IRQ_PRIORITY); eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; + eicup->clock = STM32_TIMCLK2; } #endif #if STM32_EICU_USE_TIM11 @@ -958,7 +958,7 @@ void eicu_lld_start(EICUDriver *eicup) { rccResetTIM11(); nvicEnableVector(STM32_TIM11_NUMBER, STM32_EICU_TIM11_IRQ_PRIORITY); eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; + eicup->clock = STM32_TIMCLK2; } #endif #if STM32_EICU_USE_TIM13 diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index 598807e..022ff91 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -1,11 +1,15 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
-PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
+PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c \
${CHIBIOS}/community/os/hal/src/fsmc_sdram.c
-PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
+PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/DMA2Dv1 \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/LTDCv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD
diff --git a/os/hal/ports/TIVA/LLD/ext_lld.c b/os/hal/ports/TIVA/LLD/ext_lld.c new file mode 100644 index 0000000..dc58d99 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ext_lld.c @@ -0,0 +1,981 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.c + * @brief Tiva EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_lld_serve_port_interrupt(gpiop, start) \ + do { \ + uint32_t mis = gpiop->MIS; \ + \ + gpiop->ICR = mis; \ + \ + if (mis & (1 << 0)) { \ + EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ + } \ + if (mis & (1 << 1)) { \ + EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ + } \ + if (mis & (1 << 2)) { \ + EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ + } \ + if (mis & (1 << 3)) { \ + EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ + } \ + if (mis & (1 << 4)) { \ + EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ + } \ + if (mis & (1 << 5)) { \ + EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ + } \ + if (mis & (1 << 6)) { \ + EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ + } \ + if (mis & (1 << 7)) { \ + EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ + } \ + } while (0); + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ + do { \ + gpiop->ICR = (1 << pin); \ + EXTD1.config->channels[start].cb(&EXTD1, start); \ + } while (0); + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +const ioportid_t gpio[] = +{ +#if TIVA_HAS_GPIOA + GPIOA, +#endif +#if TIVA_HAS_GPIOB + GPIOB, +#endif +#if TIVA_HAS_GPIOC + GPIOC, +#endif +#if TIVA_HAS_GPIOD + GPIOD, +#endif +#if TIVA_HAS_GPIOE + GPIOE, +#endif +#if TIVA_HAS_GPIOF + GPIOF, +#endif +#if TIVA_HAS_GPIOG + GPIOG, +#endif +#if TIVA_HAS_GPIOH + GPIOH, +#endif +#if TIVA_HAS_GPIOJ + GPIOJ, +#endif +#if TIVA_HAS_GPIOK + GPIOK, +#endif +#if TIVA_HAS_GPIOL + GPIOL, +#endif +#if TIVA_HAS_GPIOM + GPIOM, +#endif +#if TIVA_HAS_GPION + GPION, +#endif +#if TIVA_HAS_GPIOP + GPIOP, +#endif +#if TIVA_HAS_GPIOQ + GPIOQ, +#endif +#if TIVA_HAS_GPIOR + GPIOR, +#endif +#if TIVA_HAS_GPIOS + GPIOS, +#endif +#if TIVA_HAS_GPIOT + GPIOT, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Enables GPIO IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables GPIO IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_disable(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) +{ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) +{ + uint8_t i; + + if (extp->state == EXT_STOP) { + ext_lld_irq_enable(); + } + + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { + ext_lld_channel_enable(extp, i); + } + else { + ext_lld_channel_disable(extp, i); + } + } +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) +{ + if (extp->state == EXT_ACTIVE) { + ext_lld_irq_disable(); + } + +#if TIVA_HAS_GPIOA + GPIOA->IM = 0; +#endif +#if TIVA_HAS_GPIOB + GPIOB->IM = 0; +#endif +#if TIVA_HAS_GPIOC + GPIOC->IM = 0; +#endif +#if TIVA_HAS_GPIOD + GPIOD->IM = 0; +#endif +#if TIVA_HAS_GPIOE + GPIOE->IM = 0; +#endif +#if TIVA_HAS_GPIOF + GPIOF->IM = 0; +#endif +#if TIVA_HAS_GPIOG + GPIOG->IM = 0; +#endif +#if TIVA_HAS_GPIOH + GPIOH->IM = 0; +#endif +#if TIVA_HAS_GPIOJ + GPIOJ->IM = 0; +#endif +#if TIVA_HAS_GPIOK + GPIOK->IM = 0; +#endif +#if TIVA_HAS_GPIOL + GPIOL->IM = 0; +#endif +#if TIVA_HAS_GPIOM + GPIOM->IM = 0; +#endif +#if TIVA_HAS_GPION + GPION->IM = 0; +#endif +#if TIVA_HAS_GPIOP + GPIOP->IM = 0; +#endif +#if TIVA_HAS_GPIOQ + GPIOQ->IM = 0; +#endif +#if TIVA_HAS_GPIOR + GPIOR->IM = 0; +#endif +#if TIVA_HAS_GPIOS + GPIOS->IM = 0; +#endif +#if TIVA_HAS_GPIOT + GPIOT->IM = 0; +#endif +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) +{ + GPIO_TypeDef *gpiop; + uint8_t pin; + uint32_t im; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + /* Disable interrupts */ + im = gpiop->IM; + gpiop->IM = 0; + + /* Configure pin to be edge-sensitive.*/ + gpiop->IS &= ~(1 << pin); + + /* Programming edge registers.*/ + if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_BOTH_EDGES) { + gpiop->IBE |= (1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_FALLING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV &= ~(1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_RISING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV |= (1 << pin); + } + + /* Programming interrupt and event registers.*/ + if ((extp->config->channels[channel].cb != NULL) && + ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != + EXT_CH_MODE_DISABLED)) { + im |= (1 << pin); + } + else { + im &= ~(1 << pin); + } + + /* Restore interrupts */ + gpiop->IM = im; +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + GPIO_TypeDef *gpiop; + uint8_t pin; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + gpiop->IM &= ~(1 << pin); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/ext_lld.h b/os/hal/ports/TIVA/LLD/ext_lld.h new file mode 100644 index 0000000..3817130 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ext_lld.h @@ -0,0 +1,523 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.h + * @brief Tiva EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of EXT per port. + */ +#define EXT_MAX_CHANNELS TIVA_GPIO_PINS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOB interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOC interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOD interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOE interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOF interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOG interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOH interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOJ interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOK interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPION_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 +#endif +/** @} */ + +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/gpt_lld.h b/os/hal/ports/TIVA/LLD/gpt_lld.h index 0e27017..2f1f75d 100644 --- a/os/hal/ports/TIVA/LLD/gpt_lld.h +++ b/os/hal/ports/TIVA/LLD/gpt_lld.h @@ -294,62 +294,62 @@ #endif #if TIVA_GPT_USE_GPT0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT0" #endif #if TIVA_GPT_USE_GPT1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT1" #endif #if TIVA_GPT_USE_GPT2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT2" #endif #if TIVA_GPT_USE_GPT3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT3" #endif #if TIVA_GPT_USE_GPT4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT4" #endif #if TIVA_GPT_USE_GPT5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT5" #endif #if TIVA_GPT_USE_WGPT0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT0" #endif #if TIVA_GPT_USE_WGPT1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT1" #endif #if TIVA_GPT_USE_WGPT2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT2" #endif #if TIVA_GPT_USE_WGPT3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT3" #endif #if TIVA_GPT_USE_WGPT4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT4" #endif #if TIVA_GPT_USE_WGPT5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT5" #endif diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.c b/os/hal/ports/TIVA/LLD/i2c_lld.c index 4019a3b..f4c555b 100644 --- a/os/hal/ports/TIVA/LLD/i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/i2c_lld.c @@ -216,7 +216,7 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) break; } case STATE_READ_NEXT: { - if(i2cp->rxbytes == 0) { + if(i2cp->rxbytes == 2) { i2cp->intstate = STATE_READ_FINAL; } *(i2cp->rxbuf) = dp->MDR; diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.h b/os/hal/ports/TIVA/LLD/i2c_lld.h index 9b7b743..1479600 100644 --- a/os/hal/ports/TIVA/LLD/i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/i2c_lld.h @@ -300,52 +300,52 @@ #endif #if TIVA_I2C_USE_I2C0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C0" #endif #if TIVA_I2C_USE_I2C1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C1" #endif #if TIVA_I2C_USE_I2C2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C2" #endif #if TIVA_I2C_USE_I2C3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C3" #endif #if TIVA_I2C_USE_I2C4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C4" #endif #if TIVA_I2C_USE_I2C5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C5" #endif #if TIVA_I2C_USE_I2C6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C6" #endif #if TIVA_I2C_USE_I2C7 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C7" #endif #if TIVA_I2C_USE_I2C8 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C8" #endif #if TIVA_I2C_USE_I2C9 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C9" #endif diff --git a/os/hal/ports/TIVA/LLD/mac_lld.h b/os/hal/ports/TIVA/LLD/mac_lld.h index 7c86dbd..af088b0 100644 --- a/os/hal/ports/TIVA/LLD/mac_lld.h +++ b/os/hal/ports/TIVA/LLD/mac_lld.h @@ -262,6 +262,10 @@ #error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" #endif +#if !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_MAC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to MAC" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/pwm_lld.h b/os/hal/ports/TIVA/LLD/pwm_lld.h index 70ba97b..472bae8 100644 --- a/os/hal/ports/TIVA/LLD/pwm_lld.h +++ b/os/hal/ports/TIVA/LLD/pwm_lld.h @@ -154,52 +154,52 @@ #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 FAULT" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN0" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN1" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN2" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN3" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 FAULT" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN0" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN1" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN2" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN3" #endif diff --git a/os/hal/ports/TIVA/LLD/serial_lld.h b/os/hal/ports/TIVA/LLD/serial_lld.h index 5ba4645..535d0a5 100644 --- a/os/hal/ports/TIVA/LLD/serial_lld.h +++ b/os/hal/ports/TIVA/LLD/serial_lld.h @@ -341,42 +341,42 @@ #endif #if TIVA_SERIAL_USE_UART0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) #error "Invalid IRQ priority assigned to UART0" #endif #if TIVA_SERIAL_USE_UART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) #error "Invalid IRQ priority assigned to UART1" #endif #if TIVA_SERIAL_USE_UART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) #error "Invalid IRQ priority assigned to UART2" #endif #if TIVA_SERIAL_USE_UART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) #error "Invalid IRQ priority assigned to UART3" #endif #if TIVA_SERIAL_USE_UART4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) #error "Invalid IRQ priority assigned to UART4" #endif #if TIVA_SERIAL_USE_UART5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) #error "Invalid IRQ priority assigned to UART5" #endif #if TIVA_SERIAL_USE_UART6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) #error "Invalid IRQ priority assigned to UART6" #endif #if TIVA_SERIAL_USE_UART7 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) #error "Invalid IRQ priority assigned to UART7" #endif diff --git a/os/hal/ports/TIVA/LLD/spi_lld.h b/os/hal/ports/TIVA/LLD/spi_lld.h index c757a22..5c04d69 100644 --- a/os/hal/ports/TIVA/LLD/spi_lld.h +++ b/os/hal/ports/TIVA/LLD/spi_lld.h @@ -114,7 +114,7 @@ */ #define TIVA_DMACTL_RXDMAE (1 << 0) #define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -222,22 +222,22 @@ #endif #if TIVA_SPI_USE_SSI0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI0" #endif #if TIVA_SPI_USE_SSI1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI1" #endif #if TIVA_SPI_USE_SSI2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI2" #endif #if TM4C123x_SPI_USE_SSI3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif diff --git a/os/hal/ports/TIVA/LLD/st_lld.h b/os/hal/ports/TIVA/LLD/st_lld.h index bec1a36..23b3ef5 100644 --- a/os/hal/ports/TIVA/LLD/st_lld.h +++ b/os/hal/ports/TIVA/LLD/st_lld.h @@ -164,6 +164,11 @@ #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" #endif +#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ST" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index 72b53b4..5c2cd25 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -329,11 +329,6 @@ */ #define TIVA_SYSCLK (TIVA_SRC / (((TIVA_SYSDIV_VALUE << TIVA_DIV400_VALUE /*& TIVA_BYPASS_VALUE*/) | (TIVA_SYSDIV2LSB >> 22)) + 1)) -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SysTick" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0f54c5a..e808142 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -8,7 +8,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/gpt_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pwm_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/spi_lld.c \ - ${CHISIOS}/community/os/hal/ports/TIVA/LLD/tiva_udma.c + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/tiva_udma.c \ + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/ext_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h index 09a8c75..04786e0 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h @@ -98,6 +98,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 56 #endif #if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ @@ -122,6 +123,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 48 #endif #if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ @@ -146,6 +148,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 88 #endif #if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) @@ -167,6 +170,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 112 #endif #if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) #define TIVA_HAS_GPIOA TRUE @@ -187,6 +191,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 120 #endif /* GPTM attributes.*/ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index a0e769b..dc6644f 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -344,11 +344,6 @@ */ #define TIVA_SYSCLK 120000000 -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SysTick" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 35de5ce..97a5a73 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \ - ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c + ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c \ + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/ext_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c index fc0cf85..7c71e3f 100644 --- a/os/hal/src/hal_community.c +++ b/os/hal/src/hal_community.c @@ -1,20 +1,17 @@ /*
- ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+ ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
- This file is part of ChibiOS/HAL
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
- ChibiOS/HAL is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ http://www.apache.org/licenses/LICENSE-2.0
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
*/
/**
diff --git a/os/hal/src/nand.c b/os/hal/src/nand.c index 9135d1a..a621604 100644 --- a/os/hal/src/nand.c +++ b/os/hal/src/nand.c @@ -1,25 +1,18 @@ /* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - This file is part of ChibiOS/HAL + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/HAL is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ /** * @file nand.c @@ -62,7 +55,7 @@ * * @notapi */ -static void pagesize_check(size_t page_data_size){ +static void pagesize_check(size_t page_data_size) { /* Page size out of bounds.*/ osalDbgCheck((page_data_size >= NAND_MIN_PAGE_SIZE) && @@ -75,33 +68,32 @@ static void pagesize_check(size_t page_data_size){ /** * @brief Translate block-page-offset scheme to NAND internal address. * - * @param[in] cfg pointer to the @p NANDConfig from - * corresponding NAND driver - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] offset data offset related to begin of page - * @param[out] addr buffer to store calculated address - * @param[in] addr_len length of address buffer + * @param[in] cfg pointer to the @p NANDConfig from + * corresponding NAND driver + * @param[in] block block number + * @param[in] page page number related to begin of block + * @param[in] page_offset data offset related to begin of page + * @param[out] addr buffer to store calculated address + * @param[in] addr_len length of address buffer * * @notapi */ -static void calc_addr(const NANDConfig *cfg, - uint32_t block, uint32_t page, uint32_t offset, - uint8_t *addr, size_t addr_len){ +static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, + uint32_t page_offset, uint8_t *addr, size_t addr_len) { size_t i = 0; uint32_t row = 0; /* Incorrect buffer length.*/ osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len); osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) && - (offset < cfg->page_data_size + cfg->page_spare_size)); + (page_offset < cfg->page_data_size + cfg->page_spare_size)); /* convert address to NAND specific */ memset(addr, 0, addr_len); row = (block * cfg->pages_per_block) + page; for (i=0; i<cfg->colcycles; i++){ - addr[i] = offset & 0xFF; - offset = offset >> 8; + addr[i] = page_offset & 0xFF; + page_offset = page_offset >> 8; } for (; i<addr_len; i++){ addr[i] = row & 0xFF; @@ -121,8 +113,8 @@ static void calc_addr(const NANDConfig *cfg, * * @notapi */ -static void calc_blk_addr(const NANDConfig *cfg, - uint32_t block, uint8_t *addr, size_t addr_len){ +static void calc_blk_addr(const NANDConfig *cfg, uint32_t block, + uint8_t *addr, size_t addr_len) { size_t i = 0; uint32_t row = 0; @@ -139,59 +131,52 @@ static void calc_blk_addr(const NANDConfig *cfg, } } -#if NAND_USE_BAD_MAP /** - * @brief Add new bad block to map. + * @brief Read block badness mark directly from NAND memory array. * * @param[in] nandp pointer to the @p NANDDriver object * @param[in] block block number - * @param[in] map pointer to bad block map + * + * @return block condition + * @retval true if the block is bad. + * @retval false if the block is good. + * + * @notapi */ -static void bad_map_update(NANDDriver *nandp, size_t block) { +static bool read_is_block_bad(NANDDriver *nandp, size_t block) { - uint32_t *map = nandp->config->bb_map; - const size_t BPMC = sizeof(uint32_t) * 8; /* bits per map claster */ - size_t i; - size_t shift; - - /* Nand device overflow.*/ - osalDbgCheck(nandp->config->blocks > block); + if (0xFF != nandReadBadMark(nandp, block, 0)) + return true; + if (0xFF != nandReadBadMark(nandp, block, 1)) + return true; - i = block / BPMC; - shift = block % BPMC; - /* This block already mapped.*/ - osalDbgCheck(((map[i] >> shift) & 1) != 1); - map[i] |= (uint32_t)1 << shift; + return false; } /** * @brief Scan for bad blocks and fill map with their numbers. * * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi */ static void scan_bad_blocks(NANDDriver *nandp) { const size_t blocks = nandp->config->blocks; - const size_t maplen = blocks / 32; - size_t b; - uint8_t m0; - uint8_t m1; + + osalDbgCheck(bitmapGetBitsCount(nandp->bb_map) >= blocks); /* clear map just to be safe */ - for (b=0; b<maplen; b++) - nandp->config->bb_map[b] = 0; + bitmapObjectInit(nandp->bb_map, 0); /* now write numbers of bad block to map */ - for (b=0; b<blocks; b++){ - m0 = nandReadBadMark(nandp, b, 0); - m1 = nandReadBadMark(nandp, b, 1); - if ((0xFF != m0) || (0xFF != m1)){ - bad_map_update(nandp, b); + for (b=0; b<blocks; b++) { + if (read_is_block_bad(nandp, b)) { + bitmapSet(nandp->bb_map, b); } } } -#endif /* NAND_USE_BAD_MAP */ /*===========================================================================*/ /* Driver exported functions. */ @@ -235,10 +220,11 @@ void nandObjectInit(NANDDriver *nandp) { * * @param[in] nandp pointer to the @p NANDDriver object * @param[in] config pointer to the @p NANDConfig object + * @param[in] bb_map pointer to the bad block map or @NULL if not need * * @api */ -void nandStart(NANDDriver *nandp, const NANDConfig *config) { +void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map) { osalDbgCheck((nandp != NULL) && (config != NULL)); osalDbgAssert((nandp->state == NAND_STOP) || @@ -250,9 +236,10 @@ void nandStart(NANDDriver *nandp, const NANDConfig *config) { nand_lld_start(nandp); nandp->state = NAND_READY; -#if NAND_USE_BAD_MAP - scan_bad_blocks(nandp); -#endif /* NAND_USE_BAD_MAP */ + if (NULL != bb_map) { + nandp->bb_map = bb_map; + scan_bad_blocks(nandp); + } } /** @@ -283,8 +270,8 @@ void nandStop(NANDDriver *nandp) { * * @api */ -void nandReadPageWhole(NANDDriver *nandp, uint32_t block, - uint32_t page, uint8_t *data, size_t datalen) { +void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, + uint8_t *data, size_t datalen) { const NANDConfig *cfg = nandp->config; uint8_t addrbuf[8]; @@ -311,8 +298,8 @@ void nandReadPageWhole(NANDDriver *nandp, uint32_t block, * * @api */ -uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *data, size_t datalen) { +uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *data, size_t datalen) { uint8_t retval; const NANDConfig *cfg = nandp->config; @@ -369,8 +356,8 @@ void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, * * @api */ -uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *data, size_t datalen, uint32_t *ecc) { +uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *data, size_t datalen, uint32_t *ecc) { uint8_t retval; const NANDConfig *cfg = nandp->config; @@ -397,8 +384,8 @@ uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, * * @api */ -void nandReadPageSpare(NANDDriver *nandp, uint32_t block, - uint32_t page, uint8_t *spare, size_t sparelen) { +void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, + uint8_t *spare, size_t sparelen) { const NANDConfig *cfg = nandp->config; uint8_t addr[8]; @@ -425,8 +412,8 @@ void nandReadPageSpare(NANDDriver *nandp, uint32_t block, * * @api */ -uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, - uint32_t page, const uint8_t *spare, size_t sparelen) { +uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, + const uint8_t *spare, size_t sparelen) { uint8_t retVal; const NANDConfig *cfg = nandp->config; @@ -453,15 +440,12 @@ uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, void nandMarkBad(NANDDriver *nandp, uint32_t block) { uint8_t bb_mark[2] = {0, 0}; - uint8_t op_status; - op_status = nandWritePageSpare(nandp, block, 0, bb_mark, sizeof(bb_mark)); - osalDbgCheck(0 == (op_status & 1)); /* operation failed*/ - op_status = nandWritePageSpare(nandp, block, 1, bb_mark, sizeof(bb_mark)); - osalDbgCheck(0 == (op_status & 1)); /* operation failed*/ - -#if NAND_USE_BAD_MAP - bad_map_update(nandp, block); -#endif + + nandWritePageSpare(nandp, block, 0, bb_mark, sizeof(bb_mark)); + nandWritePageSpare(nandp, block, 1, bb_mark, sizeof(bb_mark)); + + if (NULL != nandp->bb_map) + bitmapSet(nandp->bb_map, block); } /** @@ -475,9 +459,9 @@ void nandMarkBad(NANDDriver *nandp, uint32_t block) { * * @api */ -uint8_t nandReadBadMark(NANDDriver *nandp, - uint32_t block, uint32_t page) { +uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) { uint8_t bb_mark[1]; + nandReadPageSpare(nandp, block, page, bb_mark, sizeof(bb_mark)); return bb_mark[0]; } @@ -492,7 +476,7 @@ uint8_t nandReadBadMark(NANDDriver *nandp, * * @api */ -uint8_t nandErase(NANDDriver *nandp, uint32_t block){ +uint8_t nandErase(NANDDriver *nandp, uint32_t block) { uint8_t retVal; const NANDConfig *cfg = nandp->config; @@ -508,7 +492,7 @@ uint8_t nandErase(NANDDriver *nandp, uint32_t block){ } /** - * @brief Report block badness. + * @brief Check block badness. * * @param[in] nandp pointer to the @p NANDDriver object * @param[in] block block number @@ -519,32 +503,15 @@ uint8_t nandErase(NANDDriver *nandp, uint32_t block){ * * @api */ -bool nandIsBad(NANDDriver *nandp, uint32_t block){ +bool nandIsBad(NANDDriver *nandp, uint32_t block) { osalDbgCheck(nandp != NULL); osalDbgAssert(nandp->state == NAND_READY, "invalid state"); -#if NAND_USE_BAD_MAP - uint32_t *map = nandp->config->bb_map; - const size_t BPMC = sizeof(uint32_t) * 8; /* bits per map claster */ - size_t i; - size_t shift; - - i = block / BPMC; - shift = block % BPMC; - if (((map[i] >> shift) & 1) == 1) - return true; - else - return false; -#else - uint8_t m0, m1; - m0 = nandReadBadMark(nandp, block, 0); - m1 = nandReadBadMark(nandp, block, 1); - if ((0xFF != m0) || (0xFF != m1)) - return true; + if (NULL != nandp->bb_map) + return 1 == bitmapGet(nandp->bb_map, block); else - return false; -#endif /* NAND_USE_BAD_MAP */ + return read_is_block_bad(nandp, block); } #if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk deleted file mode 100644 index bd76209..0000000 --- a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C123x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C123x \ - ${CHIBIOS}/os/nil/ports/ARMCMx \ - ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk deleted file mode 100644 index 7e55117..0000000 --- a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C129x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C129x \ - ${CHIBIOS}/os/nil/ports/ARMCMx \ - ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk deleted file mode 100644 index 470f42d..0000000 --- a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C123x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C123x \ - ${CHIBIOS}/os/rt/ports/ARMCMx \ - ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk deleted file mode 100644 index 0891b83..0000000 --- a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C129x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C129x \ - ${CHIBIOS}/os/rt/ports/ARMCMx \ - ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/various/bitmap.c b/os/various/bitmap.c new file mode 100644 index 0000000..a17dfcb --- /dev/null +++ b/os/various/bitmap.c @@ -0,0 +1,158 @@ +/* + ChibiOS/HAL - Copyright (C) 2015 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file bitmap.c + * @brief Bit map code. + * + * @addtogroup bitmap + * @{ + */ + +#include "string.h" /* for memset() */ + +#include "hal.h" +#include "bitmap.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/** + * @brief Get word number. + * + * @param[in] bit number of the bit + * + * @return Index of the word containing specified bit. + */ +static inline size_t word(size_t bit) { + return bit / (sizeof(bitmap_word_t) * 8); +} + +/** + * @brief Get bit position in word. + * + * @param[in] bit number of the bit + * + * @return Position of the specified bit related to word start. + */ +static inline size_t pos_in_word(size_t bit) { + return bit % (sizeof(bitmap_word_t) * 8); +} + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ +/** + * @brief Initializes an @p bitmap_t structure. + * + * @param[out] map the @p bitmap_t structure to be initialized + * @param[in] val the value to be written in all bitmap + */ +void bitmapObjectInit(bitmap_t *map, bitmap_word_t val) { + uint8_t pattern; + + osalDbgCheck(val == 1 || val == 0); + + if (val == 1) + pattern = 0xFF; + else + pattern = 0; + + memset(map->array, pattern, map->len*sizeof(bitmap_word_t)); +} + +/** + * @brief Set single bit in an @p bitmap_t structure. + * + * @param[out] map the @p bitmap_t structure + * @param[in] bit number of the bit to be set + */ +void bitmapSet(bitmap_t *map, size_t bit) { + size_t w = word(bit); + + osalDbgCheck(w < map->len); + map->array[w] |= (bitmap_word_t)1 << pos_in_word(bit); +} + +/** + * @brief Clear single bit in an @p bitmap_t structure. + * + * @param[out] map the @p bitmap_t structure + * @param[in] bit number of the bit to be cleared + */ +void bitmapClear(bitmap_t *map, size_t bit) { + size_t w = word(bit); + + osalDbgCheck(w < map->len); + map->array[w] &= ~((bitmap_word_t)1 << pos_in_word(bit)); +} + +/** + * @brief Invert single bit in an @p bitmap_t structure. + * + * @param[out] map the @p bitmap_t structure + * @param[in] bit number of the bit to be inverted + */ +void bitmapInvert(bitmap_t *map, size_t bit) { + size_t w = word(bit); + + osalDbgCheck(w < map->len); + map->array[w] ^= (bitmap_word_t)1 << pos_in_word(bit); +} + +/** + * @brief Get bit value from an @p bitmap_t structure. + * + * @param[in] map the @p bitmap_t structure + * @param[in] bit number of the requested bit + * + * @return Requested bit value. + */ +bitmap_word_t bitmapGet(const bitmap_t *map, size_t bit) { + size_t w = word(bit); + + osalDbgCheck(w < map->len); + return (map->array[w] >> pos_in_word(bit)) & 1; +} + +/** + * @brief Get total amount of bits in an @p bitmap_t structure. + * + * @param[in] map the @p bitmap_t structure + * + * @return Bit number. + */ +size_t bitmapGetBitsCount(const bitmap_t *map) { + return map->len * sizeof(bitmap_word_t) * 8; +} +/** @} */ diff --git a/os/various/bitmap.h b/os/various/bitmap.h new file mode 100644 index 0000000..d7831aa --- /dev/null +++ b/os/various/bitmap.h @@ -0,0 +1,77 @@ +/* + ChibiOS/HAL - Copyright (C) 2015 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file bitmap.h + * @brief Bit map structures and macros. + * + * @addtogroup bitmap + * @{ + */ + +#ifndef _BITMAP_H_ +#define _BITMAP_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +typedef unsigned int bitmap_word_t; + +/** + * @brief Type of a event timer structure. + */ +typedef struct { + bitmap_word_t *array; + size_t len; /* Array length in _words_ NOT bytes */ +} bitmap_t; + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void bitmapObjectInit(bitmap_t *map, bitmap_word_t val); + void bitmapSet(bitmap_t *map, size_t bit); + void bitmapClear(bitmap_t *map, size_t bit); + void bitmapInvert(bitmap_t *map, size_t bit); + bitmap_word_t bitmapGet(const bitmap_t *map, size_t bit); + size_t bitmapGetBitsCount(const bitmap_t *map); +#ifdef __cplusplus +} +#endif + +#endif /* _BITMAP_H_ */ + +/** @} */ diff --git a/os/various/devices_lib/lcd/ili9341.c b/os/various/devices_lib/lcd/ili9341.c new file mode 100644 index 0000000..979e502 --- /dev/null +++ b/os/various/devices_lib/lcd/ili9341.c @@ -0,0 +1,418 @@ +/* + Copyright (C) 2013-2015 Andrea Zoppi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ili9341.c + * @brief ILI9341 TFT LCD diaplay controller driver. + * @note Does not support multiple calling threads natively. + */ + +#include "ch.h" +#include "hal.h" +#include "ili9341.h" + +/** + * @addtogroup ili9341 + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if !ILI9341_USE_CHECKS && !defined(__DOXYGEN__) +/* Disable checks as needed.*/ + +#ifdef osalDbgCheck +#undef osalDbgCheck +#endif +#define osalDbgCheck(c, func) { \ + (void)(c), (void)__QUOTE_THIS(func)"()"; \ +} + +#ifdef osalDbgAssert +#undef osalDbgAssert +#endif +#define osalDbgAssert(c, m, r) { \ + (void)(c); \ +} + +#ifdef osalDbgCheckClassS +#undef osalDbgCheckClassS +#endif +#define osalDbgCheckClassS() {} + +#ifdef osalDbgCheckClassS +#undef osalDbgCheckClassS +#endif +#define osalDbgCheckClassI() {} + +#endif /* ILI9341_USE_CHECKS */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ILI9341D1 driver identifier.*/ +ILI9341Driver ILI9341D1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the standard part of a @p ILI9341Driver structure. + * + * @param[out] driverp pointer to the @p ILI9341Driver object + * + * @init + */ +void ili9341ObjectInit(ILI9341Driver *driverp) { + + osalDbgCheck(driverp != NULL); + + driverp->state = ILI9341_STOP; + driverp->config = NULL; +#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) +#if (TRUE == CH_CFG_USE_MUTEXES) + chMtxObjectInit(&driverp->lock); +#else + chSemObjectInit(&driverp->lock, 1); +#endif +#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */ +} + +/** + * @brief Configures and activates the ILI9341 peripheral. + * @pre ILI9341 is stopped. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * @param[in] configp pointer to the @p ILI9341Config object + * + * @api + */ +void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp) { + + chSysLock(); + osalDbgCheck(driverp != NULL); + osalDbgCheck(configp != NULL); + osalDbgCheck(configp->spi != NULL); + osalDbgAssert(driverp->state == ILI9341_STOP, "invalid state"); + + spiSelectI(configp->spi); + spiUnselectI(configp->spi); + driverp->config = configp; + driverp->state = ILI9341_READY; + chSysUnlock(); +} + +/** + * @brief Deactivates the ILI9341 peripheral. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @api + */ +void ili9341Stop(ILI9341Driver *driverp) { + + chSysLock(); + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_READY, "invalid state"); + + driverp->state = ILI9341_STOP; + chSysUnlock(); +} + +#if ILI9341_USE_MUTUAL_EXCLUSION + +/** + * @brief Gains exclusive access to the ILI9341 module. + * @details This function tries to gain ownership to the ILI9341 module, if the + * module is already being used then the invoking thread is queued. + * @pre In order to use this function the option + * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @sclass + */ +void ili9341AcquireBusS(ILI9341Driver *driverp) { + + osalDbgCheckClassS(); + osalDbgCheck(driverp == &ILI9341D1); + osalDbgAssert(driverp->state == ILI9341_READY, "not ready"); + +#if (TRUE == CH_CFG_USE_MUTEXES) + chMtxLockS(&driverp->lock); +#else + chSemWaitS(&driverp->lock); +#endif +} + +/** + * @brief Gains exclusive access to the ILI9341 module. + * @details This function tries to gain ownership to the ILI9341 module, if the + * module is already being used then the invoking thread is queued. + * @pre In order to use this function the option + * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @api + */ +void ili9341AcquireBus(ILI9341Driver *driverp) { + + chSysLock(); + ili9341AcquireBusS(driverp); + chSysUnlock(); +} + +/** + * @brief Releases exclusive access to the ILI9341 module. + * @pre In order to use this function the option + * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @sclass + */ +void ili9341ReleaseBusS(ILI9341Driver *driverp) { + + osalDbgCheckClassS(); + osalDbgCheck(driverp == &ILI9341D1); + osalDbgAssert(driverp->state == ILI9341_READY, "not ready"); + +#if (TRUE == CH_CFG_USE_MUTEXES) + chMtxUnlockS(&driverp->lock); +#else + chSemSignalI(&driverp->lock); +#endif +} + +/** + * @brief Releases exclusive access to the ILI9341 module. + * @pre In order to use this function the option + * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @api + */ +void ili9341ReleaseBus(ILI9341Driver *driverp) { + + chSysLock(); + ili9341ReleaseBusS(driverp); + chSysUnlock(); +} + +#endif /* ILI9341_USE_MUTUAL_EXCLUSION */ + +#if ILI9341_IM == ILI9341_IM_4LSI_1 /* 4-wire, half-duplex */ + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @iclass + */ +void ili9341SelectI(ILI9341Driver *driverp) { + + osalDbgCheckClassI(); + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_READY, "invalid state"); + + driverp->state = ILI9341_ACTIVE; + spiSelectI(driverp->config->spi); +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * @pre ILI9341 is ready. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @api + */ +void ili9341Select(ILI9341Driver *driverp) { + + chSysLock(); + ili9341SelectI(driverp); + chSysUnlock(); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * @pre ILI9341 is active. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @iclass + */ +void ili9341UnselectI(ILI9341Driver *driverp) { + + osalDbgCheckClassI(); + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + spiUnselectI(driverp->config->spi); + driverp->state = ILI9341_READY; +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * @pre ILI9341 is active. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @iclass + */ +void ili9341Unselect(ILI9341Driver *driverp) { + + chSysLock(); + ili9341UnselectI(driverp); + chSysUnlock(); +} + +/** + * @brief Write command byte. + * @details Sends a command byte via SPI. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * @param[in] cmd command byte + * + * @api + */ +void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd) { + + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + driverp->value = cmd; + palClearPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* !Cmd */ + spiSend(driverp->config->spi, 1, &driverp->value); +} + +/** + * @brief Write data byte. + * @details Sends a data byte via SPI. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * @param[in] value data byte + * + * @api + */ +void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value) { + + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + driverp->value = value; + palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ + spiSend(driverp->config->spi, 1, &driverp->value); +} + +/** + * @brief Read data byte. + * @details Receives a data byte via SPI. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * + * @return data byte + * + * @api + */ +uint8_t ili9341ReadByte(ILI9341Driver *driverp) { + + osalDbgAssert(FALSE, "should not be used"); + + osalDbgCheck(driverp != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ + spiReceive(driverp->config->spi, 1, &driverp->value); + return driverp->value; +} + +/** + * @brief Write data chunk. + * @details Sends a data chunk via SPI. + * @pre The chunk must be accessed by DMA. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * @param[in] chunk chunk bytes + * @param[in] length chunk length + * + * @api + */ +void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[], + size_t length) { + + osalDbgCheck(driverp != NULL); + osalDbgCheck(chunk != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + if (length != 0) { + palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ + spiSend(driverp->config->spi, length, chunk); + } +} + +/** + * @brief Read data chunk. + * @details Receives a data chunk via SPI. + * @pre The chunk must be accessed by DMA. + * + * @param[in] driverp pointer to the @p ILI9341Driver object + * @param[out] chunk chunk bytes + * @param[in] length chunk length + * + * @api + */ +void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[], + size_t length) { + + osalDbgCheck(driverp != NULL); + osalDbgCheck(chunk != NULL); + osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state"); + + if (length != 0) { + palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */ + spiReceive(driverp->config->spi, length, chunk); + } +} + +#else /* ILI9341_IM == * */ +#error "Only the ILI9341_IM_4LSI_1 interface mode is currently supported" +#endif /* ILI9341_IM == * */ + +/** @} */ diff --git a/os/various/devices_lib/lcd/ili9341.h b/os/various/devices_lib/lcd/ili9341.h new file mode 100644 index 0000000..007c4fd --- /dev/null +++ b/os/various/devices_lib/lcd/ili9341.h @@ -0,0 +1,593 @@ +/* + Copyright (C) 2013-2015 Andrea Zoppi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ili9341.h + * @brief ILI9341 TFT LCD diaplay controller driver. + */ + +#ifndef _ILI9341_H_ +#define _ILI9341_H_ + +/** + * @addtogroup ili9341 + * @{ + */ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ILI9341 regulative commands + * @{ + */ +#define ILI9341_CMD_NOP (0x00) /**< No operation.*/ +#define ILI9341_CMD_RESET (0x01) /**< Software reset.*/ +#define ILI9341_GET_ID_INFO (0x04) /**< Get ID information.*/ +#define ILI9341_GET_STATUS (0x09) /**< Get status.*/ +#define ILI9341_GET_PWR_MODE (0x0A) /**< Get power mode.*/ +#define ILI9341_GET_MADCTL (0x0B) /**< Get MADCTL.*/ +#define ILI9341_GET_PIX_FMT (0x0C) /**< Get pixel format.*/ +#define ILI9341_GET_IMG_FMT (0x0D) /**< Get image format.*/ +#define ILI9341_GET_SIG_MODE (0x0E) /**< Get signal mode.*/ +#define ILI9341_GET_SELF_DIAG (0x0F) /**< Get self-diagnostics.*/ +#define ILI9341_CMD_SLEEP_ON (0x10) /**< Enter sleep mode.*/ +#define ILI9341_CMD_SLEEP_OFF (0x11) /**< Exist sleep mode.*/ +#define ILI9341_CMD_PARTIAL_ON (0x12) /**< Enter partial mode.*/ +#define ILI9341_CMD_PARTIAL_OFF (0x13) /**< Exit partial mode.*/ +#define ILI9341_CMD_INVERT_ON (0x20) /**< Enter inverted mode.*/ +#define ILI9341_CMD_INVERT_OFF (0x21) /**< Exit inverted mode.*/ +#define ILI9341_SET_GAMMA (0x26) /**< Set gamma params.*/ +#define ILI9341_CMD_DISPLAY_OFF (0x28) /**< Disable display.*/ +#define ILI9341_CMD_DISPLAY_ON (0x29) /**< Enable display.*/ +#define ILI9341_SET_COL_ADDR (0x2A) /**< Set column address.*/ +#define ILI9341_SET_PAGE_ADDR (0x2B) /**< Set page address.*/ +#define ILI9341_SET_MEM (0x2C) /**< Set memory.*/ +#define ILI9341_SET_COLOR (0x2D) /**< Set color.*/ +#define ILI9341_GET_MEM (0x2E) /**< Get memory.*/ +#define ILI9341_SET_PARTIAL_AREA (0x30) /**< Set partial area.*/ +#define ILI9341_SET_VSCROLL (0x33) /**< Set vertical scroll def.*/ +#define ILI9341_CMD_TEARING_ON (0x34) /**< Tearing line enabled.*/ +#define ILI9341_CMD_TEARING_OFF (0x35) /**< Tearing line disabled.*/ +#define ILI9341_SET_MEM_ACS_CTL (0x36) /**< Set mem access ctl.*/ +#define ILI9341_SET_VSCROLL_ADDR (0x37) /**< Set vscroll start addr.*/ +#define ILI9341_CMD_IDLE_OFF (0x38) /**< Exit idle mode.*/ +#define ILI9341_CMD_IDLE_ON (0x39) /**< Enter idle mode.*/ +#define ILI9341_SET_PIX_FMT (0x3A) /**< Set pixel format.*/ +#define ILI9341_SET_MEM_CONT (0x3C) /**< Set memory continue.*/ +#define ILI9341_GET_MEM_CONT (0x3E) /**< Get memory continue.*/ +#define ILI9341_SET_TEAR_SCANLINE (0x44) /**< Set tearing scanline.*/ +#define ILI9341_GET_TEAR_SCANLINE (0x45) /**< Get tearing scanline.*/ +#define ILI9341_SET_BRIGHTNESS (0x51) /**< Set brightness.*/ +#define ILI9341_GET_BRIGHTNESS (0x52) /**< Get brightness.*/ +#define ILI9341_SET_DISPLAY_CTL (0x53) /**< Set display ctl.*/ +#define ILI9341_GET_DISPLAY_CTL (0x54) /**< Get display ctl.*/ +#define ILI9341_SET_CABC (0x55) /**< Set CABC.*/ +#define ILI9341_GET_CABC (0x56) /**< Get CABC.*/ +#define ILI9341_SET_CABC_MIN (0x5E) /**< Set CABC min.*/ +#define ILI9341_GET_CABC_MIN (0x5F) /**< Set CABC max.*/ +#define ILI9341_GET_ID1 (0xDA) /**< Get ID1.*/ +#define ILI9341_GET_ID2 (0xDB) /**< Get ID2.*/ +#define ILI9341_GET_ID3 (0xDC) /**< Get ID3.*/ +/** @} */ + +/** + * @name ILI9341 extended commands + * @{ + */ +#define ILI9341_SET_RGB_IF_SIG_CTL (0xB0) /**< RGB IF signal ctl.*/ +#define ILI9341_SET_FRAME_CTL_NORMAL (0xB1) /**< Set frame ctl (normal).*/ +#define ILI9341_SET_FRAME_CTL_IDLE (0xB2) /**< Set frame ctl (idle).*/ +#define ILI9341_SET_FRAME_CTL_PARTIAL (0xB3) /**< Set frame ctl (partial).*/ +#define ILI9341_SET_INVERSION_CTL (0xB4) /**< Set inversion ctl.*/ +#define ILI9341_SET_BLANKING_PORCH_CTL (0xB5) /**< Set blanking porch ctl.*/ +#define ILI9341_SET_FUNCTION_CTL (0xB6) /**< Set function ctl.*/ +#define ILI9341_SET_ENTRY_MODE (0xB7) /**< Set entry mode.*/ +#define ILI9341_SET_LIGHT_CTL_1 (0xB8) /**< Set backlight ctl 1.*/ +#define ILI9341_SET_LIGHT_CTL_2 (0xB9) /**< Set backlight ctl 2.*/ +#define ILI9341_SET_LIGHT_CTL_3 (0xBA) /**< Set backlight ctl 3.*/ +#define ILI9341_SET_LIGHT_CTL_4 (0xBB) /**< Set backlight ctl 4.*/ +#define ILI9341_SET_LIGHT_CTL_5 (0xBC) /**< Set backlight ctl 5.*/ +#define ILI9341_SET_LIGHT_CTL_7 (0xBE) /**< Set backlight ctl 7.*/ +#define ILI9341_SET_LIGHT_CTL_8 (0xBF) /**< Set backlight ctl 8.*/ +#define ILI9341_SET_POWER_CTL_1 (0xC0) /**< Set power ctl 1.*/ +#define ILI9341_SET_POWER_CTL_2 (0xC1) /**< Set power ctl 2.*/ +#define ILI9341_SET_VCOM_CTL_1 (0xC5) /**< Set VCOM ctl 1.*/ +#define ILI9341_SET_VCOM_CTL_2 (0xC6) /**< Set VCOM ctl 2.*/ +#define ILI9341_SET_NVMEM (0xD0) /**< Set NVMEM data.*/ +#define ILI9341_GET_NVMEM_KEY (0xD1) /**< Get NVMEM protect key.*/ +#define ILI9341_GET_NVMEM_STATUS (0xD2) /**< Get NVMEM status.*/ +#define ILI9341_GET_ID4 (0xD3) /**< Get ID4.*/ +#define ILI9341_SET_PGAMMA (0xE0) /**< Set positive gamma.*/ +#define ILI9341_SET_NGAMMA (0xE1) /**< Set negative gamma.*/ +#define ILI9341_SET_DGAMMA_CTL_1 (0xE2) /**< Set digital gamma ctl 1.*/ +#define ILI9341_SET_DGAMMA_CTL_2 (0xE3) /**< Set digital gamma ctl 2.*/ +#define ILI9341_SET_IF_CTL (0xF6) /**< Set interface control.*/ +/** @} */ + +/** + * @name ILI9341 interface modes + * @{ + */ +#define ILI9341_IM_3LSI_1 (0x5) /**< 3-line serial, mode 1.*/ +#define ILI9341_IM_3LSI_2 (0xD) /**< 3-line serial, mode 2.*/ +#define ILI9341_IM_4LSI_1 (0x6) /**< 4-line serial, mode 1.*/ +#define ILI9341_IM_4LSI_2 (0xE) /**< 4-line serial, mode 2.*/ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name ILI9341 configuration options + * @{ + */ + +/** + * @brief Enables the @p ili9341AcquireBus() and @p ili9341ReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ILI9341_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ILI9341_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief ILI9341 Interface Mode. + */ +#if !defined(ILI9341_IM) || defined(__DOXYGEN__) +#define ILI9341_IM (ILI9341_IM_4LSI_1) +#endif + +/** + * @brief Enables checks for ILI9341 functions. + * @note Disabling this option saves both code and data space. + * @note Disabling checks by ChibiOS will automatically disable ILI9341 + * checks. + */ +#if !defined(ILI9341_USE_CHECKS) || defined(__DOXYGEN__) +#define ILI9341_USE_CHECKS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if ((TRUE == ILI9341_USE_MUTUAL_EXCLUSION) && \ + (TRUE != CH_CFG_USE_MUTEXES) && \ + (TRUE != CH_CFG_USE_SEMAPHORES)) +#error "ILI9341_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" +#endif + +/* TODO: Add the remaining modes.*/ +#if (ILI9341_IM != ILI9341_IM_4LSI_1) +#error "Only ILI9341_IM_4LSI_1 interface mode is supported currently" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/* Complex types forwarding.*/ +typedef struct ILI9341Config ILI9341Config; +typedef enum ili9341state_t ili9341state_t; +typedef struct ILI9341Driver ILI9341Driver; + +/** + * @brief ILI9341 driver configuration. + */ +typedef struct ILI9341Config { + SPIDriver *spi; /**< SPI driver used by ILI9341.*/ +#if (ILI9341_IM == ILI9341_IM_4LSI_1) + ioportid_t dcx_port; /**< <tt>D/!C</tt> signal port.*/ + uint16_t dcx_pad; /**< <tt>D/!C</tt> signal pad.*/ +#endif /* ILI9341_IM == * */ /* TODO: Add all modes.*/ +} ILI9341Config; + +/** + * @brief ILI9341 driver state. + */ +typedef enum ili9341state_t { + ILI9341_UNINIT = (0), /**< Not initialized.*/ + ILI9341_STOP = (1), /**< Stopped.*/ + ILI9341_READY = (2), /**< Ready.*/ + ILI9341_ACTIVE = (3), /**< Exchanging data.*/ +} ili9341state_t; + +/** + * @brief ILI9341 driver. + */ +typedef struct ILI9341Driver { + ili9341state_t state; /**< Driver state.*/ + const ILI9341Config *config; /**< Driver configuration.*/ + + /* Multithreading stuff.*/ +#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) +#if (TRUE == CH_CFG_USE_MUTEXES) + mutex_t lock; /**< Multithreading lock.*/ +#elif (TRUE == CH_CFG_USE_SEMAPHORES) + semaphore_t lock; /**< Multithreading lock.*/ +#endif +#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */ + + /* Temporary variables.*/ + uint8_t value; /**< Non-stacked value, for SPI with CCM.*/ +} ILI9341Driver; + +/** + * @name ILI9341 command params (little endian) + * @{ + */ +#pragma pack(push, 1) + +typedef union { + struct ILI9341ParamBits_GET_ID_INFO { + uint8_t reserved_; + uint8_t ID1; + uint8_t ID2; + uint8_t ID3; + } bits; + uint8_t bytes[4]; +} ILI9341Params_GET_ID_INFO; + +typedef union { + struct ILI9341ParamBits_GET_STATUS { + unsigned _reserved_1 : 5; /* D[ 4: 0] */ + unsigned tearing_mode : 1; /* D[ 5] */ + unsigned gamma_curve : 3; /* D[ 8: 6] */ + unsigned tearing : 1; /* D[ 9] */ + unsigned display : 1; /* D[10] */ + unsigned all_on : 1; /* D[11] */ + unsigned all_off : 1; /* D[12] */ + unsigned invert : 1; /* D[13] */ + unsigned _reserved_2 : 1; /* D[14] */ + unsigned vscroll : 1; /* D[15] */ + unsigned normal : 1; /* D[16] */ + unsigned sleep : 1; /* D[17] */ + unsigned partial : 1; /* D[18] */ + unsigned idle : 1; /* D[19] */ + unsigned pixel_format : 3; /* D[22:20] */ + unsigned _reserved_3 : 2; /* D[24:23] */ + unsigned hrefr_rtl_nltr : 1; /* D[25] */ + unsigned bgr_nrgb : 1; /* D[26] */ + unsigned vrefr_btt_nttb : 1; /* D[27] */ + unsigned transpose : 1; /* D[28] */ + unsigned coladr_rtl_nltr : 1; /* D[29] */ + unsigned rowadr_btt_nttb : 1; /* D[30] */ + unsigned booster : 1; /* D[31] */ + } bits; + uint8_t bytes[4]; +} ILI9341Params_GET_STATUS; + +typedef union { + struct ILI9341ParamBits_GET_PWR_MODE { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned display : 1; /* D[2] */ + unsigned normal : 1; /* D[3] */ + unsigned sleep : 1; /* D[4] */ + unsigned partial : 1; /* D[5] */ + unsigned idle : 1; /* D[6] */ + unsigned booster : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_PWR_MODE; + +typedef union { + struct ILI9341ParamBits_GET_MADCTL { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned refr_rtl_nltr : 1; /* D[2] */ + unsigned bgr_nrgb : 1; /* D[3] */ + unsigned refr_btt_nttb : 1; /* D[4] */ + unsigned invert : 1; /* D[5] */ + unsigned rtl_nltr : 1; /* D[6] */ + unsigned btt_nttb : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_MADCTL; + +typedef union { + struct ILI9341ParamBits_GET_PIX_FMT { + unsigned DBI : 3; /* D[2:0] */ + unsigned _reserved_1 : 1; /* D[3] */ + unsigned DPI : 3; /* D[6:4] */ + unsigned RIM : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_PIX_FMT; + +typedef union { + struct ILI9341ParamBits_GET_IMG_FMT { + unsigned gamma_curve : 3; /* D[2:0] */ + unsigned _reserved_1 : 5; /* D[7:3] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_IMG_FMT; + +typedef union { + struct ILI9341ParamBits_GET_SIG_MODE { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned data_enable : 1; /* D[2] */ + unsigned pixel_clock : 1; /* D[3] */ + unsigned vsync : 1; /* D[4] */ + unsigned hsync : 1; /* D[5] */ + unsigned tearing_mode : 1; /* D[6] */ + unsigned tearing : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_SIG_MODE; + +typedef union { + struct ILI9341ParamBits_GET_SELF_DIAG { + unsigned _reserved_1 : 6; /* D[5:0] */ + unsigned func_err : 1; /* D[6] */ + unsigned reg_err : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_SELF_DIAG; + +typedef union { + struct ILI9341ParamBits_SET_GAMMA { + uint8_t gamma_curve; /* D[7:0] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_GAMMA; + +typedef union { + struct ILI9341ParamBits_SET_COL_ADDR { + uint8_t SC_15_8; /* D[ 7: 0] */ + uint8_t SC_7_0; /* D[15: 8] */ + uint8_t EC_15_8; /* D[23:16] */ + uint8_t EC_7_0; /* D[31:24] */ + } bits; + uint8_t bytes[4]; +} ILI9341Params_SET_COL_ADDR; + +typedef union { + struct ILI9341ParamBits_SET_PAGE_ADDR { + uint8_t SP_15_8; /* D[ 7: 0] */ + uint8_t SP_7_0; /* D[15: 8] */ + uint8_t EP_15_8; /* D[23:16] */ + uint8_t EP_7_0; /* D[31:24] */ + } bits; + uint8_t bytes[4]; +} ILI9341Params_SET_PAGE_ADDR; + +typedef union { + struct ILI9341ParamBits_SET_PARTIAL_AREA { + uint8_t SR_15_8; /* D[ 7: 0] */ + uint8_t SR_7_0; /* D[15: 8] */ + uint8_t ER_15_8; /* D[23:16] */ + uint8_t ER_7_0; /* D[31:24] */ + } bits; + uint8_t bytes[4]; +} ILI9341Params_SET_PARTIAL_AREA; + +typedef union { + struct ILI9341ParamBits_SET_VSCROLL { + uint8_t TFA_15_8; /* D[ 7: 0] */ + uint8_t TFA_7_0; /* D[15: 8] */ + uint8_t VSA_15_8; /* D[23:16] */ + uint8_t VSA_7_0; /* D[31:24] */ + uint8_t BFA_15_8; /* D[39:32] */ + uint8_t BFA_7_0; /* D[47:40] */ + } bits; + uint8_t bytes[6]; +} ILI9341Params_SET_VSCROLL; + +typedef union { + struct ILI9341ParamBits_CMD_TEARING_ON { + unsigned M : 1; /* D[0] */ + unsigned _reserved_1 : 7; /* D[7:1] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_CMD_TEARING_ON; + +typedef union { + struct ILI9341ParamBits_SET_MEM_ACS_CTL { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned MH : 1; /* D[2] */ + unsigned BGR : 1; /* D[3] */ + unsigned ML : 1; /* D[4] */ + unsigned MV : 1; /* D[5] */ + unsigned MX : 1; /* D[6] */ + unsigned MY : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_MEM_ACS_CTL; + +typedef union { + struct ILI9341ParamBits_SET_VSCROLL_ADDR { + uint8_t VSP_15_8; /* D[ 7: 0] */ + uint8_t VSP_7_0; /* D[15: 8] */ + } bits; + uint8_t bytes[2]; +} ILI9341Params_SET_VSCROLL_ADDR; + +typedef union { + struct ILI9341ParamBits_SET_PIX_FMT { + unsigned DBI : 3; /* D[2:0] */ + unsigned _reserved_1 : 1; /* D[3] */ + unsigned DPI : 3; /* D[4:6] */ + unsigned _reserved_2 : 1; /* D[7] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_PIX_FMT; + +typedef union { + struct ILI9341ParamBits_SET_TEAR_SCANLINE { + uint8_t STS_8; /* D[ 7: 0] */ + uint8_t STS_7_0; /* D[15: 8] */ + } bits; + uint8_t bytes[4]; +} ILI9341Params_SET_TEAR_SCANLINE; + +typedef union { + struct ILI9341ParamBits_GET_TEAR_SCANLINE { + uint8_t GTS_9_8; /* D[ 7: 0] */ + uint8_t GTS_7_0; /* D[15: 8] */ + } bits; + uint8_t bytes[2]; +} ILI9341Params_GET_TEAR_SCANLINE; + +typedef union { + struct ILI9341ParamBits_SET_BRIGHTNESS { + uint8_t DBV; /* D[7:0] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_BRIGHTNESS; + +typedef union { + struct ILI9341ParamBits_GET_BRIGHTNESS { + uint8_t DBV; /* D[7:0] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_BRIGHTNESS; + +typedef union { + struct ILI9341ParamBits_SET_DISPLAY_CTL { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned BL : 1; /* D[2] */ + unsigned DD : 1; /* D[3] */ + unsigned _reserved_2 : 1; /* D[4] */ + unsigned BCTRL : 1; /* D[5] */ + unsigned _reserved_3 : 1; /* D[7:6] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_DISPLAY_CTL; + +typedef union { + struct ILI9341ParamBits_GET_DISPLAY_CTL { + unsigned _reserved_1 : 2; /* D[1:0] */ + unsigned BL : 1; /* D[2] */ + unsigned DD : 1; /* D[3] */ + unsigned _reserved_2 : 1; /* D[4] */ + unsigned BCTRL : 1; /* D[5] */ + unsigned _reserved_3 : 1; /* D[7:6] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_DISPLAY_CTL; + +typedef union { + struct ILI9341ParamBits_SET_CABC { + unsigned C : 2; /* D[1:0] */ + unsigned _reserved_1 : 6; /* D[7:2] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_CABC; + +typedef union { + struct ILI9341ParamBits_GET_CABC { + unsigned C : 2; /* D[1:0] */ + unsigned _reserved_1 : 6; /* D[7:2] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_CABC; + +typedef union { + struct ILI9341ParamBits_SET_CABC_MIN { + uint8_t CMB; /* D[7:0] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_SET_CABC_MIN; + +typedef union { + struct ILI9341ParamBits_GET_CABC_MIN { + uint8_t CMB; /* D[7:0] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_GET_CABC_MIN; + +#if 0 /* TODO: Extended command structs.*/ + +typedef union { + struct ILI9341ParamBits { + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_; + +typedef union { + struct ILI9341ParamBits { + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + unsigned : 1; /* D[] */ + } bits; + uint8_t bytes[1]; +} ILI9341Params_; + +#endif /*0*/ + +#pragma pack(pop) + +/** @} */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern ILI9341Driver ILI9341D1; + +#ifdef __cplusplus +extern "C" { +#endif + + void ili9341ObjectInit(ILI9341Driver *driverp); + void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp); + void ili9341Stop(ILI9341Driver *driverp); +#if (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) + void ili9341AcquireBusS(ILI9341Driver *driverp); + void ili9341AcquireBus(ILI9341Driver *driverp); + void ili9341ReleaseBusS(ILI9341Driver *driverp); + void ili9341ReleaseBus(ILI9341Driver *driverp); +#endif /* (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) */ + void ili9341SelectI(ILI9341Driver *driverp); + void ili9341Select(ILI9341Driver *driverp); + void ili9341UnselectI(ILI9341Driver *driverp); + void ili9341Unselect(ILI9341Driver *driverp); + void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd); + void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value); + uint8_t ili9341ReadByte(ILI9341Driver *driverp); + void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[], + size_t length); + void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[], + size_t length); + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* _ILI9341_H_ */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.cpp b/os/various/memtest.cpp index 1be98a2..49828ec 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.cpp +++ b/os/various/memtest.cpp @@ -1,3 +1,19 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + #include <stdint.h> #include <stddef.h> #include <stdlib.h> @@ -12,6 +28,7 @@ class Generator { public: Generator(void) : pattern(0) {;} virtual T get(void) = 0; + virtual testtype get_type(void) = 0; virtual void init(T seed) { pattern = seed; } @@ -33,6 +50,10 @@ class GeneratorWalkingOne : public Generator<T> { return ret; } + + testtype get_type(void) { + return MEMTEST_WALKING_ONE; + } }; /* @@ -49,6 +70,10 @@ class GeneratorWalkingZero : public Generator<T> { return ret; } + + testtype get_type(void) { + return MEMTEST_WALKING_ZERO; + } }; /* @@ -61,6 +86,10 @@ class GeneratorOwnAddress : public Generator<T> { this->pattern++; return ret; } + + testtype get_type(void) { + return MEMTEST_OWN_ADDRESS; + } }; /* @@ -73,6 +102,13 @@ class GeneratorMovingInv : public Generator<T> { this->pattern = ~this->pattern; return ret; } + + testtype get_type(void) { + if ((this->pattern == 0) || ((this->pattern & 0xFF) == 0xFF)) + return MEMTEST_MOVING_INVERSION_ZERO; + else + return MEMTEST_MOVING_INVERSION_55AA; + } }; /* @@ -103,6 +139,10 @@ public: return ret; } + testtype get_type(void) { + return MEMTEST_MOVING_INVERSION_RAND; + } + private: size_t step; T prev; @@ -112,10 +152,10 @@ private: * */ template <typename T> -static void memtest_sequential(memtest_t *memp, Generator<T> &generator, T seed) { - const size_t steps = memp->size / sizeof(T); +static void memtest_sequential(memtest_t *testp, Generator<T> &generator, T seed) { + const size_t steps = testp->size / sizeof(T); size_t i; - T *mem = static_cast<T *>(memp->start); + T *mem = static_cast<T *>(testp->start); /* fill ram */ generator.init(seed); @@ -126,72 +166,72 @@ static void memtest_sequential(memtest_t *memp, Generator<T> &generator, T seed) generator.init(seed); for (i=0; i<steps; i++) { if (mem[i] != generator.get()) { - memp->ecb(memp, MEMTEST_WALKING_ONE, i*sizeof(T)); + testp->ecb(testp, generator.get_type(), i*sizeof(T)); return; } } } template <typename T> -static void walking_one(memtest_t *memp) { +static void walking_one(memtest_t *testp) { GeneratorWalkingOne<T> generator; - memtest_sequential<T>(memp, generator, 1); + memtest_sequential<T>(testp, generator, 1); } template <typename T> -static void walking_zero(memtest_t *memp) { +static void walking_zero(memtest_t *testp) { GeneratorWalkingZero<T> generator; - memtest_sequential<T>(memp, generator, 1); + memtest_sequential<T>(testp, generator, 1); } template <typename T> -static void own_address(memtest_t *memp) { +static void own_address(memtest_t *testp) { GeneratorOwnAddress<T> generator; - memtest_sequential<T>(memp, generator, 0); + memtest_sequential<T>(testp, generator, 0); } template <typename T> -static void moving_inversion_zero(memtest_t *memp) { +static void moving_inversion_zero(memtest_t *testp) { GeneratorMovingInv<T> generator; T mask = -1; - memtest_sequential<T>(memp, generator, 0); - memtest_sequential<T>(memp, generator, 0xFFFFFFFF & mask); + memtest_sequential<T>(testp, generator, 0); + memtest_sequential<T>(testp, generator, 0xFFFFFFFF & mask); } template <typename T> -static void moving_inversion_55aa(memtest_t *memp) { +static void moving_inversion_55aa(memtest_t *testp) { GeneratorMovingInv<T> generator; T mask = -1; - memtest_sequential<T>(memp, generator, 0x55555555 & mask); - memtest_sequential<T>(memp, generator, 0xAAAAAAAA & mask); + memtest_sequential<T>(testp, generator, 0x55555555 & mask); + memtest_sequential<T>(testp, generator, 0xAAAAAAAA & mask); } template <typename T> -static void moving_inversion_rand(memtest_t *memp) { +static void moving_inversion_rand(memtest_t *testp) { GeneratorMovingInvRand<T> generator; T mask = -1; - memtest_sequential<T>(memp, generator, memp->rand_seed & mask); + memtest_sequential<T>(testp, generator, testp->rand_seed & mask); } /* * */ -static void memtest_wrapper(memtest_t *memp, - void (*p_u8)(memtest_t *memp), - void (*p_u16)(memtest_t *memp), - void (*p_u32)(memtest_t *memp)) { - switch(memp->width){ +static void memtest_wrapper(memtest_t *testp, + void (*p_u8)(memtest_t *testp), + void (*p_u16)(memtest_t *testp), + void (*p_u32)(memtest_t *testp)) { + switch(testp->width) { case MEMTEST_WIDTH_32: - p_u8(memp); - p_u16(memp); - p_u32(memp); + p_u8(testp); + p_u16(testp); + p_u32(testp); break; case MEMTEST_WIDTH_16: - p_u8(memp); - p_u16(memp); + p_u8(testp); + p_u16(testp); break; case MEMTEST_WIDTH_8: - p_u8(memp); + p_u8(testp); break; } } @@ -199,45 +239,45 @@ static void memtest_wrapper(memtest_t *memp, /* * */ -void memtest_run(memtest_t *memp, uint32_t testmask) { +void memtest_run(memtest_t *testp, uint32_t testmask) { - if ((testmask & MEMTEST_WALKING_ONE) == MEMTEST_WALKING_ONE) { - memtest_wrapper(memp, + if (testmask & MEMTEST_WALKING_ONE) { + memtest_wrapper(testp, walking_one<uint8_t>, walking_one<uint16_t>, walking_one<uint32_t>); } - if ((testmask & MEMTEST_WALKING_ZERO) == MEMTEST_WALKING_ZERO) { - memtest_wrapper(memp, + if (testmask & MEMTEST_WALKING_ZERO) { + memtest_wrapper(testp, walking_zero<uint8_t>, walking_zero<uint16_t>, walking_zero<uint32_t>); } - if ((testmask & MEMTEST_OWN_ADDRESS) == MEMTEST_OWN_ADDRESS) { - memtest_wrapper(memp, + if (testmask & MEMTEST_OWN_ADDRESS) { + memtest_wrapper(testp, own_address<uint8_t>, own_address<uint16_t>, own_address<uint32_t>); } - if ((testmask & MEMTEST_MOVING_INVERSION_ZERO) == MEMTEST_MOVING_INVERSION_ZERO) { - memtest_wrapper(memp, + if (testmask & MEMTEST_MOVING_INVERSION_ZERO) { + memtest_wrapper(testp, moving_inversion_zero<uint8_t>, moving_inversion_zero<uint16_t>, moving_inversion_zero<uint32_t>); } - if ((testmask & MEMTEST_MOVING_INVERSION_55AA) == MEMTEST_MOVING_INVERSION_55AA) { - memtest_wrapper(memp, + if (testmask & MEMTEST_MOVING_INVERSION_55AA) { + memtest_wrapper(testp, moving_inversion_55aa<uint8_t>, moving_inversion_55aa<uint16_t>, moving_inversion_55aa<uint32_t>); } - if ((testmask & MEMTEST_MOVING_INVERSION_RAND) == MEMTEST_MOVING_INVERSION_RAND) { - memtest_wrapper(memp, + if (testmask & MEMTEST_MOVING_INVERSION_RAND) { + memtest_wrapper(testp, moving_inversion_rand<uint8_t>, moving_inversion_rand<uint16_t>, moving_inversion_rand<uint32_t>); diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.hpp b/os/various/memtest.hpp index 4a9e4e3..200db1f 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.hpp +++ b/os/various/memtest.hpp @@ -1,3 +1,19 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + #ifndef MEMTEST_HPP_ #define MEMTEST_HPP_ @@ -8,20 +24,20 @@ #define MEMTEST_MOVING_INVERSION_55AA (1 << 4) #define MEMTEST_MOVING_INVERSION_RAND (1 << 5) -#define MEMTEST_RUN_ALL (MEMTEST_WALKING_ONE | \ - MEMTEST_WALKING_ZERO | \ - MEMTEST_OWN_ADDRESS | \ - MEMTEST_MOVING_INVERSION_ZERO | \ - MEMTEST_MOVING_INVERSION_55AA | \ +#define MEMTEST_RUN_ALL (MEMTEST_WALKING_ONE | \ + MEMTEST_WALKING_ZERO | \ + MEMTEST_OWN_ADDRESS | \ + MEMTEST_MOVING_INVERSION_ZERO | \ + MEMTEST_MOVING_INVERSION_55AA | \ MEMTEST_MOVING_INVERSION_RAND) typedef struct memtest_t memtest_t; -typedef uint32_t testtype_t; +typedef uint32_t testtype; /* * Error call back. */ -typedef void (*memtestecb_t)(memtest_t *memp, testtype_t e, size_t address); +typedef void (*memtestecb_t)(memtest_t *testp, testtype type, size_t address); /* * @@ -49,7 +65,7 @@ struct memtest_t { #ifdef __cplusplus extern "C" { #endif - void memtest_run(memtest_t *memp, uint32_t testmask); + void memtest_run(memtest_t *testp, uint32_t testmask); #ifdef __cplusplus } #endif diff --git a/os/various/tribuf.c b/os/various/tribuf.c new file mode 100644 index 0000000..80eb258 --- /dev/null +++ b/os/various/tribuf.c @@ -0,0 +1,214 @@ +/*
+ Copyright (C) 2014..2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "osal.h"
+#include "tribuf.h"
+
+/**
+ * @file tribuf.c
+ * @brief Triple buffer handler source.
+ *
+ * @addtogroup TriBuf
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the tribuf handler object.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @param[in] front Pointer to the initial front buffer.
+ * @param[in] back Pointer to the initial back buffer.
+ * @param[in] orphan Pointer to the initial orphan buffer.
+ *
+ * @init
+ */
+void tribufObjectInit(tribuf_t *handler, void *front, void *back, void *orphan) {
+
+ handler->front = front;
+ handler->back = back;
+ handler->orphan = orphan;
+#if (TRIBUF_USE_WAIT == TRUE)
+ chSemObjectInit(&handler->ready, (cnt_t)0);
+#else
+ handler->ready = false;
+#endif
+}
+
+/**
+ * @brief Gets the current front buffer.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Pointer to the current front buffer.
+ *
+ * @api
+ */
+void *tribufGetFront(tribuf_t *handler) {
+
+ void *front;
+
+ osalSysLock();
+ front = tribufGetFrontI(handler);
+ osalSysUnlock();
+ return front;
+}
+
+/**
+ * @brief Swaps the current front buffer.
+ *
+ * @details Exchanges the pointer of the current front buffer, which will be
+ * dismissed, with the pointer of the current orphan buffer, which
+ * holds the content of the new front buffer.
+ *
+ * @pre The orphan buffer holds new data, swapped by the back buffer.
+ * @pre The fron buffer is ready for swap.
+ * @post The orphan buffer can be used as new back buffer in the future.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ *
+ * @iclass
+ */
+void tribufSwapFrontI(tribuf_t *handler) {
+
+ void *front;
+
+ osalDbgCheckClassI();
+
+ front = handler->orphan;
+ handler->orphan = handler->front;
+ handler->front = front;
+}
+
+/**
+ * @brief Swaps the current front buffer.
+ *
+ * @details Exchanges the pointer of the current front buffer, which will be
+ * dismissed, with the pointer of the current orphan buffer, which
+ * holds the content of the new front buffer.
+ *
+ * @pre The orphan buffer holds new data, swapped by the back buffer.
+ * @pre The fron buffer is ready for swap.
+ * @post The orphan buffer can be used as new back buffer in the future.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ *
+ * @api
+ */
+void tribufSwapFront(tribuf_t *handler) {
+
+ osalSysLock();
+ tribufSwapFrontI(handler);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Gets the current back buffer.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Pointer to the current back buffer.
+ *
+ * @api
+ */
+void *tribufGetBack(tribuf_t *handler) {
+
+ void *back;
+
+ osalSysLock();
+ back = tribufGetBackI(handler);
+ osalSysUnlock();
+ return back;
+}
+
+/**
+ * @brief Swaps the current back buffer.
+ *
+ * @details Exchanges the pointer of the current back buffer, which holds new
+ * useful data, with the pointer of the current orphan buffer.
+ *
+ * @pre The orphan buffer holds no meaningful data.
+ * @post The orphan buffer is candidate for new front buffer.
+ * @post A new front buffer is ready and signaled.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ *
+ * @iclass
+ */
+void tribufSwapBackI(tribuf_t *handler) {
+
+ void *back;
+
+ osalDbgCheckClassI();
+
+ back = handler->orphan;
+ handler->orphan = handler->back;
+ handler->back = back;
+
+#if (TRIBUF_USE_WAIT == TRUE)
+ if (chSemGetCounterI(&handler->ready) < (cnt_t)1)
+ chSemSignalI(&handler->ready);
+#else
+ handler->ready = true;
+#endif
+}
+
+/**
+ * @brief Swaps the current back buffer.
+ *
+ * @details Exchanges the pointer of the current back buffer, which holds new
+ * useful data, with the pointer of the current orphan buffer.
+ *
+ * @pre The orphan buffer holds no meaningful data.
+ * @post The orphan buffer is candidate for new front buffer.
+ * @post A new front buffer is ready and signaled.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ *
+ * @api
+ */
+void tribufSwapBack(tribuf_t *handler) {
+
+ osalSysLock();
+ tribufSwapBackI(handler);
+#if (TRIBUF_USE_WAIT == TRUE)
+ osalOsRescheduleS();
+#endif
+ osalSysUnlock();
+}
+
+/** @} */
diff --git a/os/various/tribuf.h b/os/various/tribuf.h new file mode 100644 index 0000000..4ba3f25 --- /dev/null +++ b/os/various/tribuf.h @@ -0,0 +1,225 @@ +/*
+ Copyright (C) 2014..2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file tribuf.h
+ * @brief Triple buffer handler header.
+ *
+ * @addtogroup TriBuf
+ * @{
+ */
+
+#ifndef _TRIBUF_H_
+#define _TRIBUF_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Triple buffer configuration options
+ * @{
+ */
+
+/**
+ * @brief Triple buffers use blocking functions.
+ */
+#if !defined(TRIBUF_USE_WAIT) || defined(__DOXYGEN__)
+#define TRIBUF_USE_WAIT TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Triple buffer handler object.
+ */
+typedef struct {
+ void *front; /**< @brief Current front buffer pointer.*/
+ void *back; /**< @brief Current back buffer pointer.*/
+ void *orphan; /**< @brief Current orphan buffer pointer.*/
+#if (TRIBUF_USE_WAIT == TRUE)
+ semaphore_t ready; /**< @brief A new front buffer is ready.*/
+#else
+ bool ready; /**< @brief A new front buffer is ready.*/
+#endif
+} tribuf_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Checks if a new front buffer is ready.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Availability of a new front buffer.
+ *
+ * @iclass
+ */
+static inline
+bool tribufIsReadyI(tribuf_t *handler)
+{
+ osalDbgCheckClassI();
+
+#if (TRIBUF_USE_WAIT == TRUE)
+ return (0 != chSemGetCounterI(&handler->ready));
+#else
+ return handler->ready;
+#endif
+}
+
+#if (TRIBUF_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+
+/**
+ * @brief Waits until a new front buffer is ready, with timeout.
+ *
+ * @post The ready signal, result of the back buffer swap, is consumed.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @param[in] timeout Timeout of the wait operation.
+ * @return Timeout error code, as from @p chSemWaitTimeoutS.
+ *
+ * @see chSemWaitTimeoutS
+ * @sclass
+ */
+static inline
+msg_t tribufWaitReadyTimeoutS(tribuf_t *handler, systime_t timeout)
+{
+ osalDbgCheckClassS();
+
+ return chSemWaitTimeoutS(&handler->ready, timeout);
+}
+
+/**
+ * @brief Waits until a new front buffer is ready, with timeout.
+ *
+ * @post The ready signal, result of the back buffer swap, is consumed.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @param[in] timeout Timeout of the wait operation.
+ * @return Timeout error code, as from @p chSemWaitTimeout.
+ *
+ * @see chSemWaitTimeout
+ * @api
+ */
+static inline
+msg_t tribufWaitReadyTimeout(tribuf_t *handler, systime_t timeout)
+{
+ return chSemWaitTimeout(&handler->ready, timeout);
+}
+
+/**
+ * @brief Waits until a new front buffer is ready.
+ *
+ * @post The ready signal, result of the back buffer swap, is consumed.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Timeout error code, as from @p chSemWaitS.
+ *
+ * @see chSemWaitS
+ * @sclass
+ */
+static inline
+void tribufWaitReadyS(tribuf_t *handler)
+{
+ osalDbgCheckClassS();
+
+ chSemWaitS(&handler->ready);
+}
+
+/**
+ * @brief Waits until a new front buffer is ready.
+ *
+ * @post The ready signal, result of the back buffer swap, is consumed.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Timeout error code, as from @p chSemWait.
+ *
+ * @see chSemWait
+ * @api
+ */
+static inline
+void tribufWaitReady(tribuf_t *handler)
+{
+ chSemWait(&handler->ready);
+}
+
+#endif /* (TRIBUF_USE_WAIT == TRUE) || defined(__DOXYGEN__) */
+
+/**
+ * @brief Gets the current front buffer.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Pointer to the current front buffer.
+ *
+ * @iclass
+ */
+static inline
+void *tribufGetFrontI(tribuf_t *handler) {
+
+ osalDbgCheckClassI();
+
+ return handler->front;
+}
+
+/**
+ * @brief Gets the current back buffer.
+ *
+ * @param[in] handler Pointer to the tribuf handler object.
+ * @return Pointer to the current back buffer.
+ *
+ * @iclass
+ */
+static inline
+void *tribufGetBackI(tribuf_t *handler) {
+
+ osalDbgCheckClassI();
+
+ return handler->back;
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void tribufObjectInit(tribuf_t *handler, void *front, void *back, void *orphan);
+ void *tribufGetFront(tribuf_t *handler);
+ void tribufSwapFrontI(tribuf_t *handler);
+ void tribufSwapFront(tribuf_t *handler);
+ void *tribufGetBack(tribuf_t *handler);
+ void tribufSwapBackI(tribuf_t *handler);
+ void tribufSwapBack(tribuf_t *handler);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TRIBUF_H_ */
+/** @} */
diff --git a/testhal/STM32/STM32F0xx/onewire/Makefile b/testhal/STM32/STM32F0xx/onewire/Makefile index 72acaf4..1d47242 100644 --- a/testhal/STM32/STM32F0xx/onewire/Makefile +++ b/testhal/STM32/STM32F0xx/onewire/Makefile @@ -170,7 +170,7 @@ AOPT = TOPT = -mthumb -DTHUMB
# Define C warning options here
-CWARN = -Wall -Wextra -Wstrict-prototypes
+CWARN = -Wall -Wextra -Wstrict-prototypes -Wundef
# Define C++ warning options here
CPPWARN = -Wall -Wextra
diff --git a/testhal/STM32/STM32F0xx/onewire/halconf.h b/testhal/STM32/STM32F0xx/onewire/halconf.h index b0151c3..cf2b3f6 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf.h @@ -45,6 +45,13 @@ #endif
/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
diff --git a/testhal/STM32/STM32F0xx/onewire/halconf_community.h b/testhal/STM32/STM32F0xx/onewire/halconf_community.h index 7f64b2b..e90257b 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf_community.h @@ -38,6 +38,13 @@ #define HAL_USE_ONEWIRE TRUE
#endif
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -50,14 +57,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F1xx/onewire/Makefile b/testhal/STM32/STM32F1xx/onewire/Makefile index 8875fd8..4e33419 100644 --- a/testhal/STM32/STM32F1xx/onewire/Makefile +++ b/testhal/STM32/STM32F1xx/onewire/Makefile @@ -175,10 +175,10 @@ AOPT = TOPT = -mthumb -DTHUMB
# Define C warning options here
-CWARN = -Wall -Wextra -Wstrict-prototypes
+CWARN = -Wall -Wextra -Wstrict-prototypes -Wundef
# Define C++ warning options here
-CPPWARN = -Wall -Wextra
+CPPWARN = -Wall -Wextra -Wundef
#
# Compiler settings
diff --git a/testhal/STM32/STM32F1xx/onewire/halconf.h b/testhal/STM32/STM32F1xx/onewire/halconf.h index 6d7df57..0ecf5be 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf.h @@ -45,6 +45,13 @@ #endif
/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
diff --git a/testhal/STM32/STM32F1xx/onewire/halconf_community.h b/testhal/STM32/STM32F1xx/onewire/halconf_community.h index 7f64b2b..e90257b 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf_community.h @@ -38,6 +38,13 @@ #define HAL_USE_ONEWIRE TRUE
#endif
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -50,14 +57,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config new file mode 100644 index 0000000..e0284f4 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.config @@ -0,0 +1,2 @@ +// Add predefined macros for your project here. For example: +// #define THE_ANSWER 42 diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator @@ -0,0 +1 @@ +[General] diff --git a/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user new file mode 100644 index 0000000..80d783a --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/EICU_F4x.creator.user @@ -0,0 +1,156 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE QtCreatorProject> +<!-- Written by QtCreator 3.4.0, 2015-07-07T01:03:00. --> +<qtcreator> + <data> + <variable>EnvironmentId</variable> + <value type="QByteArray">{19e2588b-face-4845-bb71-0434e910b089}</value> + </data> + <data> + <variable>ProjectExplorer.Project.ActiveTarget</variable> + <value type="int">0</value> + </data> + <data> + <variable>ProjectExplorer.Project.EditorSettings</variable> + <valuemap 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+os/hal/ports/KINETIS/KL2x/kinetis_registry.h +os/hal/ports/KINETIS/KL2x/kinetis_tpm.h +os/hal/ports/KINETIS/KL2x/pal_lld.c +os/hal/ports/KINETIS/KL2x/pal_lld.h +os/hal/ports/KINETIS/KL2x/pwm_lld.c +os/hal/ports/KINETIS/KL2x/pwm_lld.h +os/hal/ports/KINETIS/KL2x/serial_lld.c +os/hal/ports/KINETIS/KL2x/serial_lld.h +os/hal/ports/KINETIS/KL2x/st_lld.c +os/hal/ports/KINETIS/KL2x/st_lld.h +os/hal/ports/KINETIS/LLD/adc_lld.c +os/hal/ports/KINETIS/LLD/adc_lld.h +os/hal/ports/KINETIS/LLD/ext_lld.c +os/hal/ports/KINETIS/LLD/ext_lld.h +os/hal/ports/KINETIS/LLD/i2c_lld.c +os/hal/ports/KINETIS/LLD/i2c_lld.h +os/hal/ports/LPC/LPC214x/hal_lld.c +os/hal/ports/LPC/LPC214x/hal_lld.h +os/hal/ports/LPC/LPC214x/pal_lld.c +os/hal/ports/LPC/LPC214x/pal_lld.h +os/hal/ports/LPC/LPC214x/serial_lld.c +os/hal/ports/LPC/LPC214x/serial_lld.h +os/hal/ports/LPC/LPC214x/spi_lld.c +os/hal/ports/LPC/LPC214x/spi_lld.h +os/hal/ports/LPC/LPC214x/st_lld.c +os/hal/ports/LPC/LPC214x/st_lld.h +os/hal/ports/LPC/LPC214x/vic.c +os/hal/ports/LPC/LPC214x/vic.h +os/hal/ports/simulator/win32/hal_lld.c +os/hal/ports/simulator/win32/hal_lld.h +os/hal/ports/simulator/win32/serial_lld.c +os/hal/ports/simulator/win32/serial_lld.h +os/hal/ports/simulator/console.c +os/hal/ports/simulator/console.h +os/hal/ports/simulator/pal_lld.c +os/hal/ports/simulator/pal_lld.h +os/hal/ports/simulator/st_lld.c +os/hal/ports/simulator/st_lld.h +os/hal/ports/STM32/LLD/DACv1/dac_lld.c +os/hal/ports/STM32/LLD/DACv1/dac_lld.h +os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c +os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h +os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h +os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h +os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h +os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h +os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +os/hal/ports/STM32/LLD/OTGv1/usb_lld.h +os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c +os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h +os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h +os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c +os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h +os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +os/hal/ports/STM32/LLD/SPIv1/spi_lld.h +os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +os/hal/ports/STM32/LLD/SPIv2/spi_lld.h +os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h +os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +os/hal/ports/STM32/LLD/TIMv1/icu_lld.h +os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h +os/hal/ports/STM32/LLD/TIMv1/st_lld.c +os/hal/ports/STM32/LLD/TIMv1/st_lld.h +os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h +os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +os/hal/ports/STM32/LLD/USARTv1/serial_lld.h +os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +os/hal/ports/STM32/LLD/USARTv1/uart_lld.h +os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +os/hal/ports/STM32/LLD/USARTv2/serial_lld.h +os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +os/hal/ports/STM32/LLD/USARTv2/uart_lld.h +os/hal/ports/STM32/LLD/USBv1/stm32_usb.h +os/hal/ports/STM32/LLD/USBv1/usb_lld.c +os/hal/ports/STM32/LLD/USBv1/usb_lld.h +os/hal/ports/STM32/LLD/can_lld.c +os/hal/ports/STM32/LLD/can_lld.h +os/hal/ports/STM32/LLD/ext_lld.c +os/hal/ports/STM32/LLD/ext_lld.h +os/hal/ports/STM32/LLD/mac_lld.c +os/hal/ports/STM32/LLD/mac_lld.h +os/hal/ports/STM32/LLD/sdc_lld.c +os/hal/ports/STM32/LLD/sdc_lld.h +os/hal/ports/STM32/STM32F0xx/adc_lld.c +os/hal/ports/STM32/STM32F0xx/adc_lld.h +os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c +os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h +os/hal/ports/STM32/STM32F0xx/hal_lld.c +os/hal/ports/STM32/STM32F0xx/hal_lld.h +os/hal/ports/STM32/STM32F0xx/stm32_dma.c +os/hal/ports/STM32/STM32F0xx/stm32_dma.h +os/hal/ports/STM32/STM32F0xx/stm32_isr.h +os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +os/hal/ports/STM32/STM32F0xx/stm32_registry.h +os/hal/ports/STM32/STM32F1xx/adc_lld.c +os/hal/ports/STM32/STM32F1xx/adc_lld.h +os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c +os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h +os/hal/ports/STM32/STM32F1xx/hal_lld.c +os/hal/ports/STM32/STM32F1xx/hal_lld.h +os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h +os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h +os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h +os/hal/ports/STM32/STM32F1xx/stm32_dma.c +os/hal/ports/STM32/STM32F1xx/stm32_dma.h +os/hal/ports/STM32/STM32F1xx/stm32_isr.h +os/hal/ports/STM32/STM32F1xx/stm32_rcc.h +os/hal/ports/STM32/STM32F1xx/stm32_registry.h +os/hal/ports/STM32/STM32F37x/adc_lld.c +os/hal/ports/STM32/STM32F37x/adc_lld.h +os/hal/ports/STM32/STM32F37x/ext_lld_isr.c +os/hal/ports/STM32/STM32F37x/ext_lld_isr.h +os/hal/ports/STM32/STM32F37x/hal_lld.c +os/hal/ports/STM32/STM32F37x/hal_lld.h +os/hal/ports/STM32/STM32F37x/stm32_dma.c +os/hal/ports/STM32/STM32F37x/stm32_dma.h +os/hal/ports/STM32/STM32F37x/stm32_isr.h +os/hal/ports/STM32/STM32F37x/stm32_rcc.h +os/hal/ports/STM32/STM32F37x/stm32_registry.h +os/hal/ports/STM32/STM32F3xx/adc_lld.c +os/hal/ports/STM32/STM32F3xx/adc_lld.h +os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c +os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h +os/hal/ports/STM32/STM32F3xx/hal_lld.c +os/hal/ports/STM32/STM32F3xx/hal_lld.h +os/hal/ports/STM32/STM32F3xx/stm32_dma.c +os/hal/ports/STM32/STM32F3xx/stm32_dma.h +os/hal/ports/STM32/STM32F3xx/stm32_isr.h +os/hal/ports/STM32/STM32F3xx/stm32_rcc.h +os/hal/ports/STM32/STM32F3xx/stm32_registry.h +os/hal/ports/STM32/STM32F4xx/adc_lld.c +os/hal/ports/STM32/STM32F4xx/adc_lld.h +os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c +os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h +os/hal/ports/STM32/STM32F4xx/hal_lld.c +os/hal/ports/STM32/STM32F4xx/hal_lld.h +os/hal/ports/STM32/STM32F4xx/stm32_dma.c +os/hal/ports/STM32/STM32F4xx/stm32_dma.h +os/hal/ports/STM32/STM32F4xx/stm32_isr.h +os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +os/hal/ports/STM32/STM32F4xx/stm32_registry.h +os/hal/ports/STM32/STM32L1xx/adc_lld.c +os/hal/ports/STM32/STM32L1xx/adc_lld.h +os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c +os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h +os/hal/ports/STM32/STM32L1xx/hal_lld.c +os/hal/ports/STM32/STM32L1xx/hal_lld.h +os/hal/ports/STM32/STM32L1xx/stm32_dma.c +os/hal/ports/STM32/STM32L1xx/stm32_dma.h +os/hal/ports/STM32/STM32L1xx/stm32_isr.h +os/hal/ports/STM32/STM32L1xx/stm32_rcc.h +os/hal/ports/STM32/STM32L1xx/stm32_registry.h +os/hal/src/adc.c +os/hal/src/can.c +os/hal/src/dac.c +os/hal/src/ext.c +os/hal/src/gpt.c +os/hal/src/hal.c +os/hal/src/hal_mmcsd.c +os/hal/src/hal_queues.c +os/hal/src/i2c.c +os/hal/src/i2s.c +os/hal/src/icu.c +os/hal/src/mac.c +os/hal/src/mmc_spi.c +os/hal/src/pal.c +os/hal/src/pwm.c +os/hal/src/rtc.c +os/hal/src/sdc.c +os/hal/src/serial.c +os/hal/src/serial_usb.c +os/hal/src/spi.c +os/hal/src/st.c +os/hal/src/uart.c +os/hal/src/usb.c +os/hal/templates/osal/osal.c +os/hal/templates/osal/osal.h +os/hal/templates/adc_lld.c +os/hal/templates/adc_lld.h +os/hal/templates/can_lld.c +os/hal/templates/can_lld.h +os/hal/templates/dac_lld.c +os/hal/templates/dac_lld.h +os/hal/templates/ext_lld.c +os/hal/templates/ext_lld.h +os/hal/templates/gpt_lld.c +os/hal/templates/gpt_lld.h +os/hal/templates/hal_lld.c +os/hal/templates/hal_lld.h +os/hal/templates/halconf.h +os/hal/templates/i2c_lld.c +os/hal/templates/i2c_lld.h +os/hal/templates/i2s_lld.c +os/hal/templates/i2s_lld.h +os/hal/templates/icu_lld.c +os/hal/templates/icu_lld.h +os/hal/templates/mac_lld.c +os/hal/templates/mac_lld.h +os/hal/templates/mcuconf.h +os/hal/templates/pal_lld.c +os/hal/templates/pal_lld.h +os/hal/templates/pwm_lld.c +os/hal/templates/pwm_lld.h +os/hal/templates/rtc_lld.c +os/hal/templates/rtc_lld.h +os/hal/templates/sdc_lld.c +os/hal/templates/sdc_lld.h +os/hal/templates/serial_lld.c +os/hal/templates/serial_lld.h +os/hal/templates/spi_lld.c +os/hal/templates/spi_lld.h +os/hal/templates/st_lld.c +os/hal/templates/st_lld.h +os/hal/templates/uart_lld.c +os/hal/templates/uart_lld.h +os/hal/templates/usb_lld.c +os/hal/templates/usb_lld.h +os/nil/include/nil.h +os/nil/ports/ARMCMx/compilers/GCC/niltypes.h +os/nil/ports/ARMCMx/nilcore.c +os/nil/ports/ARMCMx/nilcore.h +os/nil/ports/ARMCMx/nilcore_timer.h +os/nil/ports/ARMCMx/nilcore_v6m.c +os/nil/ports/ARMCMx/nilcore_v6m.h +os/nil/ports/ARMCMx/nilcore_v7m.c +os/nil/ports/ARMCMx/nilcore_v7m.h +os/nil/ports/AVR/compilers/GCC/niltypes.h +os/nil/ports/AVR/nilcore.c +os/nil/ports/AVR/nilcore.h +os/nil/ports/AVR/nilcore_timer.h +os/nil/ports/e200/compilers/GCC/niltypes.h +os/nil/ports/e200/nilcore.c +os/nil/ports/e200/nilcore.h +os/nil/src/nil.c +os/nil/templates/nilconf.h +os/nil/templates/nilcore.c +os/nil/templates/nilcore.h +os/nil/templates/nilcore_timer.h +os/nil/templates/niltypes.h +os/rt/include/ch.h +os/rt/include/chbsem.h +os/rt/include/chcond.h +os/rt/include/chdebug.h +os/rt/include/chdynamic.h +os/rt/include/chevents.h +os/rt/include/chheap.h +os/rt/include/chlicense.h +os/rt/include/chmboxes.h +os/rt/include/chmemcore.h +os/rt/include/chmempools.h +os/rt/include/chmsg.h +os/rt/include/chmtx.h +os/rt/include/chqueues.h +os/rt/include/chregistry.h +os/rt/include/chschd.h +os/rt/include/chsem.h +os/rt/include/chstats.h +os/rt/include/chstreams.h +os/rt/include/chsys.h +os/rt/include/chsystypes.h +os/rt/include/chthreads.h +os/rt/include/chtm.h +os/rt/include/chvt.h +os/rt/ports/ARM/compilers/GCC/chtypes.h +os/rt/ports/ARM/chcore.c +os/rt/ports/ARM/chcore.h +os/rt/ports/ARM/chcore_timer.h +os/rt/ports/ARMCMx/cmsis_os/cmsis_os.c +os/rt/ports/ARMCMx/cmsis_os/cmsis_os.h +os/rt/ports/ARMCMx/compilers/GCC/chtypes.h +os/rt/ports/ARMCMx/compilers/IAR/chtypes.h +os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h +os/rt/ports/ARMCMx/chcore.c +os/rt/ports/ARMCMx/chcore.h +os/rt/ports/ARMCMx/chcore_timer.h +os/rt/ports/ARMCMx/chcore_v6m.c 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+community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/ARMCMx/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/AVR +community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/AVR/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/e200 +community/testhal/STM32/STM32F4xx/EICU/os/nil/ports/e200/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/nil/templates +community/testhal/STM32/STM32F4xx/EICU/os/rt/include +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARM +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARM/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/cmsis_os +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/IAR +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/ARMCMx/compilers/RVCT +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/AVR +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/AVR/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/e200 +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/e200/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/SIMIA32 +community/testhal/STM32/STM32F4xx/EICU/os/rt/ports/SIMIA32/compilers/GCC +community/testhal/STM32/STM32F4xx/EICU/os/rt/templates +community/testhal/STM32/STM32F4xx/EICU/os/rt/templates/meta +community/testhal/STM32/STM32F4xx/EICU/os/various +community/testhal/STM32/STM32F4xx/EICU/os/various/devices_lib/accel +community/testhal/STM32/STM32F4xx/EICU/os/various/devices_lib/lcd +community/testhal/STM32/STM32F4xx/EICU/os/various/lwip_bindings +community/testhal/STM32/STM32F4xx/EICU/os/various/lwip_bindings/arch +community/testhal/STM32/STM32F4xx/FSMC_NAND +community/testhal/STM32/STM32F4xx/FSMC_SDRAM +community/testhal/STM32/STM32F4xx/FSMC_SRAM +community/testhal/STM32/STM32F4xx/onewire +community/testhal/TIVA/TM4C123x/EXT +community/testhal/TIVA/TM4C123x/GPT +community/testhal/TIVA/TM4C123x/I2C +community/testhal/TIVA/TM4C123x/PWM +community/testhal/TIVA/TM4C123x/SPI +os/common/ports/ARM/devices/LPC214x +os/common/ports/ARMCMx/devices/K20x +os/common/ports/ARMCMx/devices/KL2x +os/common/ports/ARMCMx/devices/STM32F0xx +os/common/ports/ARMCMx/devices/STM32F1xx +os/common/ports/ARMCMx/devices/STM32F3xx +os/common/ports/ARMCMx/devices/STM32F4xx +os/common/ports/ARMCMx/devices/STM32L0xx +os/common/ports/ARMCMx/devices/STM32L1xx +os/common/ports/e200/compilers/GCC +os/common/ports/e200/devices/SPC560BCxx +os/common/ports/e200/devices/SPC560Bxx +os/common/ports/e200/devices/SPC560Dxx +os/common/ports/e200/devices/SPC560Pxx +os/common/ports/e200/devices/SPC563Mxx +os/common/ports/e200/devices/SPC564Axx +os/common/ports/e200/devices/SPC56ECxx +os/common/ports/e200/devices/SPC56ELxx +os/common/ports/e200/devices/SPC57EMxx_HSM +os/ext/CMSIS/include +os/ext/CMSIS/KINETIS +os/ext/CMSIS/ST +os/hal/boards/ARDUINO_MEGA +os/hal/boards/EA_LPCXPRESSO_11C24 +os/hal/boards/EA_LPCXPRESSO_BB_1114 +os/hal/boards/EA_LPCXPRESSO_BB_11U14 +os/hal/boards/EA_LPCXPRESSO_BB_1343 +os/hal/boards/EA_LPCXPRESSO_LPC812 +os/hal/boards/FREESCALE_FREEDOM_K20D50M +os/hal/boards/FREESCALE_FREEDOM_KL25Z +os/hal/boards/MAPLEMINI_STM32_F103 +os/hal/boards/MCHCK_K20 +os/hal/boards/NGX_BB_LPC11U14 +os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1 +os/hal/boards/OLIMEX_AVR_CAN +os/hal/boards/OLIMEX_AVR_MT_128 +os/hal/boards/OLIMEX_LPC_P1227 +os/hal/boards/OLIMEX_LPC_P1343 +os/hal/boards/OLIMEX_LPC_P2148 +os/hal/boards/OLIMEX_MSP430_P1611 +os/hal/boards/OLIMEX_SAM7_EX256 +os/hal/boards/OLIMEX_SAM7_P256 +os/hal/boards/OLIMEX_STM32_103STK +os/hal/boards/OLIMEX_STM32_E407 +os/hal/boards/OLIMEX_STM32_E407_REV_D +os/hal/boards/OLIMEX_STM32_H103 +os/hal/boards/OLIMEX_STM32_H407 +os/hal/boards/OLIMEX_STM32_LCD +os/hal/boards/OLIMEX_STM32_P103 +os/hal/boards/OLIMEX_STM32_P107 +os/hal/boards/OLIMEX_STM32_P407 +os/hal/boards/PJRC_TEENSY_3 +os/hal/boards/RAISONANCE_REVA_STM8S +os/hal/boards/simulator +os/hal/boards/ST_EVB_SPC560B +os/hal/boards/ST_EVB_SPC560BC +os/hal/boards/ST_EVB_SPC560D +os/hal/boards/ST_EVB_SPC560P +os/hal/boards/ST_EVB_SPC563M +os/hal/boards/ST_EVB_SPC564A +os/hal/boards/ST_EVB_SPC56EC +os/hal/boards/ST_EVB_SPC56EL +os/hal/boards/ST_INEMO_M1_DISCOVERY +os/hal/boards/ST_NUCLEO_F030R8 +os/hal/boards/ST_NUCLEO_F103RB +os/hal/boards/ST_NUCLEO_F302R8 +os/hal/boards/ST_NUCLEO_F334R8 +os/hal/boards/ST_NUCLEO_F401RE +os/hal/boards/ST_NUCLEO_F411RE +os/hal/boards/ST_NUCLEO_L152RE +os/hal/boards/ST_STM3210C_EVAL +os/hal/boards/ST_STM3210E_EVAL +os/hal/boards/ST_STM3220G_EVAL +os/hal/boards/ST_STM32373C_EVAL +os/hal/boards/ST_STM32F072B_DISCOVERY +os/hal/boards/ST_STM32F0_DISCOVERY +os/hal/boards/ST_STM32F3_DISCOVERY +os/hal/boards/ST_STM32F401C_DISCOVERY +os/hal/boards/ST_STM32F429I_DISCOVERY +os/hal/boards/ST_STM32F4_DISCOVERY +os/hal/boards/ST_STM32L_DISCOVERY +os/hal/boards/ST_STM32VL_DISCOVERY +os/hal/boards/ST_STM8L_DISCOVERY +os/hal/boards/ST_STM8S_DISCOVERY +os/hal/boards/STUDIEL_AT91SAM7A3_EK +os/hal/include +os/hal/lib/streams +os/hal/osal/nil +os/hal/osal/os-less/ARMCMx +os/hal/osal/rt +os/hal/ports/AVR +os/hal/ports/common/ARMCMx +os/hal/ports/KINETIS/K20x +os/hal/ports/KINETIS/KL2x +os/hal/ports/KINETIS/LLD +os/hal/ports/LPC/LPC214x +os/hal/ports/simulator +os/hal/ports/simulator/win32 +os/hal/ports/STM32/LLD +os/hal/ports/STM32/LLD/DACv1 +os/hal/ports/STM32/LLD/DMAv1 +os/hal/ports/STM32/LLD/GPIOv1 +os/hal/ports/STM32/LLD/GPIOv2 +os/hal/ports/STM32/LLD/I2Cv1 +os/hal/ports/STM32/LLD/I2Cv2 +os/hal/ports/STM32/LLD/OTGv1 +os/hal/ports/STM32/LLD/RTCv1 +os/hal/ports/STM32/LLD/RTCv2 +os/hal/ports/STM32/LLD/SPIv1 +os/hal/ports/STM32/LLD/SPIv2 +os/hal/ports/STM32/LLD/TIMv1 +os/hal/ports/STM32/LLD/USARTv1 +os/hal/ports/STM32/LLD/USARTv2 +os/hal/ports/STM32/LLD/USBv1 +os/hal/ports/STM32/STM32F0xx +os/hal/ports/STM32/STM32F1xx +os/hal/ports/STM32/STM32F37x +os/hal/ports/STM32/STM32F3xx +os/hal/ports/STM32/STM32F4xx +os/hal/ports/STM32/STM32L1xx +os/hal/templates +os/hal/templates/osal +os/nil/include +os/nil/ports/ARMCMx +os/nil/ports/ARMCMx/compilers/GCC +os/nil/ports/AVR +os/nil/ports/AVR/compilers/GCC +os/nil/ports/e200 +os/nil/ports/e200/compilers/GCC +os/nil/templates +os/rt/include +os/rt/ports/ARM +os/rt/ports/ARM/compilers/GCC +os/rt/ports/ARMCMx +os/rt/ports/ARMCMx/cmsis_os +os/rt/ports/ARMCMx/compilers/GCC +os/rt/ports/ARMCMx/compilers/IAR +os/rt/ports/ARMCMx/compilers/RVCT +os/rt/ports/AVR +os/rt/ports/AVR/compilers/GCC +os/rt/ports/e200 +os/rt/ports/e200/compilers/GCC +os/rt/ports/SIMIA32 +os/rt/ports/SIMIA32/compilers/GCC +os/rt/templates +os/rt/templates/meta +os/various +os/various/devices_lib/accel +os/various/devices_lib/lcd +os/various/lwip_bindings +os/various/lwip_bindings/arch diff --git a/testhal/STM32/STM32F4xx/EICU/Makefile b/testhal/STM32/STM32F4xx/EICU/Makefile new file mode 100644 index 0000000..45641c8 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/Makefile @@ -0,0 +1,209 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/community/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = ccache $(TRGT)gcc
+CPPC = ccache $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes -Wundef
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
+
diff --git a/testhal/STM32/STM32F4xx/EICU/chconf.h b/testhal/STM32/STM32F4xx/EICU/chconf.h new file mode 100644 index 0000000..c8a8f19 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/chconf.h @@ -0,0 +1,498 @@ +/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 100000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM false
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES FALSE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS FALSE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS FALSE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT FALSE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES FALSE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES FALSE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES FALSE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE FALSE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP FALSE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS FALSE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/community b/testhal/STM32/STM32F4xx/EICU/community new file mode 120000 index 0000000..544599d --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/community @@ -0,0 +1 @@ +../../../../../community
\ No newline at end of file diff --git a/testhal/STM32/STM32F4xx/EICU/halconf.h b/testhal/STM32/STM32F4xx/EICU/halconf.h new file mode 100644 index 0000000..c65fbb4 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/halconf.h @@ -0,0 +1,340 @@ +/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Community drivers's includes */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/halconf_community.h b/testhal/STM32/STM32F4xx/EICU/halconf_community.h new file mode 100644 index 0000000..70856e8 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/halconf_community.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _HALCONF_COMMUNITY_H_
+#define _HALCONF_COMMUNITY_H_
+
+/**
+ * @brief Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY TRUE
+#endif
+
+/**
+ * @brief Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND FALSE
+#endif
+
+/**
+ * @brief Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE FALSE
+#endif
+
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU TRUE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables strong pull up feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP FALSE
+
+/**
+ * @brief Enables search ROM feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM FALSE
+
+#endif /* _HALCONF_COMMUNITY_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/EICU/main.c b/testhal/STM32/STM32F4xx/EICU/main.c new file mode 100644 index 0000000..4b3d72c --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/main.c @@ -0,0 +1,152 @@ +/*
+ ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * Make following connections on your discovery board:
+ * PD13-PB4
+ * PD12-PB5
+ * PD14-PB0
+ * PD15-PB1
+ */
+
+#include "ch.h"
+#include "hal.h"
+#include "stdlib.h"
+
+typedef struct {
+ systime_t high;
+ systime_t low;
+ uint32_t pad;
+} pulse_t;
+
+/*
+ * Chose values suitable for measurement using 16-bit timer on 1MHz
+ */
+static pulse_t pulse_led3 = {MS2ST(2), MS2ST(59), GPIOD_LED3};
+static pulse_t pulse_led4 = {MS2ST(3), MS2ST(53), GPIOD_LED4};
+static pulse_t pulse_led5 = {MS2ST(5), MS2ST(47), GPIOD_LED5};
+static pulse_t pulse_led6 = {MS2ST(7), MS2ST(43), GPIOD_LED6};
+
+/*
+ *
+ */
+static THD_WORKING_AREA(PulseThreadWA_LED3, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED4, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED5, 128);
+static THD_WORKING_AREA(PulseThreadWA_LED6, 128);
+
+static THD_FUNCTION(PulseThread, arg) {
+ chRegSetThreadName("Pulse");
+ pulse_t *pulse = arg;
+
+ systime_t t = chVTGetSystemTimeX();
+
+ while (!chThdShouldTerminateX()) {
+ t += pulse->high;
+ palSetPad(GPIOD, pulse->pad);
+ chThdSleepUntil(t);
+ palClearPad(GPIOD, pulse->pad);
+ t+= pulse->low;
+ chThdSleepUntil(t);
+ }
+
+ chThdExit(MSG_OK);
+}
+
+static const int32_t tolerance = 20; // uS
+void eicu_cb(EICUDriver *eicup, eicuchannel_t channel, uint32_t w, uint32_t p) {
+ (void)eicup;
+ (void)p;
+ switch (channel) {
+ case EICU_CHANNEL_1:
+ if (abs((int32_t)w - (int32_t)ST2US(pulse_led3.high)) > tolerance)
+ osalSysHalt("ch1");
+ break;
+ case EICU_CHANNEL_2:
+ if (abs((int32_t)w - (int32_t)ST2US(pulse_led4.high)) > tolerance)
+ osalSysHalt("ch2");
+ break;
+ case EICU_CHANNEL_3:
+ if (abs((int32_t)w - (int32_t)ST2US(pulse_led5.high)) > tolerance)
+ osalSysHalt("ch3");
+ break;
+ case EICU_CHANNEL_4:
+ if (abs((int32_t)w - (int32_t)ST2US(pulse_led6.high)) > tolerance)
+ osalSysHalt("ch4");
+ break;
+ default:
+ osalSysHalt("unhandled case");
+ break;
+ }
+}
+
+static const EICUChannelConfig led3cfg = {
+ EICU_INPUT_ACTIVE_HIGH,
+ EICU_INPUT_PULSE,
+ eicu_cb
+};
+
+static const EICUConfig eicucfg = {
+ 1000000, /* EICU clock frequency in Hz.*/
+ {
+ &led3cfg,
+ &led3cfg,
+ &led3cfg,
+ &led3cfg
+ },
+ 0
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ palSetPadMode(GPIOB, GPIOB_PIN0, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+ palSetPadMode(GPIOB, GPIOB_PIN1, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+ palSetPadMode(GPIOB, GPIOB_PIN4, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+ palSetPadMode(GPIOB, GPIOB_PIN5, PAL_MODE_ALTERNATE(2) | PAL_STM32_PUDR_FLOATING);
+
+ eicuStart(&EICUD3, &eicucfg);
+ eicuEnable(&EICUD3);
+
+ osalThreadSleepMicroseconds(10); // need to stabilize input puns
+
+ chThdCreateStatic(PulseThreadWA_LED3, sizeof(PulseThreadWA_LED3),
+ NORMALPRIO+1, PulseThread, &pulse_led3);
+ chThdCreateStatic(PulseThreadWA_LED4, sizeof(PulseThreadWA_LED4),
+ NORMALPRIO+1, PulseThread, &pulse_led4);
+ chThdCreateStatic(PulseThreadWA_LED5, sizeof(PulseThreadWA_LED5),
+ NORMALPRIO+1, PulseThread, &pulse_led5);
+ chThdCreateStatic(PulseThreadWA_LED6, sizeof(PulseThreadWA_LED6),
+ NORMALPRIO+1, PulseThread, &pulse_led6);
+
+ while (true) {
+ osalThreadSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf.h b/testhal/STM32/STM32F4xx/EICU/mcuconf.h new file mode 100644 index 0000000..e67608f --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/mcuconf.h @@ -0,0 +1,310 @@ +/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * header for community drivers.
+ */
+#include "mcuconf_community.h"
+
diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h new file mode 100644 index 0000000..adc9d92 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 FALSE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 + +/* + * FSMC NAND driver system settings. + */ +#define STM32_NAND_USE_FSMC_NAND1 FALSE +#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") + +/* + * FSMC SRAM driver system settings. + */ +#define STM32_USE_FSMC_SRAM FALSE +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#define STM32_SRAM_USE_FSMC_SRAM3 FLASE +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE + +/* + * FSMC PC card driver system settings. + */ +#define STM32_USE_FSMC_PCARD FALSE + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM FALSE + +/* + * EICU driver system settings. + */ +#define STM32_EICU_USE_TIM1 FALSE +#define STM32_EICU_USE_TIM2 FALSE +#define STM32_EICU_USE_TIM3 TRUE +#define STM32_EICU_USE_TIM4 FALSE +#define STM32_EICU_USE_TIM5 FALSE +#define STM32_EICU_USE_TIM8 FALSE +#define STM32_EICU_USE_TIM9 FALSE +#define STM32_EICU_USE_TIM10 FALSE +#define STM32_EICU_USE_TIM11 FALSE +#define STM32_EICU_USE_TIM12 FALSE +#define STM32_EICU_USE_TIM13 FALSE +#define STM32_EICU_USE_TIM14 FALSE +#define STM32_EICU_TIM1_IRQ_PRIORITY 7 +#define STM32_EICU_TIM2_IRQ_PRIORITY 7 +#define STM32_EICU_TIM3_IRQ_PRIORITY 7 +#define STM32_EICU_TIM4_IRQ_PRIORITY 7 +#define STM32_EICU_TIM5_IRQ_PRIORITY 7 +#define STM32_EICU_TIM8_IRQ_PRIORITY 7 +#define STM32_EICU_TIM9_IRQ_PRIORITY 7 +#define STM32_EICU_TIM10_IRQ_PRIORITY 7 +#define STM32_EICU_TIM11_IRQ_PRIORITY 7 +#define STM32_EICU_TIM12_IRQ_PRIORITY 7 +#define STM32_EICU_TIM13_IRQ_PRIORITY 7 +#define STM32_EICU_TIM14_IRQ_PRIORITY 7 + diff --git a/testhal/STM32/STM32F4xx/EICU/os b/testhal/STM32/STM32F4xx/EICU/os new file mode 120000 index 0000000..18fd3d9 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/os @@ -0,0 +1 @@ +../../../../../os
\ No newline at end of file diff --git a/testhal/STM32/STM32F4xx/EICU/readme.txt b/testhal/STM32/STM32F4xx/EICU/readme.txt new file mode 100644 index 0000000..2f45f99 --- /dev/null +++ b/testhal/STM32/STM32F4xx/EICU/readme.txt @@ -0,0 +1,32 @@ +*****************************************************************************
+** ChibiOS/RT HAL - 1-Wire driver demo for STM32F4xx. **
+*****************************************************************************
+
+** TARGET **
+
+The demo will on an STMicroelectronics STM32F4-Discovery board.
+
+** The Demo **
+
+The application demonstrates the use of the STM32F4xx 1-Wire driver.
+
+** Board Setup **
+
+To use demo you have to power your 1-wire device from 5V bus on board
+and connect DQ line to PB0 pin. Do not forget about external pullup
+resistor to 5V (4k7 recommended).
+
+** Build Procedure **
+
+The demo has been tested using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile b/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile index 5474ee7..a203a21 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile @@ -105,6 +105,7 @@ CSRC = $(STARTUPSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(TESTSRC) \ + $(CHIBIOS)/community/os/various/bitmap.c \ dma_storm_adc.c \ dma_storm_spi.c \ dma_storm_uart.c \ @@ -139,7 +140,7 @@ ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various $(CHIBIOS)/community/os/various # diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h index b983830..7bd9c15 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h @@ -361,7 +361,7 @@ * * @note The default is @p FALSE. */ -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE FALSE /** * @brief Debug option, stack checks. diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h index 0be66ba..79dc76d 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h @@ -1,3 +1,19 @@ +/* + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + #ifndef DMA_STORM_H_ #define DMA_STORM_H_ diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h index b284367..b4882dc 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h @@ -45,6 +45,13 @@ #endif /** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** * @brief Enables the CAN subsystem. */ #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h index fd15a4e..5c979fa 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h @@ -38,6 +38,13 @@ #define HAL_USE_ONEWIRE FALSE
#endif
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -50,14 +57,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index bdc72e0..2379a12 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -44,6 +44,8 @@ #include "ch.h" #include "hal.h" +#include "bitmap.h" + #include "dma_storm.h" #include "string.h" #include "stdlib.h" @@ -54,6 +56,8 @@ ****************************************************************************** */ +#define USE_BAD_MAP TRUE + #define USE_KILL_BLOCK_TEST FALSE #define FSMCNAND_TIME_SET ((uint32_t) 2) //(8nS) @@ -69,7 +73,7 @@ #define NAND_ROW_WRITE_CYCLES 3 #define NAND_COL_WRITE_CYCLES 2 -#define NANF_TEST_START_BLOCK 1200 +#define NAND_TEST_START_BLOCK 1200 #define NAND_TEST_END_BLOCK 1220 #if USE_KILL_BLOCK_TEST @@ -120,23 +124,25 @@ static time_measurement_t tmu_write_data; static time_measurement_t tmu_write_spare; static time_measurement_t tmu_read_data; static time_measurement_t tmu_read_spare; - -#if NAND_USE_BAD_MAP -static uint32_t badblock_map[NAND_BLOCKS_COUNT / 32]; +static time_measurement_t tmu_driver_start; + +#if USE_BAD_MAP +#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8)) +static bitmap_word_t badblock_map_array[BAD_MAP_LEN]; +static bitmap_t badblock_map = { + badblock_map_array, + BAD_MAP_LEN +}; #endif /* * */ static const NANDConfig nandcfg = { - &FSMCD1, NAND_BLOCKS_COUNT, NAND_PAGE_DATA_SIZE, NAND_PAGE_SPARE_SIZE, NAND_PAGES_PER_BLOCK, -#if NAND_USE_BAD_MAP - badblock_map, -#endif NAND_ROW_WRITE_CYCLES, NAND_COL_WRITE_CYCLES, /* stm32 specific fields */ @@ -567,7 +573,14 @@ int main(void) { #if STM32_NAND_USE_EXT_INT extStart(&EXTD1, &extcfg); #endif - nandStart(&NAND, &nandcfg); + chTMObjectInit(&tmu_driver_start); + chTMStartMeasurementX(&tmu_driver_start); +#if USE_BAD_MAP + nandStart(&NAND, &nandcfg, &badblock_map); +#else + nandStart(&NAND, &nandcfg, NULL); +#endif + chTMStopMeasurementX(&tmu_driver_start); chThdSleepMilliseconds(4000); @@ -586,7 +599,7 @@ int main(void) { dma_storm_uart_start(); dma_storm_spi_start(); T = chVTGetSystemTimeX(); - general_test(&NAND, NANF_TEST_START_BLOCK, NAND_TEST_END_BLOCK, 1); + general_test(&NAND, NAND_TEST_START_BLOCK, NAND_TEST_END_BLOCK, 1); T = chVTGetSystemTimeX() - T; adc_ints = dma_storm_adc_stop(); uart_ints = dma_storm_uart_stop(); @@ -611,9 +624,9 @@ int main(void) { * ensure that NAND code have negligible impact on other subsystems */ osalDbgCheck(background_cnt > (BackgroundThdCnt / 4)); - osalDbgCheck(abs(adc_ints - adc_idle_ints) < (adc_idle_ints / 20)); + osalDbgCheck(abs(adc_ints - adc_idle_ints) < (adc_idle_ints / 20)); osalDbgCheck(abs(uart_ints - uart_idle_ints) < (uart_idle_ints / 20)); - osalDbgCheck(abs(spi_ints - spi_idle_ints) < (spi_idle_ints / 10)); + osalDbgCheck(abs(spi_ints - spi_idle_ints) < (spi_idle_ints / 10)); /* * perform ECC calculation test @@ -629,7 +642,7 @@ int main(void) { /* * Normal main() thread activity, in this demo it does nothing. */ - while (TRUE) { + while (true) { chThdSleepMilliseconds(500); } } diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index a9c0daf..f2b53d8 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -21,7 +21,8 @@ #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_NAND_USE_FSMC_NAND1 TRUE -#define STM32_NAND_USE_EXT_INT TRUE +#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 #define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") @@ -30,4 +31,12 @@ * FSMC SRAM driver system settings. */ #define STM32_USE_FSMC_SRAM FALSE +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE #define STM32_SRAM_USE_FSMC_SRAM4 FALSE + +/* + * FSMC PC card driver system settings. + */ +#define STM32_USE_FSMC_PCCARD FALSE diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile index 7e083fa..2cc9d5a 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile @@ -30,7 +30,7 @@ endif # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) - USE_LTO = yes + USE_LTO = no endif # If enabled, this option allows to compile the application in THUMB mode. @@ -81,32 +81,40 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/community/os/hal/hal.mk -include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk -include $(CHIBIOS)/test/rt/test.mk - +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/STM32F407xG.ld +LDSCRIPT = $(STARTUPLD)/STM32F429xI.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - $(CHIBIOS)/os/various/chprintf.c \ - main.c + $(TESTSRC) \ + main.c \ + memcpy_dma.c \ + membench.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CPPSRC = +CPPSRC = $(CHCPPSRC) \ + $(CHIBIOS)/community/os/various/memtest.cpp # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler @@ -129,12 +137,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various/cpp_wrappers \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/community/os/various # # Project, sources and paths diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index c9b292d..f18d5cf 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -50,14 +50,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 68d9b44..5f93520 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -18,24 +18,20 @@ aka barthess. */ -/* -TODO: -write memtest function using ideas from http://www.memtest86.com/technical.htm -*/ - #include "ch.h" #include "hal.h" #include "string.h" #include "fsmc_sdram.h" +#include "membench.h" +#include "memtest.hpp" /* ****************************************************************************** * DEFINES ****************************************************************************** */ -#define USE_INFINITE_MEMTEST FALSE /* * FMC SDRAM Mode definition register defines @@ -116,6 +112,9 @@ write memtest function using ideas from http://www.memtest86.com/technical.htm #define FMC_Write_Protection_Disable ((uint32_t)0x00000000) #define FMC_Write_Protection_Enable ((uint32_t)0x00000200) +#define SDRAM_SIZE (8 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) + /* ****************************************************************************** * EXTERNS @@ -128,14 +127,13 @@ write memtest function using ideas from http://www.memtest86.com/technical.htm ****************************************************************************** */ +static void mem_error_cb(memtest_t *memp, testtype e, size_t address); + /* ****************************************************************************** * GLOBAL VARIABLES ****************************************************************************** */ -static uint32_t extram_check_buf[16 * 1024]; -static uint32_t *extram_start = (uint32_t *)STM32_SDRAM1_MAP_BASE; -static const size_t extram_size = 1024*1024; /* * SDRAM driver configuration structure. @@ -164,17 +162,46 @@ static const SDRAMConfig sdram_cfg = { FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, - /* if (STM32_SYSCLK == 180000000) -> - 64ms/4096=15.625us - 15.625us*90MHz=1406-20=1386 */ - .sdrtr = 1386 << 1 + .sdrtr = (uint32_t)(683 << 1), +}; + +/* + * + */ +static uint8_t int_buf[64*1024]; + +/* + * + */ +static memtest_t memtest_struct = { + SDRAM_START, + SDRAM_SIZE, + MEMTEST_WIDTH_16, + mem_error_cb, + 42 +}; + +/* + * + */ +static membench_t membench_ext = { + SDRAM_START, + SDRAM_SIZE, +}; + +/* + * + */ +static membench_t membench_int = { + int_buf, + sizeof(int_buf), }; -/* benchmarking results in MiB/S */ -double memset_speed_ext; -double memset_speed_int; -double memcpy_speed_ext2int; -double memcpy_speed_int2ext; +/* + * + */ +static membench_result_t membench_result_ext2int; +static membench_result_t membench_result_int2ext; /* ****************************************************************************** @@ -183,58 +210,33 @@ double memcpy_speed_int2ext; ****************************************************************************** ****************************************************************************** */ -/** - * - */ -static void extram_benchmark(void){ - - size_t i=0; - time_measurement_t mem_tmu; - - /* memset speed ext */ - chTMObjectInit(&mem_tmu); - chTMStartMeasurementX(&mem_tmu); - memset(extram_start, 0x55, extram_size); - //memset(extram_start, 0x00, extram_size); - chTMStopMeasurementX(&mem_tmu); - memset_speed_ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK); - - /* memset speed int */ - chTMObjectInit(&mem_tmu); - chTMStartMeasurementX(&mem_tmu); - for (i=0; i<16; i++) - memset(extram_check_buf, i, sizeof(extram_check_buf)); - chTMStopMeasurementX(&mem_tmu); - memset_speed_int = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK); - - /* memcpy ext2int */ - chTMObjectInit(&mem_tmu); - chTMStartMeasurementX(&mem_tmu); - for (i=0; i<16; i++) - memcpy(extram_check_buf, extram_start+ i * sizeof(extram_check_buf), sizeof(extram_check_buf)); - chTMStopMeasurementX(&mem_tmu); - memcpy_speed_ext2int = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK); - - /* memcpy int2ext */ - chTMObjectInit(&mem_tmu); - memset(extram_check_buf, 0xAA, sizeof(extram_check_buf)); - chTMStartMeasurementX(&mem_tmu); - for (i=0; i<16; i++) - memcpy(extram_start + i * sizeof(extram_check_buf), extram_check_buf, sizeof(extram_check_buf)); - chTMStopMeasurementX(&mem_tmu); - memcpy_speed_int2ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK); + +void mem_error_cb(memtest_t *memp, testtype e, size_t address) { + (void)memp; + (void)e; + (void)address; + + osalSysHalt("Memory broken"); } -/** +/* * */ -#if USE_INFINITE_MEMTEST -static void memstest(void){ +static void memtest(void) { + while (true) { - ; + memtest_struct.rand_seed = chSysGetRealtimeCounterX(); + memtest_run(&memtest_struct, MEMTEST_RUN_ALL); } } -#endif /* USE_INFINITE_MEMTEST */ + +/* + * + */ +static void membench(void) { + membench_run(&membench_ext, &membench_int, &membench_result_int2ext); + membench_run(&membench_int, &membench_ext, &membench_result_ext2int); +} /* ****************************************************************************** @@ -259,11 +261,9 @@ int main(void) { fsmcSdramInit(); fsmcSdramStart(&SDRAMD, &sdram_cfg); - extram_benchmark(); -#if USE_INFINITE_MEMTEST + membench(); memtest(); -#endif /* * Normal main() thread activity, in this demo it does nothing. diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h index 95a584c..81c7e2c 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h @@ -24,4 +24,5 @@ * FSMC SDRAM driver system settings. */ #define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.c new file mode 100644 index 0000000..91b9aee --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.c @@ -0,0 +1,133 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include <string.h> + +#include "ch.h" +#include "hal.h" + +#include "membench.h" +#include "memcpy_dma.h" + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ + +/* + ****************************************************************************** + * EXTERNS + ****************************************************************************** + */ + +/* + ****************************************************************************** + * PROTOTYPES + ****************************************************************************** + */ + +/* + ****************************************************************************** + * GLOBAL VARIABLES + ****************************************************************************** + */ +volatile int warning_suppressor; + +/* + ****************************************************************************** + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + ****************************************************************************** + */ +/* + * Calculates memory access time in MiB/s. + */ +double speed_mibps(const time_measurement_t *tmu, size_t len) { + double size; // MiB + double time; // sec + + size = len; + size /= 1024 * 1024; + + time = tmu->last; + time /= STM32_SYSCLK; + + return size / time; +} + +/* + * Calculates memory access time in B/s. + */ +uint32_t speed_bps(const time_measurement_t *tmu, size_t len) { + + uint64_t tmp = len; + tmp *= STM32_SYSCLK; + + return tmp / tmu->last; +} + +/* + ****************************************************************************** + * EXPORTED FUNCTIONS + ****************************************************************************** + */ + +/* + * + */ +void membench_run(membench_t *dest, const membench_t *src, + membench_result_t *result) { + time_measurement_t mem_tmu; + size_t len; + + if (src->size < dest->size) + len = src->size; + else + len = dest->size; + + /* memset */ + chTMObjectInit(&mem_tmu); + chTMStartMeasurementX(&mem_tmu); + memset(dest->start, 0x55, dest->size); + chTMStopMeasurementX(&mem_tmu); + result->memset = speed_bps(&mem_tmu, dest->size); + + /* memcpy */ + chTMObjectInit(&mem_tmu); + chTMStartMeasurementX(&mem_tmu); + memcpy(dest->start, src->start, len); + chTMStopMeasurementX(&mem_tmu); + result->memcpy = speed_bps(&mem_tmu, len); + + /* memcmp */ + chTMObjectInit(&mem_tmu); + chTMStartMeasurementX(&mem_tmu); + warning_suppressor = memcmp(dest->start, src->start, len); + chTMStopMeasurementX(&mem_tmu); + result->memcmp = speed_bps(&mem_tmu, len); + + /* memcpy DMA */ + memcpy_dma_start(); + chTMObjectInit(&mem_tmu); + chTMStartMeasurementX(&mem_tmu); + memcpy_dma(dest->start, src->start, len); + chTMStopMeasurementX(&mem_tmu); + result->memcpy_dma = speed_bps(&mem_tmu, len); + memcpy_dma_stop(); +} + diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.h new file mode 100644 index 0000000..1169145 --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/membench.h @@ -0,0 +1,49 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MEMBENCH_H_ +#define MEMBENCH_H_ + +/* + * + */ +typedef struct { + void *start; + size_t size; +} membench_t; + +/* + * all values in B/s + */ +typedef struct { + uint32_t memset; + uint32_t memcpy; + uint32_t memcpy_dma; + uint32_t memcmp; +} membench_result_t; + +/* + * + */ +#ifdef __cplusplus +extern "C" { +#endif + void membench_run(membench_t *dest, const membench_t *src, membench_result_t *ret); +#ifdef __cplusplus +} +#endif + +#endif /* MEMBENCH_H_ */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.c new file mode 100644 index 0000000..4961c7c --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.c @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include <string.h> + +#include "ch.h" +#include "hal.h" + +#include "memcpy_dma.h" + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ +#define STM32_MEMCPY_DMA_PRIORITY 0 +#define STM32_MEMCPY_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) + +/* + ****************************************************************************** + * EXTERNS + ****************************************************************************** + */ + +/* + ****************************************************************************** + * PROTOTYPES + ****************************************************************************** + */ + +/* + ****************************************************************************** + * GLOBAL VARIABLES + ****************************************************************************** + */ +static memcpy_dma_engine_t engine; + +/* + ****************************************************************************** + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + ****************************************************************************** + */ + +/* + ****************************************************************************** + * EXPORTED FUNCTIONS + ****************************************************************************** + */ +/* + * + */ +void memcpy_dma_start(void) { + bool b; + + engine.dma = STM32_DMA_STREAM(STM32_MEMCPY_DMA_STREAM); + b = dmaStreamAllocate(engine.dma, STM32_MEMCPY_DMA_PRIORITY, NULL, NULL); + osalDbgAssert(!b, "stream already allocated"); +} + +/* + * + */ +void memcpy_dma_stop(void) { + dmaStreamRelease(engine.dma); +} + +/* + * + */ +void memcpy_dma(void *dest, const void *src, size_t size) { + + size_t words = size / 4; + size_t remainder = size % 4; + size_t max_block = 0xFFFF; /* DMA limitation */ + + uint32_t cr = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; + + while (words > max_block) { + dmaStartMemCopy(engine.dma, cr, src, dest, max_block) + dmaWaitCompletion(engine.dma); + words -= max_block; + } + + dmaStartMemCopy(engine.dma, cr, src, dest, words) + dmaWaitCompletion(engine.dma); + + if (remainder > 0) + memcpy(dest+size-remainder, src+size-remainder, remainder); +} + diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.h new file mode 100644 index 0000000..8d6212c --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/memcpy_dma.h @@ -0,0 +1,40 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MEMCPY_DMA_H_ +#define MEMCPY_DMA_H_ + +/* + * + */ +typedef struct { + const stm32_dma_stream_t *dma; +} memcpy_dma_engine_t; + +/* + * + */ +#ifdef __cplusplus +extern "C" { +#endif + void memcpy_dma_start(void); + void memcpy_dma_stop(void); + void memcpy_dma(void *dest, const void *src, size_t size); +#ifdef __cplusplus +} +#endif + +#endif /* MEMCPY_DMA_H_ */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/Makefile b/testhal/STM32/STM32F4xx/FSMC_SRAM/Makefile index ec5d18c..e3d83c4 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/Makefile +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/Makefile @@ -10,7 +10,7 @@ endif # C specific options here (added to USE_OPT). ifeq ($(USE_COPT),) - USE_COPT = + USE_COPT = endif # C++ specific options here (added to USE_OPT). @@ -114,7 +114,7 @@ CSRC = $(STARTUPSRC) \ # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. CPPSRC = $(CHCPPSRC) \ - memtest.cpp + $(CHIBIOS)/community/os/various/memtest.cpp # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler @@ -142,7 +142,8 @@ ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various/cpp_wrappers \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various \ + $(CHIBIOS)/community/os/various # # Project, sources and paths diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf.h index b284367..b4882dc 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf.h @@ -45,6 +45,13 @@ #endif /** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** * @brief Enables the CAN subsystem. */ #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index c9b292d..be71357 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -38,6 +38,13 @@ #define HAL_USE_ONEWIRE FALSE
#endif
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -50,14 +57,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c index 186450f..03d7f1d 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c @@ -41,7 +41,7 @@ ****************************************************************************** */ -static void mem_error_cb(memtest_t *memp, testtype_t e, size_t address); +static void mem_error_cb(memtest_t *memp, testtype e, size_t address); /* ****************************************************************************** @@ -110,7 +110,7 @@ static inline void green_led_on(void) {palSetPad(GPIOI, GPIOI_LED_G);} static inline void green_led_off(void) {palClearPad(GPIOI, GPIOI_LED_G);} static inline void green_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_G);} -void mem_error_cb(memtest_t *memp, testtype_t e, size_t address) { +void mem_error_cb(memtest_t *memp, testtype e, size_t address) { (void)memp; (void)e; (void)address; diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h index d1afed1..ebcb63d 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h @@ -24,6 +24,7 @@ * FSMC NAND driver system settings. */ #define STM32_NAND_USE_FSMC_NAND1 FALSE +#define STM32_NAND_USE_FSMC_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 @@ -33,4 +34,17 @@ * FSMC SRAM driver system settings. */ #define STM32_USE_FSMC_SRAM TRUE +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#define STM32_SRAM_USE_FSMC_SRAM3 FLASE #define STM32_SRAM_USE_FSMC_SRAM4 TRUE + +/* + * FSMC PC card driver system settings. + */ +#define STM32_USE_FSMC_PCARD FALSE + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM FALSE diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/membench.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/membench.h index 5f23e1c..1169145 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/membench.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/membench.h @@ -1,3 +1,19 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + #ifndef MEMBENCH_H_ #define MEMBENCH_H_ diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.c index 2705382..4961c7c 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.c @@ -68,7 +68,7 @@ void memcpy_dma_start(void) { bool b; engine.dma = STM32_DMA_STREAM(STM32_MEMCPY_DMA_STREAM); - b = dmaStreamAllocate(engine.dma, STM32_NAND_DMA_PRIORITY, NULL, NULL); + b = dmaStreamAllocate(engine.dma, STM32_MEMCPY_DMA_PRIORITY, NULL, NULL); osalDbgAssert(!b, "stream already allocated"); } @@ -103,11 +103,3 @@ void memcpy_dma(void *dest, const void *src, size_t size) { memcpy(dest+size-remainder, src+size-remainder, remainder); } - - - - - - - - diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.h index ceefee1..8d6212c 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/memcpy_dma.h @@ -1,3 +1,19 @@ +/* + ChibiOS/RT - Copyright (C) 2013-2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + #ifndef MEMCPY_DMA_H_ #define MEMCPY_DMA_H_ diff --git a/testhal/STM32/STM32F4xx/onewire/Makefile b/testhal/STM32/STM32F4xx/onewire/Makefile index 999fb12..c07981c 100644 --- a/testhal/STM32/STM32F4xx/onewire/Makefile +++ b/testhal/STM32/STM32F4xx/onewire/Makefile @@ -173,10 +173,10 @@ AOPT = TOPT = -mthumb -DTHUMB
# Define C warning options here
-CWARN = -Wall -Wextra -Wstrict-prototypes
+CWARN = -Wall -Wextra -Wstrict-prototypes -Wundef
# Define C++ warning options here
-CPPWARN = -Wall -Wextra
+CPPWARN = -Wall -Wextra -Wundef
#
# Compiler settings
diff --git a/testhal/STM32/STM32F4xx/onewire/halconf.h b/testhal/STM32/STM32F4xx/onewire/halconf.h index 6d7df57..0ecf5be 100644 --- a/testhal/STM32/STM32F4xx/onewire/halconf.h +++ b/testhal/STM32/STM32F4xx/onewire/halconf.h @@ -45,6 +45,13 @@ #endif
/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
diff --git a/testhal/STM32/STM32F4xx/onewire/halconf_community.h b/testhal/STM32/STM32F4xx/onewire/halconf_community.h index 7f64b2b..e90257b 100644 --- a/testhal/STM32/STM32F4xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/halconf_community.h @@ -38,6 +38,13 @@ #define HAL_USE_ONEWIRE TRUE
#endif
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -50,14 +57,6 @@ #define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
-/**
- * @brief Enables internal driver map for bad blocks.
- * @note Disabling this option saves both code and data space.
- */
-#if !defined(NAND_USE_BAD_MAP) || defined(__DOXYGEN__)
-#define NAND_USE_BAD_MAP TRUE
-#endif
-
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
diff --git a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h index fa9798e..1acd3de 100644 --- a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h @@ -20,7 +20,11 @@ #define STM32_FSMC_USE_FSMC1 FALSE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +/* + * FSMC NAND driver system settings. + */ #define STM32_NAND_USE_FSMC_NAND1 FALSE +#define STM32_NAND_USE_FSMC_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 @@ -30,4 +34,17 @@ * FSMC SRAM driver system settings. */ #define STM32_USE_FSMC_SRAM FALSE +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#define STM32_SRAM_USE_FSMC_SRAM3 FLASE #define STM32_SRAM_USE_FSMC_SRAM4 FALSE + +/* + * FSMC PC card driver system settings. + */ +#define STM32_USE_FSMC_PCARD FALSE + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM FALSE diff --git a/testhal/TIVA/TM4C123x/EXT/.cproject b/testhal/TIVA/TM4C123x/EXT/.cproject new file mode 100644 index 0000000..5aa94c5 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/.cproject @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?> +<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="0.114656749"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg"> + <folderInfo id="0.114656749." name="/" resourcePath=""> + <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain"> + <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/> + <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> + <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> + <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="TM4C123x-EXT.null.1703860681" name="TM4C123x-EXT"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + <scannerConfigBuildInfo instanceId="0.114656749"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> +</cproject> diff --git a/testhal/TIVA/TM4C123x/EXT/.project b/testhal/TIVA/TM4C123x/EXT/.project new file mode 100644 index 0000000..79bd112 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/.project @@ -0,0 +1,106 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>TM4C123x-EXT</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.autoBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value>-j1</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>make</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>board</name> + <type>2</type> + <locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD</locationURI> + </link> + <link> + <name>community_os</name> + <type>2</type> + <locationURI>CHIBIOS3/community/os</locationURI> + </link> + <link> + <name>os</name> + <type>2</type> + <locationURI>CHIBIOS3/os</locationURI> + </link> + <link> + <name>test</name> + <type>2</type> + <locationURI>CHIBIOS3/test</locationURI> + </link> + </linkedResources> + <variableList> + <variable> + <name>CHIBIOS3</name> + <value>file:/C:/ChibiStudio/chibios3</value> + </variable> + </variableList> +</projectDescription> diff --git a/testhal/TIVA/TM4C123x/EXT/Makefile b/testhal/TIVA/TM4C123x/EXT/Makefile new file mode 100644 index 0000000..43de29b --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/TIVA/TM4C123x/EXT/chconf.h b/testhal/TIVA/TM4C123x/EXT/chconf.h new file mode 100644 index 0000000..5e26c27 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/chconf.h @@ -0,0 +1,468 @@ +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** + * @brief Realtime Counter frequency. + * @details Frequency of the system counter used for realtime delays and + * measurements. + */ +#define CH_CFG_RTC_FREQUENCY 80000000 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch b/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch new file mode 100644 index 0000000..8772f9c --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType"> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.ui.externaltools.launchGroup"/> +</listAttribute> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="${eclipse_home}\..\tools\openocd\bin\openocd.exe"/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-c "telnet_port 4444" -f "interface/ti-icdi.cfg" -f "${file_prompt}""/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${eclipse_home}\..\tools\openocd\bin\"/> +</launchConfiguration> diff --git a/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch b/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..d963642 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType"> 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key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/> +<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="dmachis-spi_serve_interrupt-(format)" val="0"/></contentList>"/> +<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="TM4C123x-EXT"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/TM4C123x-EXT"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/> +</listAttribute> +</launchConfiguration> diff --git a/testhal/TIVA/TM4C123x/EXT/halconf.h b/testhal/TIVA/TM4C123x/EXT/halconf.h new file mode 100644 index 0000000..bb46d6e --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/halconf.h @@ -0,0 +1,278 @@ +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/EXT/main.c b/testhal/TIVA/TM4C123x/EXT/main.c new file mode 100644 index 0000000..3d15451 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/main.c @@ -0,0 +1,126 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void extcb1(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + (void)channel; + + palTogglePad(GPIOF, GPIOF_LED_RED); +} + +static void extcb2(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + (void)channel; + + palTogglePad(GPIOF, GPIOF_LED_GREEN); +} + +static const EXTConfig extcfg = +{ + { + /* GPIOA */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOB */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOC */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOD */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOE */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOF */ + {EXT_CH_MODE_FALLING_EDGE | EXT_CH_MODE_AUTOSTART, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) +{ + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOF, GPIOF_SW1, PAL_MODE_INPUT_PULLUP); + palSetPadMode(GPIOF, GPIOF_SW2, PAL_MODE_INPUT_PULLUP); + + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + + return 0; +} diff --git a/testhal/TIVA/TM4C123x/EXT/mcuconf.h b/testhal/TIVA/TM4C123x/EXT/mcuconf.h new file mode 100644 index 0000000..99b4536 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/mcuconf.h @@ -0,0 +1,152 @@ +/* + * TM4C123x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...Highest. + */ + +#define TM4C123x_MCUCONF + +/* + * HAL driver system settings. + */ +#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_MOSC_ENABLE TRUE +#define TIVA_DIV400_VALUE 1 +#define TIVA_SYSDIV_VALUE 2 +#define TIVA_USESYSDIV_ENABLE FALSE +#define TIVA_SYSDIV2LSB_ENABLE FALSE +#define TIVA_BYPASS_VALUE 0 +#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ + TIVA_RCC_PWMDIV_8) + +/* + * GPIO driver system settings. + */ +#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#define TIVA_GPIO_GPIOF_USE_AHB TRUE + +/* + * GPT driver system settings. + */ +#define TIVA_GPT_USE_GPT0 FALSE +#define TIVA_GPT_USE_GPT1 FALSE +#define TIVA_GPT_USE_GPT2 FALSE +#define TIVA_GPT_USE_GPT3 FALSE +#define TIVA_GPT_USE_GPT4 FALSE +#define TIVA_GPT_USE_GPT5 FALSE +#define TIVA_GPT_USE_WGPT0 FALSE +#define TIVA_GPT_USE_WGPT1 FALSE +#define TIVA_GPT_USE_WGPT2 FALSE +#define TIVA_GPT_USE_WGPT3 FALSE +#define TIVA_GPT_USE_WGPT4 FALSE +#define TIVA_GPT_USE_WGPT5 FALSE + +#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define TIVA_I2C_USE_I2C0 FALSE +#define TIVA_I2C_USE_I2C1 FALSE +#define TIVA_I2C_USE_I2C2 FALSE +#define TIVA_I2C_USE_I2C3 FALSE +#define TIVA_I2C_USE_I2C4 FALSE +#define TIVA_I2C_USE_I2C5 FALSE +#define TIVA_I2C_USE_I2C6 FALSE +#define TIVA_I2C_USE_I2C7 FALSE +#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 + +/* + * PWM driver system settings. + */ +#define TIVA_PWM_USE_PWM0 FALSE +#define TIVA_PWM_USE_PWM1 FALSE +#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 + +/* + * SERIAL driver system settings. + */ +#define TIVA_SERIAL_USE_UART0 FALSE +#define TIVA_SERIAL_USE_UART1 FALSE +#define TIVA_SERIAL_USE_UART2 FALSE +#define TIVA_SERIAL_USE_UART3 FALSE +#define TIVA_SERIAL_USE_UART4 FALSE +#define TIVA_SERIAL_USE_UART5 FALSE +#define TIVA_SERIAL_USE_UART6 FALSE +#define TIVA_SERIAL_USE_UART7 FALSE +#define TIVA_SERIAL_UART0_PRIORITY 5 +#define TIVA_SERIAL_UART1_PRIORITY 5 +#define TIVA_SERIAL_UART2_PRIORITY 5 +#define TIVA_SERIAL_UART3_PRIORITY 5 +#define TIVA_SERIAL_UART4_PRIORITY 5 +#define TIVA_SERIAL_UART5_PRIORITY 5 +#define TIVA_SERIAL_UART6_PRIORITY 5 +#define TIVA_SERIAL_UART7_PRIORITY 5 + +/* + * SPI driver system settings. + */ +#define TIVA_SPI_USE_SSI0 TRUE +#define TIVA_SPI_USE_SSI1 FALSE +#define TIVA_SPI_USE_SSI2 FALSE +#define TIVA_SPI_USE_SSI3 FALSE +#define TIVA_SPI_SSI0_RX_UDMA_CHANNEL 10 +#define TIVA_SPI_SSI1_RX_UDMA_CHANNEL 24 +#define TIVA_SPI_SSI2_RX_UDMA_CHANNEL 12 +#define TIVA_SPI_SSI3_RX_UDMA_CHANNEL 14 +#define TIVA_SPI_SSI0_TX_UDMA_CHANNEL 11 +#define TIVA_SPI_SSI1_TX_UDMA_CHANNEL 25 +#define TIVA_SPI_SSI2_TX_UDMA_CHANNEL 13 +#define TIVA_SPI_SSI3_TX_UDMA_CHANNEL 15 +#define TIVA_SPI_SSI0_RX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI1_RX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI2_RX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI3_RX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI0_TX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI1_TX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI2_TX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI3_TX_UDMA_MAPPING 2 + +/* + * ST driver system settings. + */ +#define TIVA_ST_IRQ_PRIORITY 2 +#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_TIMER_NUMBER 5 +#define TIVA_ST_TIMER_LETTER A diff --git a/testhal/TIVA/TM4C123x/GPT/Makefile b/testhal/TIVA/TM4C123x/GPT/Makefile index abbd840..43de29b 100644 --- a/testhal/TIVA/TM4C123x/GPT/Makefile +++ b/testhal/TIVA/TM4C123x/GPT/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,31 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +133,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +160,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/I2C/Makefile b/testhal/TIVA/TM4C123x/I2C/Makefile index 4123eb6..3aa487c 100644 --- a/testhal/TIVA/TM4C123x/I2C/Makefile +++ b/testhal/TIVA/TM4C123x/I2C/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,27 +81,33 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - main.c \ - $(CHIBIOS)/os/various/chprintf.c + $(TESTSRC) \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -123,11 +134,11 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various $(CHIBIOS)/os/hal/lib/streams # # Project, sources and paths @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/PWM/Makefile b/testhal/TIVA/TM4C123x/PWM/Makefile index e3845c1..43de29b 100644 --- a/testhal/TIVA/TM4C123x/PWM/Makefile +++ b/testhal/TIVA/TM4C123x/PWM/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,31 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +133,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +160,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/SPI/Makefile b/testhal/TIVA/TM4C123x/SPI/Makefile index e3845c1..43de29b 100644 --- a/testhal/TIVA/TM4C123x/SPI/Makefile +++ b/testhal/TIVA/TM4C123x/SPI/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,31 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +133,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +160,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex |
