diff options
Diffstat (limited to 'demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h')
| -rw-r--r-- | demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h index da7ba95..9118e7b 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h @@ -24,11 +24,23 @@ */
/* Select the MCU clocking mode below by enabling the appropriate block. */
+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
-/* FEI mode */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode - ~24MHz */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
-#define KINETIS_SYSCLK_FREQUENCY 21000000UL
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
@@ -36,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
@@ -49,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
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