diff options
Diffstat (limited to 'os/hal/ports/NRF5/LLD')
35 files changed, 1713 insertions, 20 deletions
diff --git a/os/hal/ports/NRF5/LLD/ADCv1/driver.mk b/os/hal/ports/NRF5/LLD/ADCv1/driver.mk new file mode 100644 index 0000000..88deb3e --- /dev/null +++ b/os/hal/ports/NRF5/LLD/ADCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv1
diff --git a/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c new file mode 100644 index 0000000..e1d8bc6 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.c @@ -0,0 +1,227 @@ +/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ADCv1/adc_lld.c
+ * @brief NRF51 ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+#define ADC_CHANNEL_MASK 0x7
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void adc_lld_config_next_channel(ADCDriver *adcp, uint32_t config) {
+
+ /* Default to all analog input pins disabled */
+ config &= ~ADC_CONFIG_PSEL_Msk;
+
+ if (adcp->grpp->channel_mask) {
+ /* Skip to the next channel */
+ while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0)
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ config |= (((1 << adcp->current_channel) << ADC_CONFIG_PSEL_Pos) & ADC_CONFIG_PSEL_Msk);
+ }
+
+ /* Setup analog input pin select and user config values */
+ adcp->adc->CONFIG = config;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+ ADCDriver *adcp = &ADCD1;
+ NRF_ADC_Type *adc = adcp->adc;
+ bool more = true;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear the ADC event */
+ adc->EVENTS_END = 0;
+
+ /* Read the sample into the buffer */
+ adcp->samples[adcp->current_index++] = adc->RESULT;
+
+ /* At the end of the buffer then we may be finished */
+ if (adcp->current_index == adcp->number_of_samples) {
+ _adc_isr_full_code(adcp);
+
+ adcp->current_index = 0;
+
+ /* We are never finished in circular mode */
+ more = adcp->grpp->circular;
+ }
+
+ if (more) {
+
+ /* Signal half completion in circular mode. */
+ if (adcp->grpp->circular &&
+ (adcp->current_index == (adcp->number_of_samples / 2))) {
+
+ _adc_isr_half_code(adcp);
+ }
+
+ /* Skip to the next channel */
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ adc_lld_config_next_channel(adcp, adcp->adc->CONFIG);
+ adcp->adc->TASKS_START = 1;
+ } else {
+ adc_lld_stop_conversion(adcp);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if NRF5_ADC_USE_ADC1
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.adc = NRF_ADC;
+#endif
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ /* If in stopped state then configures and enables the ADC. */
+ if (adcp->state == ADC_STOP) {
+#if NRF5_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+
+ adcp->adc->INTENSET = ADC_INTENSET_END_Enabled << ADC_INTENSET_END_Pos;
+ nvicEnableVector(ADC_IRQn, NRF5_ADC_IRQ_PRIORITY);
+ }
+#endif /* NRF5_ADC_USE_ADC1 */
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock and analog part.*/
+ if (adcp->state == ADC_READY) {
+
+#if NRF5_ADC_USE_ADC1
+ if (&ADCD1 == adcp) {
+
+ nvicDisableVector(ADC_IRQn);
+ adcp->adc->INTENCLR = ADC_INTENCLR_END_Clear << ADC_INTENCLR_END_Pos;
+ adc_lld_stop_conversion(adcp);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+
+ NRF_ADC_Type *adc = adcp->adc;
+
+ adcp->number_of_samples = adcp->depth * adcp->grpp->num_channels;
+ adcp->current_index = 0;
+
+ /* At least one sample must be configured */
+ osalDbgAssert(adcp->number_of_samples, "must configure at least one sample");
+
+ /* Skip to the next channel */
+ adcp->current_channel = 0;
+ adc_lld_config_next_channel(adcp, adcp->grpp->cfg);
+
+ /* Enable and start the conversion */
+ adc->ENABLE = ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos;
+ adc->TASKS_START = 1;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+ NRF_ADC_Type *adc = adcp->adc;
+
+ adc->TASKS_STOP = 1;
+ adc->ENABLE = ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.h new file mode 100644 index 0000000..4e185d5 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/ADCv1/hal_adc_lld.h @@ -0,0 +1,229 @@ +/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ADCv1/adc_lld.h
+ * @brief NRF51 ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(NRF5_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define NRF5_ADC_USE_ADC1 FALSE
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(NRF5_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_ADC_IRQ_PRIORITY 2
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !NRF5_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if NRF5_ADC_USE_ADC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ADC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint8_t adc_channels_num_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * STM32 ADC cell registers interface, please refer to the STM32
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Bitmask of channels for ADC conversion.
+ */
+ uint32_t channel_mask;
+ /**
+ * @brief ADC CONFIG register details.
+ * @note All the required bits must be defined into this field.
+ */
+ uint32_t cfg;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ uint32_t dummy;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ NRF_ADC_Type *adc;
+ /**
+ * @brief Number of samples expected.
+ */
+ size_t number_of_samples;
+ /**
+ * @brief Current position in the buffer.
+ */
+ size_t current_index;
+ /**
+ * @brief Current channel index into group channel_mask.
+ */
+ size_t current_channel;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if NRF5_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/GPIOTEv1/driver.mk b/os/hal/ports/NRF5/LLD/GPIOTEv1/driver.mk new file mode 100644 index 0000000..97e0660 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/GPIOTEv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOTEv1
diff --git a/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.c b/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.c new file mode 100644 index 0000000..f38fa0c --- /dev/null +++ b/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.c @@ -0,0 +1,168 @@ +/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GPIOTEv1/ext_lld.c
+ * @brief NRF51 EXT subsystem low level driver source.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "hal_ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTD1 driver identifier.
+ */
+EXTDriver EXTD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level EXT driver initialization.
+ *
+ * @notapi
+ */
+void ext_lld_init(void) {
+
+ /* Driver initialization.*/
+ extObjectInit(&EXTD1);
+}
+
+/**
+ * @brief Configures and activates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_start(EXTDriver *extp) {
+
+ unsigned i;
+
+ ext_lld_exti_irq_enable();
+
+ /* Configuration of automatic channels.*/
+ for (i = 0; i < EXT_MAX_CHANNELS; i++) {
+ uint32_t config = 0;
+ uint32_t pad = (extp->config->channels[i].mode & EXT_MODE_GPIO_MASK)
+ >> EXT_MODE_GPIO_OFFSET;
+
+ if (extp->config->channels[i].mode & EXT_CH_MODE_BOTH_EDGES)
+ config |= (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
+ else if (extp->config->channels[i].mode & EXT_CH_MODE_RISING_EDGE)
+ config |= (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
+ else
+ config |= (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
+
+ config |= (pad << GPIOTE_CONFIG_PSEL_Pos);
+
+ NRF_GPIOTE->CONFIG[i] = config;
+ NRF_GPIOTE->EVENTS_PORT = 0;
+ NRF_GPIOTE->EVENTS_IN[i] = 0;
+
+ if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
+ ext_lld_channel_enable(extp, i);
+ else
+ ext_lld_channel_disable(extp, i);
+ }
+}
+
+/**
+ * @brief Deactivates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_stop(EXTDriver *extp) {
+
+ unsigned i;
+
+ (void)extp;
+ ext_lld_exti_irq_disable();
+
+ for (i = 0; i < EXT_MAX_CHANNELS; i++)
+ NRF_GPIOTE->CONFIG[i] = 0;
+
+ NRF_GPIOTE->INTENCLR =
+ (GPIOTE_INTENCLR_IN3_Msk | GPIOTE_INTENCLR_IN2_Msk |
+ GPIOTE_INTENCLR_IN1_Msk | GPIOTE_INTENCLR_IN0_Msk);
+}
+
+/**
+ * @brief Enables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be enabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+
+ uint32_t config = NRF_GPIOTE->CONFIG[channel] & ~GPIOTE_CONFIG_MODE_Msk;
+
+ (void)extp;
+ config |= (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos);
+
+ NRF_GPIOTE->CONFIG[channel] = config;
+ NRF_GPIOTE->INTENSET = (1 << channel);
+}
+
+/**
+ * @brief Disables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be disabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+
+ (void)extp;
+ NRF_GPIOTE->CONFIG[channel] &= ~GPIOTE_CONFIG_MODE_Msk;
+ NRF_GPIOTE->INTENCLR = (1 << channel);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.h b/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.h new file mode 100644 index 0000000..8a93b6d --- /dev/null +++ b/os/hal/ports/NRF5/LLD/GPIOTEv1/hal_ext_lld.h @@ -0,0 +1,139 @@ +/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GPIOTEv1/ext_lld.h
+ * @brief NRF51 EXT subsystem low level driver header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_H
+#define HAL_EXT_LLD_H
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Available number of EXT channels.
+ */
+#define EXT_MAX_CHANNELS 4
+#define EXT_MODE_GPIO_MASK 0xF8 /**< @brief Pad field mask. */
+#define EXT_MODE_GPIO_OFFSET 3 /**< @brief Pad field offset. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief EXT channel identifier.
+ */
+typedef uint32_t expchannel_t;
+
+/**
+ * @brief Type of an EXT generic notification callback.
+ *
+ * @param[in] extp pointer to the @p EXPDriver object triggering the
+ * callback
+ */
+typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
+
+/**
+ * @brief Channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel mode.
+ */
+ uint32_t mode;
+ /**
+ * @brief Channel callback.
+ * @details In the STM32 implementation a @p NULL callback pointer is
+ * valid and configures the channel as an event sources instead
+ * of an interrupt source.
+ */
+ extcallback_t cb;
+} EXTChannelConfig;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Channel configurations.
+ */
+ EXTChannelConfig channels[EXT_MAX_CHANNELS];
+ /* End of the mandatory fields.*/
+} EXTConfig;
+
+/**
+ * @brief Structure representing an EXT driver.
+ */
+struct EXTDriver {
+ /**
+ * @brief Driver state.
+ */
+ extstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const EXTConfig *config;
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern EXTDriver EXTD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_init(void);
+ void ext_lld_start(EXTDriver *extp);
+ void ext_lld_stop(EXTDriver *extp);
+ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
+ void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk b/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk new file mode 100644 index 0000000..a627fab --- /dev/null +++ b/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1
diff --git a/os/hal/ports/NRF5/LLD/hal_pal_lld.c b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c index 21e4b0b..9cfad8d 100644 --- a/os/hal/ports/NRF5/LLD/hal_pal_lld.c +++ b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_pal_lld.c
+ * @file GPIOv1/hal_pal_lld.c
* @brief NRF5 PAL subsystem low level driver source.
*
* @addtogroup PAL
diff --git a/os/hal/ports/NRF5/LLD/hal_pal_lld.h b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.h index 745afd3..a005d50 100644 --- a/os/hal/ports/NRF5/LLD/hal_pal_lld.h +++ b/os/hal/ports/NRF5/LLD/GPIOv1/hal_pal_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_pal_lld.h
+ * @file GPIOv1/hal_pal_lld.h
* @brief NRF5 PAL subsystem low level driver header.
*
* @addtogroup PAL
@@ -119,6 +119,11 @@ typedef uint32_t ioline_t; */
typedef NRF_GPIO_Type *ioportid_t;
+/**
+ * @brief Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
/*===========================================================================*/
/* I/O Ports Identifiers. */
/*===========================================================================*/
diff --git a/os/hal/ports/NRF5/LLD/PWMv1/driver.mk b/os/hal/ports/NRF5/LLD/PWMv1/driver.mk new file mode 100644 index 0000000..d64b5dc --- /dev/null +++ b/os/hal/ports/NRF5/LLD/PWMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv1
diff --git a/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c new file mode 100644 index 0000000..d5201b8 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.c @@ -0,0 +1,492 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Stéphane D'Alu
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file PWMv1/hal_pwm_lld.c
+ * @brief NRF51 PWM subsystem low level driver source.
+ *
+ * @note Using the method described in nrf51-pwm-library to correctly
+ * handle toggling of the pin with GPIOTE when changing period.
+ * It means it is generally unsafe to use GPIOTE with a period
+ * less than (2 * PWM_GPIOTE_DECISION_TIME / 16MHz)
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define PWM_GPIOTE_PPI_CC 3
+#define PWM_GPIOTE_DECISION_TIME 160
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer TIMER0 when enabled.
+ */
+#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer TIMER1 when enabled.
+ */
+#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer TIMER2 when enabled.
+ */
+#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+static const uint8_t pwm_margin_by_prescaler[] = {
+ (PWM_GPIOTE_DECISION_TIME + 0) >> 0,
+ (PWM_GPIOTE_DECISION_TIME + 1) >> 1,
+ (PWM_GPIOTE_DECISION_TIME + 3) >> 2,
+ (PWM_GPIOTE_DECISION_TIME + 7) >> 3,
+ (PWM_GPIOTE_DECISION_TIME + 15) >> 4,
+ (PWM_GPIOTE_DECISION_TIME + 31) >> 5,
+ (PWM_GPIOTE_DECISION_TIME + 63) >> 6,
+ (PWM_GPIOTE_DECISION_TIME + 127) >> 7,
+ (PWM_GPIOTE_DECISION_TIME + 255) >> 8,
+ (PWM_GPIOTE_DECISION_TIME + 511) >> 9
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint8_t channel;
+ /* Deal with PWM channels
+ */
+ for (channel = 0 ; channel < pwmp->channels ; channel++) {
+ if (pwmp->timer->EVENTS_COMPARE[channel]) {
+ pwmp->timer->EVENTS_COMPARE[channel] = 0;
+
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->config->channels[channel].callback(pwmp);
+ }
+ }
+ }
+
+ /* Deal with PWM period
+ */
+ if (pwmp->timer->EVENTS_COMPARE[pwmp->channels]) {
+ pwmp->timer->EVENTS_COMPARE[pwmp->channels] = 0;
+
+ if (pwmp->config->callback != NULL) {
+ pwmp->config->callback(pwmp);
+ }
+ }
+}
+
+static inline
+bool pwm_within_safe_margins(PWMDriver *pwmp, uint32_t timer, uint32_t width) {
+ const uint32_t margin = pwm_margin_by_prescaler[pwmp->timer->PRESCALER];
+ return (width <= margin)
+ ? ((width <= timer) && (timer < (pwmp->period + width - margin)))
+ : ((width <= timer) || (timer < (width - margin)));
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if NRF5_PWM_USE_TIMER0
+/**
+ * @brief TIMER0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* NRF5_PWM_USE_TIMER0 */
+
+#if NRF5_PWM_USE_TIMER1
+/**
+ * @brief TIMER1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* NRF5_PWM_USE_TIMER1 */
+
+#if NRF5_PWM_USE_TIMER2
+/**
+ * @brief TIMER2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* NRF5_PWM_USE_TIMER2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if NRF5_PWM_USE_TIMER0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = PWM_CHANNELS;
+ PWMD1.timer = NRF_TIMER0;
+#endif
+
+#if NRF5_PWM_USE_TIMER1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = PWM_CHANNELS;
+ PWMD2.timer = NRF_TIMER1;
+#endif
+
+#if NRF5_PWM_USE_TIMER2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = PWM_CHANNELS;
+ PWMD3.timer = NRF_TIMER2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ /* Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER */
+ uint16_t psc_ratio = NRF5_HFCLK_FREQUENCY / pwmp->config->frequency;
+ /* Prescaler ratio must be between 1 and 512, and a power of two. */
+ osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)),
+ "invalid frequency");
+ /* Prescaler value as a power of 2, must be 0..9 */
+ uint32_t psc_value;
+ for (psc_value = 0; psc_value < 10; psc_value++)
+ if (psc_ratio == (unsigned)(1 << psc_value))
+ break;
+
+ /* Configure as 16bits timer (only TIMER0 support 32bits) */
+ pwmp->timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
+ pwmp->timer->MODE = TIMER_MODE_MODE_Timer;
+
+ /* With clear shortcuts for period */
+ pwmp->timer->SHORTS =
+ 0x1UL << (TIMER_SHORTS_COMPARE0_CLEAR_Pos + pwmp->channels);
+
+ /* Disable and reset interrupts for compare events */
+ pwmp->timer->INTENCLR = (TIMER_INTENCLR_COMPARE0_Msk |
+ TIMER_INTENCLR_COMPARE1_Msk |
+ TIMER_INTENCLR_COMPARE2_Msk |
+ TIMER_INTENCLR_COMPARE3_Msk );
+ pwmp->timer->EVENTS_COMPARE[0] = 0;
+ pwmp->timer->EVENTS_COMPARE[1] = 0;
+ pwmp->timer->EVENTS_COMPARE[2] = 0;
+ pwmp->timer->EVENTS_COMPARE[3] = 0;
+
+ /* Set prescaler */
+ pwmp->timer->PRESCALER = psc_value;
+
+ /* Set period */
+ pwmp->timer->CC[pwmp->channels] = pwmp->period;
+
+ /* Clear everything */
+ pwmp->timer->TASKS_CLEAR = 1;
+
+ /* Enable interrupt */
+#if NRF5_PWM_USE_TIMER0
+ if (&PWMD1 == pwmp) {
+ nvicEnableVector(TIMER0_IRQn, NRF5_PWM_TIMER0_PRIORITY);
+ }
+#endif
+
+#if NRF5_PWM_USE_TIMER1
+ if (&PWMD2 == pwmp) {
+ nvicEnableVector(TIMER1_IRQn, NRF5_PWM_TIMER1_PRIORITY);
+ }
+#endif
+
+#if NRF5_PWM_USE_TIMER2
+ if (&PWMD3 == pwmp) {
+ nvicEnableVector(TIMER2_IRQn, NRF5_PWM_TIMER2_PRIORITY);
+ }
+#endif
+
+ /* Start timer */
+ pwmp->timer->TASKS_START = 1;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+ pwmp->timer->TASKS_SHUTDOWN = 1;
+
+#if NRF5_PWM_USE_TIMER0
+ if (&PWMD1 == pwmp) {
+ nvicDisableVector(TIMER0_IRQn);
+ }
+#endif
+
+#if NRF5_PWM_USE_TIMER1
+ if (&PWMD2 == pwmp) {
+ nvicDisableVector(TIMER1_IRQn);
+ }
+#endif
+
+#if NRF5_PWM_USE_TIMER2
+ if (&PWMD3 == pwmp) {
+ nvicDisableVector(TIMER2_IRQn);
+ }
+#endif
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+#if NRF5_PWM_USE_GPIOTE_PPI
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+ const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
+ const uint8_t *ppi_channel = cfg_channel->ppi_channel;
+
+ uint32_t outinit;
+ switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_LOW : outinit = GPIOTE_CONFIG_OUTINIT_Low; break;
+ case PWM_OUTPUT_ACTIVE_HIGH: outinit = GPIOTE_CONFIG_OUTINIT_High; break;
+ case PWM_OUTPUT_DISABLED : /* fall-through */
+ default : goto no_output_config;
+ }
+
+ /* Deal with corner case: 0% and 100% */
+ if ((width <= 0) || (width >= pwmp->period)) {
+ /* Disable GPIOTE/PPI task */
+ NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Disabled;
+ NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
+ /* Set Line */
+ palWriteLine(cfg_channel->ioline,
+ ((width <= 0) ^
+ ((cfg_channel->mode & PWM_OUTPUT_MASK) == PWM_OUTPUT_ACTIVE_HIGH)));
+
+ /* Really doing PWM */
+ } else {
+ const uint32_t gpio_pin = PAL_PAD(cfg_channel->ioline);
+ const uint32_t polarity = GPIOTE_CONFIG_POLARITY_Toggle;
+
+ /* Program tasks (one for duty cycle, one for periode) */
+ NRF_PPI->CH[ppi_channel[0]].EEP =
+ (uint32_t)&pwmp->timer->EVENTS_COMPARE[channel];
+ NRF_PPI->CH[ppi_channel[0]].TEP =
+ (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
+ NRF_PPI->CH[ppi_channel[1]].EEP =
+ (uint32_t)&pwmp->timer->EVENTS_COMPARE[pwmp->channels];
+ NRF_PPI->CH[ppi_channel[1]].TEP =
+ (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
+ NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
+
+ /* Something Old, something New */
+ const uint32_t old_width = pwmp->timer->CC[channel];
+ const uint32_t new_width = width;
+
+ /* Check GPIOTE state */
+ const bool gpiote = (NRF_GPIOTE->CONFIG[gpiote_channel] &
+ GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
+
+ /* GPIOTE is currently running */
+ if (gpiote) {
+ uint32_t current;
+ while (true) {
+ pwmp->timer->TASKS_CAPTURE[PWM_GPIOTE_PPI_CC] = 1;
+ current = pwmp->timer->CC[PWM_GPIOTE_PPI_CC];
+
+ if (pwm_within_safe_margins(pwmp, current, old_width) &&
+ pwm_within_safe_margins(pwmp, current, new_width))
+ break;
+ }
+ if (((old_width <= current) && (current < new_width)) ||
+ ((new_width <= current) && (current < old_width))) {
+ NRF_GPIOTE->TASKS_OUT[gpiote_channel] = 1;
+ }
+
+ /* GPIOTE need to be restarted */
+ } else {
+ /* Create GPIO Task */
+ NRF_GPIOTE->CONFIG[gpiote_channel] =
+ (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
+ ((gpio_pin << GPIOTE_CONFIG_PSEL_Pos ) & GPIOTE_CONFIG_PSEL_Msk )|
+ ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk)|
+ ((outinit << GPIOTE_CONFIG_OUTINIT_Pos ) & GPIOTE_CONFIG_OUTINIT_Msk );
+
+ pwmp->timer->TASKS_CAPTURE[PWM_GPIOTE_PPI_CC] = 1;
+ if (pwmp->timer->CC[PWM_GPIOTE_PPI_CC] > width)
+ NRF_GPIOTE->TASKS_OUT[gpiote_channel] = 1;
+ }
+ }
+
+ no_output_config:
+#endif
+
+ pwmp->timer->CC[channel] = width;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+ pwmp->timer->CC[channel] = 0;
+#if NRF5_PWM_USE_GPIOTE_PPI
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+ switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_LOW:
+ case PWM_OUTPUT_ACTIVE_HIGH: {
+ const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
+ const uint8_t *ppi_channel = cfg_channel->ppi_channel;
+ NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
+ NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Disabled;
+ break;
+ }
+ case PWM_OUTPUT_DISABLED:
+ default:
+ break;
+ }
+#endif
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->timer->INTENSET =
+ 0x1UL << (TIMER_INTENSET_COMPARE0_Pos + pwmp->channels);
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->timer->INTENCLR =
+ 0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + pwmp->channels);
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->timer->INTENSET =
+ 0x1UL << (TIMER_INTENSET_COMPARE0_Pos + channel);
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->timer->INTENCLR =
+ 0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + channel);
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.h b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.h new file mode 100644 index 0000000..616e61a --- /dev/null +++ b/os/hal/ports/NRF5/LLD/PWMv1/hal_pwm_lld.h @@ -0,0 +1,334 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Stéphane D'Alu
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file PWMv1/hal_pwm_lld.h
+ * @brief NRF51 PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef HAL_PWM_LLD_H_
+#define HAL_PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#if NRF5_PWM_USE_GPIOTE_PPI
+#define PWM_CHANNELS 2
+#else
+#define PWM_CHANNELS 3
+#endif
+
+#define PWM_FREQUENCY_16MHZ 16000000 /** @brief 16MHz */
+#define PWM_FREQUENCY_8MHZ 8000000 /** @brief 8MHz */
+#define PWM_FREQUENCY_4MHZ 4000000 /** @brief 4MHz */
+#define PWM_FREQUENCY_2MHZ 2000000 /** @brief 2MHz */
+#define PWM_FREQUENCY_1MHZ 1000000 /** @brief 1MHz */
+#define PWM_FREQUENCY_500KHZ 500000 /** @brief 500kHz */
+#define PWM_FREQUENCY_250KHZ 250000 /** @brief 250kHz */
+#define PWM_FREQUENCY_125KHZ 125000 /** @brief 125kHz */
+#define PWM_FREQUENCY_62500HZ 62500 /** @brief 62500Hz */
+#define PWM_FREQUENCY_31250HZ 31250 /** @brief 31250Hz */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief TIMER0 as driver implementation
+ */
+#if !defined(NRF5_PWM_USE_TIMER0)
+#define NRF5_PWM_USE_TIMER0 FALSE
+#endif
+
+/**
+ * @brief TIMER1 as driver implementation
+ */
+#if !defined(NRF5_PWM_USE_TIMER1)
+#define NRF5_PWM_USE_TIMER1 FALSE
+#endif
+
+/**
+ * @brief TIMER2 as driver implementation
+ */
+#if !defined(NRF5_PWM_USE_TIMER2)
+#define NRF5_PWM_USE_TIMER2 FALSE
+#endif
+
+/**
+ * @brief TIMER0 interrupt priority level setting.
+ */
+#if !defined(NRF5_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_PWM_TIMER0_PRIORITY 3
+#endif
+
+/**
+ * @brief TIMER1 interrupt priority level setting.
+ */
+#if !defined(NRF5_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_PWM_TIMER1_PRIORITY 3
+#endif
+
+/**
+ * @brief TIMER2 interrupt priority level setting.
+ */
+#if !defined(NRF5_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
+#define NRF5_PWM_TIMER2_PRIORITY 3
+#endif
+
+/**
+ * @brief Allow driver to use GPIOTE/PPI to control PAL line
+ */
+#if !defined(NRF5_PWM_USE_GPIOTE_PPI)
+#define NRF5_PWM_USE_GPIOTE_PPI TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !NRF5_PWM_USE_TIMER0 && !NRF5_PWM_USE_TIMER1 && !NRF5_PWM_USE_TIMER2
+#error "PWM driver activated but no TIMER peripheral assigned"
+#endif
+
+#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_PWM_USE_TIMER0 == TRUE)
+#error "TIMER0 used for ST and PWM"
+#endif
+
+#if NRF5_PWM_USE_TIMER0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER0_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER0"
+#endif
+
+#if NRF5_PWM_USE_TIMER1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER1_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER1"
+#endif
+
+#if NRF5_PWM_USE_TIMER2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER2_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER2"
+#endif
+
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+
+#if NRF5_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
+ /**
+ * @brief PAL line to toggle.
+ * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
+ * @note When NRF5_PWM_USE_GPIOTE_PPI is used and channel enabled,
+ * it wont be possible to access this PAL line using the PAL
+ * driver.
+ */
+ ioline_t ioline;
+
+ /**
+ * @brief Unique GPIOTE channel to use. (1 channel)
+ * @note Only 4 GPIOTE channels are available on nRF51.
+ */
+ uint8_t gpiote_channel;
+
+ /**
+ * @brief Unique PPI channels to use. (2 channels)
+ * @note Only 16 PPI channels are available on nRF51
+ * (When Softdevice is enabled, only channels 0-7 are available)
+ */
+ uint8_t ppi_channel[2];
+#endif
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the TIMER registers block.
+ */
+ NRF_TIMER_Type *timer;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ do { \
+ (pwmp)->timer->CC[(pwmp)->channels] = ((period) - 1); \
+ } while(0)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* HAL_PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/NRF5/LLD/QDECv1/driver.mk b/os/hal/ports/NRF5/LLD/QDECv1/driver.mk new file mode 100644 index 0000000..de18c39 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/QDECv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/QDECv1
diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.c b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c index d3b99cd..f0c24c9 100644 --- a/os/hal/ports/NRF5/LLD/hal_qei_lld.c +++ b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.c @@ -15,8 +15,8 @@ */
/**
- * @file NRF51/hal_qei_lld.c
- * @brief NRF51 QEI subsystem low level driver.
+ * @file QDECv1/hal_qei_lld.c
+ * @brief NRF5 QEI subsystem low level driver.
*
* @addtogroup QEI
* @{
diff --git a/os/hal/ports/NRF5/LLD/hal_qei_lld.h b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.h index 85c96a5..f4db11e 100644 --- a/os/hal/ports/NRF5/LLD/hal_qei_lld.h +++ b/os/hal/ports/NRF5/LLD/QDECv1/hal_qei_lld.h @@ -15,8 +15,8 @@ */
/**
- * @file NRF51/hal_qei_lld.h
- * @brief NRF51 QEI subsystem low level driver header.
+ * @file QDECv1/hal_qei_lld.h
+ * @brief NRF5 QEI subsystem low level driver header.
*
* @note Not tested with LED pin
*
diff --git a/os/hal/ports/NRF5/LLD/RNGv1/driver.mk b/os/hal/ports/NRF5/LLD/RNGv1/driver.mk new file mode 100644 index 0000000..c128aae --- /dev/null +++ b/os/hal/ports/NRF5/LLD/RNGv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/RNGv1
diff --git a/os/hal/ports/NRF5/LLD/hal_rng_lld.c b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c index 9712150..bf9382c 100644 --- a/os/hal/ports/NRF5/LLD/hal_rng_lld.c +++ b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.c @@ -15,7 +15,7 @@ */ /** - * @file NRF5/LLD/hal_rng_lld.c + * @file RNGv1/hal_rng_lld.c * @brief NRF5 RNG subsystem low level driver source. * * @addtogroup RNG diff --git a/os/hal/ports/NRF5/LLD/hal_rng_lld.h b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.h index 5c56be2..a74f6ef 100644 --- a/os/hal/ports/NRF5/LLD/hal_rng_lld.h +++ b/os/hal/ports/NRF5/LLD/RNGv1/hal_rng_lld.h @@ -15,7 +15,7 @@ */ /** - * @file NRF5/LLD/hal_rng_lld.h + * @file RNGv1/hal_rng_lld.h * @brief NRF5 RNG subsystem low level driver header. * * @addtogroup RNG diff --git a/os/hal/ports/NRF5/LLD/SPIv1/driver.mk b/os/hal/ports/NRF5/LLD/SPIv1/driver.mk new file mode 100644 index 0000000..d583a68 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/SPIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1
diff --git a/os/hal/ports/NRF5/LLD/hal_spi_lld.c b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c index 2c6ec91..95bb9b7 100644 --- a/os/hal/ports/NRF5/LLD/hal_spi_lld.c +++ b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_spi_lld.c
+ * @file SPIv1/hal_spi_lld.c
* @brief NRF5 low level SPI driver code.
*
* @addtogroup SPI
diff --git a/os/hal/ports/NRF5/LLD/hal_spi_lld.h b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.h index afad5ab..1c6d858 100644 --- a/os/hal/ports/NRF5/LLD/hal_spi_lld.h +++ b/os/hal/ports/NRF5/LLD/SPIv1/hal_spi_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF/LLD/hal_spi_lld.h
+ * @file SPIv1/hal_spi_lld.h
* @brief NRF5 low level SPI driver header.
*
* @addtogroup SPI
diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk b/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk new file mode 100644 index 0000000..6f3ce0e --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TIMERv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TIMERv1
diff --git a/os/hal/ports/NRF5/LLD/hal_gpt_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c index 20dbcef..aaff432 100644 --- a/os/hal/ports/NRF5/LLD/hal_gpt_lld.c +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_gpt_lld.c
+ * @file TIMERv1/hal_gpt_lld.c
* @brief NRF5 GPT subsystem low level driver source.
*
* @addtogroup GPT
diff --git a/os/hal/ports/NRF5/LLD/hal_gpt_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.h index 4173a3a..d362106 100644 --- a/os/hal/ports/NRF5/LLD/hal_gpt_lld.h +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_gpt_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/gpt_lld.h
+ * @file TIMERv1/gpt_lld.h
* @brief NRF5 GPT subsystem low level driver header.
*
* @addtogroup GPT
diff --git a/os/hal/ports/NRF5/LLD/hal_st_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c index 8e42029..20aa6e0 100644 --- a/os/hal/ports/NRF5/LLD/hal_st_lld.c +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.c @@ -16,7 +16,7 @@ */
/**
- * @file NRF5/LLD/hal_st_lld.c
+ * @file TIMERv1/hal_st_lld.c
* @brief NRF5 ST subsystem low level driver source.
*
* @addtogroup ST
diff --git a/os/hal/ports/NRF5/LLD/hal_st_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.h index 93c2abb..c026d2b 100644 --- a/os/hal/ports/NRF5/LLD/hal_st_lld.h +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_st_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/st_lld.h
+ * @file TIMERv1/st_lld.h
* @brief NRF5 ST subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
diff --git a/os/hal/ports/NRF5/LLD/TWIv1/driver.mk b/os/hal/ports/NRF5/LLD/TWIv1/driver.mk new file mode 100644 index 0000000..3bc55d8 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/TWIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIv1
diff --git a/os/hal/ports/NRF5/LLD/hal_i2c_lld.c b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c index fefca0c..9f75906 100644 --- a/os/hal/ports/NRF5/LLD/hal_i2c_lld.c +++ b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_i2c_lld.c
+ * @file TWIv1/hal_i2c_lld.c
* @brief NRF5 I2C subsystem low level driver source.
*
* @addtogroup I2C
diff --git a/os/hal/ports/NRF5/LLD/hal_i2c_lld.h b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.h index 578d69b..7a4050b 100644 --- a/os/hal/ports/NRF5/LLD/hal_i2c_lld.h +++ b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_i2c_lld.h
+ * @file TWIv1/hal_i2c_lld.h
* @brief NRF5 I2C subsystem low level driver header.
*
* @addtogroup I2C
diff --git a/os/hal/ports/NRF5/LLD/UARTv1/driver.mk b/os/hal/ports/NRF5/LLD/UARTv1/driver.mk new file mode 100644 index 0000000..5b4f634 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/UARTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1
diff --git a/os/hal/ports/NRF5/LLD/hal_serial_lld.c b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c index 42091e8..76ba0e0 100644 --- a/os/hal/ports/NRF5/LLD/hal_serial_lld.c +++ b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_serial_lld.c
+ * @file UARTv1/hal_serial_lld.c
* @brief NRF5 serial subsystem low level driver source.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/NRF5/LLD/hal_serial_lld.h b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.h index 741a40a..9c76777 100644 --- a/os/hal/ports/NRF5/LLD/hal_serial_lld.h +++ b/os/hal/ports/NRF5/LLD/UARTv1/hal_serial_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_serial_lld.h
+ * @file UARTv1/hal_serial_lld.h
* @brief NRF5 serial subsystem low level driver header.
*
* @addtogroup SERIAL
diff --git a/os/hal/ports/NRF5/LLD/WDTv1/driver.mk b/os/hal/ports/NRF5/LLD/WDTv1/driver.mk new file mode 100644 index 0000000..07e0fb9 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/WDTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c
+endif
+else
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c
+endif
+
+PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/WDTv1
diff --git a/os/hal/ports/NRF5/LLD/hal_wdg_lld.c b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c index 35c079f..7bd2966 100644 --- a/os/hal/ports/NRF5/LLD/hal_wdg_lld.c +++ b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_wdg_lld.c
+ * @file WDTv1/hal_wdg_lld.c
* @brief NRF5 Watchdog Driver subsystem low level driver source template.
*
* @addtogroup WDG
diff --git a/os/hal/ports/NRF5/LLD/hal_wdg_lld.h b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.h index 109b67e..c478919 100644 --- a/os/hal/ports/NRF5/LLD/hal_wdg_lld.h +++ b/os/hal/ports/NRF5/LLD/WDTv1/hal_wdg_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file NRF5/LLD/hal_wdg_lld.h
+ * @file WDTv1/hal_wdg_lld.h
* @brief NRF5 Watchdog Driver subsystem low level driver header template.
*
* @addtogroup WDG
|