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-rw-r--r--os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_ext_lld.c)72
-rw-r--r--os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_ext_lld.h)0
-rw-r--r--os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_pal_lld.c)61
-rw-r--r--os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_pal_lld.h)76
-rw-r--r--os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_gpt_lld.c)138
-rw-r--r--os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_gpt_lld.h)4
-rw-r--r--os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_st_lld.c)30
-rw-r--r--os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_st_lld.h)46
-rw-r--r--os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_i2c_lld.c)184
-rw-r--r--os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_i2c_lld.h)76
-rw-r--r--os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_mac_lld.c)128
-rw-r--r--os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_mac_lld.h)0
-rw-r--r--os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_pwm_lld.c)133
-rw-r--r--os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_pwm_lld.h)10
-rw-r--r--os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_spi_lld.c)158
-rw-r--r--os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_spi_lld.h)86
-rw-r--r--os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_serial_lld.c)207
-rw-r--r--os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_serial_lld.h)181
-rw-r--r--os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c (renamed from os/hal/ports/TIVA/LLD/hal_wdg_lld.c)38
-rw-r--r--os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h (renamed from os/hal/ports/TIVA/LLD/hal_wdg_lld.h)19
-rw-r--r--os/hal/ports/TIVA/LLD/tiva_gpt.h135
-rw-r--r--os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c (renamed from os/hal/ports/TIVA/LLD/tiva_udma.c)12
-rw-r--r--os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h (renamed from os/hal/ports/TIVA/LLD/tiva_udma.h)65
23 files changed, 712 insertions, 1147 deletions
diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
index efe6421..d0788f4 100644
--- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
@@ -34,11 +34,11 @@
* @brief Generic interrupt serving code for multiple pins per interrupt
* handler.
*/
-#define ext_lld_serve_port_interrupt(gpiop, start) \
+#define ext_lld_serve_port_interrupt(gpio, start) \
do { \
- uint32_t mis = gpiop->MIS; \
+ uint32_t mis = HWREG(gpio + GPIO_O_MIS); \
\
- gpiop->ICR = mis; \
+ HWREG(gpio + GPIO_O_ICR) = mis; \
\
if (mis & (1 << 0)) { \
EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \
@@ -89,7 +89,7 @@ EXTDriver EXTD1;
/* Driver local variables and types. */
/*===========================================================================*/
-const ioportid_t gpio[] =
+const ioportid_t gpio_table[] =
{
#if TIVA_HAS_GPIOA
GPIOA,
@@ -847,58 +847,58 @@ void ext_lld_stop(EXTDriver *extp)
}
#if TIVA_HAS_GPIOA
- GPIOA->IM = 0;
+ HWREG(GPIOA + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOB
- GPIOB->IM = 0;
+ HWREG(GPIOB + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOC
- GPIOC->IM = 0;
+ HWREG(GPIOC + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOD
- GPIOD->IM = 0;
+ HWREG(GPIOD + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOE
- GPIOE->IM = 0;
+ HWREG(GPIOE + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOF
- GPIOF->IM = 0;
+ HWREG(GPIOF + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOG
- GPIOG->IM = 0;
+ HWREG(GPIOG + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOH
- GPIOH->IM = 0;
+ HWREG(GPIOH + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOJ
- GPIOJ->IM = 0;
+ HWREG(GPIOJ + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOK
- GPIOK->IM = 0;
+ HWREG(GPIOK + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOL
- GPIOL->IM = 0;
+ HWREG(GPIOL + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOM
- GPIOM->IM = 0;
+ HWREG(GPIOM + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPION
- GPION->IM = 0;
+ HWREG(GPION + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOP
- GPIOP->IM = 0;
+ HWREG(GPIOP + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOQ
- GPIOQ->IM = 0;
+ HWREG(GPIOQ + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOR
- GPIOR->IM = 0;
+ HWREG(GPIOR + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOS
- GPIOS->IM = 0;
+ HWREG(GPIOS + GPIO_O_IM) = 0;
#endif
#if TIVA_HAS_GPIOT
- GPIOT->IM = 0;
+ HWREG(GPIOT + GPIO_O_IM) = 0;
#endif
}
@@ -912,34 +912,34 @@ void ext_lld_stop(EXTDriver *extp)
*/
void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
{
- GPIO_TypeDef *gpiop;
+ uint32_t gpio;
uint8_t pin;
uint32_t im;
pin = channel & 0x07;
- gpiop = gpio[channel >> 3];
+ gpio = gpio_table[channel >> 3];
/* Disable interrupts */
- im = gpiop->IM;
- gpiop->IM = 0;
+ im = HWREG(gpio + GPIO_O_IM);
+ HWREG(gpio + GPIO_O_IM) = 0;
/* Configure pin to be edge-sensitive.*/
- gpiop->IS &= ~(1 << pin);
+ HWREG(gpio + GPIO_O_IS) &= ~(1 << pin);
/* Programming edge registers.*/
if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
EXT_CH_MODE_BOTH_EDGES) {
- gpiop->IBE |= (1 << pin);
+ HWREG(gpio + GPIO_O_IBE) |= (1 << pin);
}
else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
EXT_CH_MODE_FALLING_EDGE) {
- gpiop->IBE &= ~(1 << pin);
- gpiop->IEV &= ~(1 << pin);
+ HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin);
+ HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin);
}
else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
EXT_CH_MODE_RISING_EDGE) {
- gpiop->IBE &= ~(1 << pin);
- gpiop->IEV |= (1 << pin);
+ HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin);
+ HWREG(gpio + GPIO_O_IEV) |= (1 << pin);
}
/* Programming interrupt and event registers.*/
@@ -953,7 +953,7 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
}
/* Restore interrupts */
- gpiop->IM = im;
+ HWREG(gpio + GPIO_O_IM) = im;
}
/**
@@ -967,13 +967,13 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel)
{
(void)extp;
- GPIO_TypeDef *gpiop;
+ uint32_t gpio;
uint8_t pin;
pin = channel & 0x07;
- gpiop = gpio[channel >> 3];
+ gpio = gpio_table[channel >> 3];
- gpiop->IM &= ~(1 << pin);
+ HWREG(gpio + GPIO_O_IM) &= ~(1 << pin);
}
#endif /* HAL_USE_EXT */
diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
index 08accb2..08accb2 100644
--- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index 5460fd4..4df6665 100644
--- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -250,19 +250,19 @@
*/
static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
{
- port->DATA = config->data;
- port->DIR = config->dir;
- port->AFSEL = config->afsel;
- port->DR2R = config->dr2r;
- port->DR4R = config->dr4r;
- port->DR8R = config->dr8r;
- port->ODR = config->odr;
- port->PUR = config->pur;
- port->PDR = config->pdr;
- port->SLR = config->slr;
- port->DEN = config->den;
- port->AMSEL = config->amsel;
- port->PCTL = config->pctl;
+ HWREG((port) + GPIO_O_DATA) = config->data;
+ HWREG((port) + GPIO_O_DIR) = config->dir;
+ HWREG((port) + GPIO_O_AFSEL) = config->afsel;
+ HWREG((port) + GPIO_O_DR2R) = config->dr2r;
+ HWREG((port) + GPIO_O_DR4R) = config->dr4r;
+ HWREG((port) + GPIO_O_DR8R) = config->dr8r;
+ HWREG((port) + GPIO_O_ODR) = config->odr;
+ HWREG((port) + GPIO_O_PUR) = config->pur;
+ HWREG((port) + GPIO_O_PDR) = config->pdr;
+ HWREG((port) + GPIO_O_SLR) = config->slr;
+ HWREG((port) + GPIO_O_DEN) = config->den;
+ HWREG((port) + GPIO_O_AMSEL) = config->amsel;
+ HWREG((port) + GPIO_O_PCTL) = config->pctl;
}
/**
@@ -274,8 +274,9 @@ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
*/
static void gpio_unlock(ioportid_t port, ioportmask_t mask)
{
- port->LOCK = TIVA_GPIO_LOCK_PWD;
- port->CR = mask;
+
+ HWREG((port) + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD;
+ HWREG((port) + GPIO_O_CR) = mask;
}
/*===========================================================================*/
@@ -299,13 +300,13 @@ void _pal_lld_init(const PALConfig *config)
/*
* Enables all GPIO clocks.
*/
- SYSCTL->RCGCGPIO = RCGCGPIO_MASK;
+ HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK;
#if defined(TM4C123x)
- SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK;
+ HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK;
#endif
/* Wait until all GPIO modules are ready */
- while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK))
+ while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK))
;
#if TIVA_HAS_GPIOA
@@ -402,18 +403,18 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
uint32_t bit_mask = (1 << bit);
if ((mask & 1) != 0) {
- port->DIR = (port->DIR & ~bit_mask) | dir;
- port->AFSEL = (port->AFSEL & ~bit_mask) | afsel;
- port->DR2R = (port->DR2R & ~bit_mask) | dr2r;
- port->DR4R = (port->DR4R & ~bit_mask) | dr4r;
- port->DR8R = (port->DR8R & ~bit_mask) | dr8r;
- port->ODR = (port->ODR & ~bit_mask) | odr;
- port->PUR = (port->PUR & ~bit_mask) | pur;
- port->PDR = (port->PDR & ~bit_mask) | pdr;
- port->SLR = (port->SLR & ~bit_mask) | slr;
- port->DEN = (port->DEN & ~bit_mask) | den;
- port->AMSEL = (port->AMSEL & ~bit_mask) | amsel;
- port->PCTL = (port->PCTL & ~pctl_mask) | pctl;
+ HWREG((port) + GPIO_O_DIR) = (HWREG((port) + GPIO_O_DIR) & ~bit_mask) | dir;
+ HWREG((port) + GPIO_O_AFSEL) = (HWREG((port) + GPIO_O_AFSEL) & ~bit_mask) | afsel;
+ HWREG((port) + GPIO_O_DR2R) = (HWREG((port) + GPIO_O_DR2R) & ~bit_mask) | dr2r;
+ HWREG((port) + GPIO_O_DR4R) = (HWREG((port) + GPIO_O_DR4R) & ~bit_mask) | dr4r;
+ HWREG((port) + GPIO_O_DR8R) = (HWREG((port) + GPIO_O_DR8R) & ~bit_mask) | dr8r;
+ HWREG((port) + GPIO_O_ODR) = (HWREG((port) + GPIO_O_ODR) & ~bit_mask) | odr;
+ HWREG((port) + GPIO_O_PUR) = (HWREG((port) + GPIO_O_PUR) & ~bit_mask) | pur;
+ HWREG((port) + GPIO_O_PDR) = (HWREG((port) + GPIO_O_PDR) & ~bit_mask) | pdr;
+ HWREG((port) + GPIO_O_SLR) = (HWREG((port) + GPIO_O_SLR) & ~bit_mask) | slr;
+ HWREG((port) + GPIO_O_DEN) = (HWREG((port) + GPIO_O_DEN) & ~bit_mask) | den;
+ HWREG((port) + GPIO_O_AMSEL) = (HWREG((port) + GPIO_O_AMSEL) & ~bit_mask) | amsel;
+ HWREG((port) + GPIO_O_PCTL) = (HWREG((port) + GPIO_O_PCTL) & ~pctl_mask) | pctl;
}
mask >>= 1;
diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index c0cd82b..4e7005b 100644
--- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -352,70 +352,70 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if defined(TM4C123x)
+//#if defined(TM4C123x)
#if TIVA_GPIO_GPIOA_USE_AHB
-#define GPIOA GPIOA_AHB
+#define GPIOA GPIO_PORTA_AHB_BASE
#else
-#define GPIOA GPIOA_APB
+#define GPIOA GPIO_PORTA_BASE
#endif
#if TIVA_GPIO_GPIOB_USE_AHB
-#define GPIOB GPIOB_AHB
+#define GPIOB GPIO_PORTB_AHB_BASE
#else
-#define GPIOB GPIOB_APB
+#define GPIOB GPIO_PORTB_BASE
#endif
#if TIVA_GPIO_GPIOC_USE_AHB
-#define GPIOC GPIOC_AHB
+#define GPIOC GPIO_PORTC_AHB_BASE
#else
-#define GPIOC GPIOC_APB
+#define GPIOC GPIO_PORTC_BASE
#endif
#if TIVA_GPIO_GPIOD_USE_AHB
-#define GPIOD GPIOD_AHB
+#define GPIOD GPIO_PORTD_AHB_BASE
#else
-#define GPIOD GPIOD_APB
+#define GPIOD GPIO_PORTD_BASE
#endif
#if TIVA_GPIO_GPIOE_USE_AHB
-#define GPIOE GPIOE_AHB
+#define GPIOE GPIO_PORTE_AHB_BASE
#else
-#define GPIOE GPIOE_APB
+#define GPIOE GPIO_PORTE_BASE
#endif
#if TIVA_GPIO_GPIOF_USE_AHB
-#define GPIOF GPIOF_AHB
+#define GPIOF GPIO_PORTF_AHB_BASE
#else
-#define GPIOF GPIOF_APB
+#define GPIOF GPIO_PORTF_BASE
#endif
#if TIVA_GPIO_GPIOG_USE_AHB
-#define GPIOG GPIOG_AHB
+#define GPIOG GPIO_PORTG_AHB_BASE
#else
-#define GPIOG GPIOG_APB
+#define GPIOG GPIO_PORTG_BASE
#endif
#if TIVA_GPIO_GPIOH_USE_AHB
-#define GPIOH GPIOH_AHB
+#define GPIOH GPIO_PORTH_AHB_BASE
#else
-#define GPIOH GPIOH_APB
+#define GPIOH GPIO_PORTH_BASE
#endif
#if TIVA_GPIO_GPIOJ_USE_AHB
-#define GPIOJ GPIOJ_AHB
+#define GPIOJ GPIO_PORTJ_AHB_BASE
#else
-#define GPIOJ GPIOJ_APB
+#define GPIOJ GPIO_PORTJ_BASE
#endif
-#define GPIOK GPIOK_AHB
-#define GPIOL GPIOL_AHB
-#define GPIOM GPIOM_AHB
-#define GPION GPION_AHB
-#define GPIOP GPIOP_AHB
-#define GPIOQ GPIOQ_AHB
+#define GPIOK GPIO_PORTK_BASE
+#define GPIOL GPIO_PORTL_BASE
+#define GPIOM GPIO_PORTM_BASE
+#define GPION GPIO_PORTN_BASE
+#define GPIOP GPIO_PORTP_BASE
+#define GPIOQ GPIO_PORTQ_BASE
-#endif
+//#endif
/*===========================================================================*/
/* Driver data structures and types. */
@@ -550,7 +550,7 @@ typedef uint32_t iomode_t;
/**
* @brief Port Identifier.
*/
-typedef GPIO_TypeDef *ioportid_t;
+typedef uint32_t ioportid_t;
/*===========================================================================*/
/* Driver macros. */
@@ -573,7 +573,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_readport(port) ((port)->DATA)
+#define pal_lld_readport(port) (HWREG((port) + GPIO_O_DATA + (0xff << 2)))
/**
* @brief Reads the output latch.
@@ -585,7 +585,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_readlatch(port) ((port)->DATA)
+#define pal_lld_readlatch(port) pal_lld_readport(port)
/**
* @brief Writes a bits mask on a I/O port.
@@ -595,7 +595,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_writeport(port, bits) ((port)->DATA = (bits))
+#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_DATA + (0xff << 2)) = (bits))
/**
* @brief Sets a bits mask on a I/O port.
@@ -608,7 +608,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF)
+#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0xFF)
/**
* @brief Clears a bits mask on a I/O port.
@@ -621,7 +621,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0)
+#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0)
/**
* @brief Reads a group of bits.
@@ -637,7 +637,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_readgroup(port, mask, offset) \
- ((port)->MASKED_ACCESS[(mask) << (offset)])
+ (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))))
/**
* @brief Writes a group of bits.
@@ -654,7 +654,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) \
- ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
+ (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))) = (bits))
/**
* @brief Pads group mode setup.
@@ -686,7 +686,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
-#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)])
+#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))))
/**
* @brief Writes a logical state on an output pad.
@@ -704,7 +704,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_writepad(port, pad, bit) \
- ((port)->MASKED_ACCESS[1 << (pad)] = (bit))
+ (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit))
/**
* @brief Sets a pad logical state to @p PAL_HIGH.
@@ -718,7 +718,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_setpad(port, pad) \
- ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
+ (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (pad))
/**
* @brief Clears a pad logical state to @p PAL_LOW.
@@ -732,7 +732,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_clearpad(port, pad) \
- ((port)->MASKED_ACCESS[1 << (pad)] = 0)
+ (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0)
/*===========================================================================*/
/* External declarations. */
diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
index 870ba12..60d2b82 100644
--- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c
@@ -133,7 +133,7 @@ GPTDriver GPTD12;
*/
static void gpt_lld_serve_interrupt(GPTDriver *gptp)
{
- gptp->gpt->ICR = 0xffffffff;
+ HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
if (gptp->state == GPT_ONESHOT) {
gptp->state = GPT_READY;
@@ -388,62 +388,62 @@ void gpt_lld_init(void)
{
/* Driver initialization.*/
#if TIVA_GPT_USE_GPT0
- GPTD1.gpt = GPT0;
+ GPTD1.gpt = TIMER0_BASE;
gptObjectInit(&GPTD1);
#endif
#if TIVA_GPT_USE_GPT1
- GPTD2.gpt = GPT1;
+ GPTD2.gpt = TIMER1_BASE;
gptObjectInit(&GPTD2);
#endif
#if TIVA_GPT_USE_GPT2
- GPTD3.gpt = GPT2;
+ GPTD3.gpt = TIMER2_BASE;
gptObjectInit(&GPTD3);
#endif
#if TIVA_GPT_USE_GPT3
- GPTD4.gpt = GPT3;
+ GPTD4.gpt = TIMER3_BASE;
gptObjectInit(&GPTD4);
#endif
#if TIVA_GPT_USE_GPT4
- GPTD5.gpt = GPT4;
+ GPTD5.gpt = TIMER4_BASE;
gptObjectInit(&GPTD5);
#endif
#if TIVA_GPT_USE_GPT5
- GPTD6.gpt = GPT5;
+ GPTD6.gpt = TIMER5_BASE;
gptObjectInit(&GPTD6);
#endif
#if TIVA_GPT_USE_WGPT0
- GPTD7.gpt = WGPT0;
+ GPTD7.gpt = WTIMER0_BASE;
gptObjectInit(&GPTD7);
#endif
#if TIVA_GPT_USE_WGPT1
- GPTD8.gpt = WGPT1;
+ GPTD8.gpt = WTIMER1_BASE;
gptObjectInit(&GPTD8);
#endif
#if TIVA_GPT_USE_WGPT2
- GPTD9.gpt = WGPT2;
+ GPTD9.gpt = WTIMER2_BASE;
gptObjectInit(&GPTD9);
#endif
#if TIVA_GPT_USE_WGPT3
- GPTD10.gpt = WGPT3;
+ GPTD10.gpt = WTIMER3_BASE;
gptObjectInit(&GPTD10);
#endif
#if TIVA_GPT_USE_WGPT4
- GPTD11.gpt = WGPT4;
+ GPTD11.gpt = WTIMER4_BASE;
gptObjectInit(&GPTD11);
#endif
#if TIVA_GPT_USE_WGPT5
- GPTD12.gpt = WGPT5;
+ GPTD12.gpt = WTIMER5_BASE;
gptObjectInit(&GPTD12);
#endif
}
@@ -461,9 +461,9 @@ void gpt_lld_start(GPTDriver *gptp)
/* Clock activation.*/
#if TIVA_GPT_USE_GPT0
if (&GPTD1 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 0);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 0);
- while (!(SYSCTL->PRTIMER & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0)))
;
nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY);
@@ -472,9 +472,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_GPT1
if (&GPTD2 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 1);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 1);
- while (!(SYSCTL->PRTIMER & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1)))
;
nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY);
@@ -483,9 +483,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_GPT2
if (&GPTD3 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 2);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 2);
- while (!(SYSCTL->PRTIMER & (1 << 2)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2)))
;
nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY);
@@ -494,9 +494,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_GPT3
if (&GPTD4 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 3);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 3);
- while (!(SYSCTL->PRTIMER & (1 << 3)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3)))
;
nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY);
@@ -505,9 +505,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_GPT4
if (&GPTD5 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 4);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 4);
- while (!(SYSCTL->PRTIMER & (1 << 4)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4)))
;
nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY);
@@ -516,9 +516,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_GPT5
if (&GPTD6 == gptp) {
- SYSCTL->RCGCTIMER |= (1 << 5);
+ HWREG(SYSCTL_RCGCTIMER) |= (1 << 5);
- while (!(SYSCTL->PRTIMER & (1 << 5)))
+ while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5)))
;
nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY);
@@ -527,9 +527,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT0
if (&GPTD7 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 0);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0);
- while (!(SYSCTL->PRWTIMER & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0)))
;
nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY);
@@ -538,9 +538,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT1
if (&GPTD8 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 1);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1);
- while (!(SYSCTL->PRWTIMER & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1)))
;
nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY);
@@ -549,9 +549,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT2
if (&GPTD9 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 2);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2);
- while (!(SYSCTL->PRWTIMER & (1 << 2)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2)))
;
nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY);
@@ -560,9 +560,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT3
if (&GPTD10 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 3);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3);
- while (!(SYSCTL->PRWTIMER & (1 << 3)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3)))
;
nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY);
@@ -571,9 +571,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT4
if (&GPTD11 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 4);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4);
- while (!(SYSCTL->PRWTIMER & (1 << 4)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4)))
;
nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY);
@@ -582,9 +582,9 @@ void gpt_lld_start(GPTDriver *gptp)
#if TIVA_GPT_USE_WGPT5
if (&GPTD12 == gptp) {
- SYSCTL->RCGCWTIMER |= (1 << 5);
+ HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5);
- while (!(SYSCTL->PRWTIMER & (1 << 5)))
+ while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5)))
;
nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY);
@@ -593,9 +593,9 @@ void gpt_lld_start(GPTDriver *gptp)
}
/* Timer configuration.*/
- gptp->gpt->CTL = 0;
- gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT;
- gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1);
+ HWREG(gptp->gpt + TIMER_O_CTL) = 0;
+ HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT;
+ HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1);
}
/**
@@ -608,91 +608,91 @@ void gpt_lld_start(GPTDriver *gptp)
void gpt_lld_stop(GPTDriver *gptp)
{
if (gptp->state == GPT_READY) {
- gptp->gpt->IMR = 0;
- gptp->gpt->TAILR = 0;
- gptp->gpt->CTL = 0;
+ HWREG(gptp->gpt + TIMER_O_IMR) = 0;
+ HWREG(gptp->gpt + TIMER_O_TAILR) = 0;
+ HWREG(gptp->gpt + TIMER_O_CTL) = 0;
#if TIVA_GPT_USE_GPT0
if (&GPTD1 == gptp) {
nvicDisableVector(TIVA_GPT0A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 0);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 0);
}
#endif
#if TIVA_GPT_USE_GPT1
if (&GPTD2 == gptp) {
nvicDisableVector(TIVA_GPT1A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 1);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 1);
}
#endif
#if TIVA_GPT_USE_GPT2
if (&GPTD3 == gptp) {
nvicDisableVector(TIVA_GPT2A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 2);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 2);
}
#endif
#if TIVA_GPT_USE_GPT3
if (&GPTD4 == gptp) {
nvicDisableVector(TIVA_GPT3A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 3);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 3);
}
#endif
#if TIVA_GPT_USE_GPT4
if (&GPTD5 == gptp) {
nvicDisableVector(TIVA_GPT4A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 4);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 4);
}
#endif
#if TIVA_GPT_USE_GPT5
if (&GPTD6 == gptp) {
nvicDisableVector(TIVA_GPT5A_NUMBER);
- SYSCTL->RCGCTIMER &= ~(1 << 5);
+ HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 5);
}
#endif
#if TIVA_GPT_USE_WGPT0
if (&GPTD7 == gptp) {
nvicDisableVector(TIVA_WGPT0A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 0);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 0);
}
#endif
#if TIVA_GPT_USE_WGPT1
if (&GPTD8 == gptp) {
nvicDisableVector(TIVA_WGPT1A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 1);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 1);
}
#endif
#if TIVA_GPT_USE_WGPT2
if (&GPTD9 == gptp) {
nvicDisableVector(TIVA_WGPT2A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 2);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 2);
}
#endif
#if TIVA_GPT_USE_WGPT3
if (&GPTD10 == gptp) {
nvicDisableVector(TIVA_WGPT3A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 3);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 3);
}
#endif
#if TIVA_GPT_USE_WGPT4
if (&GPTD11 == gptp) {
nvicDisableVector(TIVA_WGPT4A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 4);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 4);
}
#endif
#if TIVA_GPT_USE_WGPT5
if (&GPTD12 == gptp) {
nvicDisableVector(TIVA_WGPT5A_NUMBER);
- SYSCTL->RCGCWTIMER &= ~(1 << 5);
+ HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 5);
}
#endif
}
@@ -708,11 +708,11 @@ void gpt_lld_stop(GPTDriver *gptp)
*/
void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval)
{
- gptp->gpt->TAILR = interval - 1;
- gptp->gpt->ICR = 0xfffffff;
- gptp->gpt->IMR = GPTM_IMR_TATOIM;
- gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
- gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
+ HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1;
+ HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff;
+ HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM;
+ HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS;
+ HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL;
}
/**
@@ -724,9 +724,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval)
*/
void gpt_lld_stop_timer(GPTDriver *gptp)
{
- gptp->gpt->IMR = 0;
- gptp->gpt->TAILR = 0;
- gptp->gpt->CTL &= ~GPTM_CTL_TAEN;
+ HWREG(gptp->gpt + TIMER_O_IMR) = 0;
+ HWREG(gptp->gpt + TIMER_O_TAILR) = 0;
+ HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN;
}
/**
@@ -742,13 +742,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp)
*/
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval)
{
- gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
- gptp->gpt->TAILR = interval - 1;
- gptp->gpt->ICR = 0xffffffff;
- gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
- while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM))
+ HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS;
+ HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1;
+ HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
+ HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL;
+ while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM))
;
- gptp->gpt->ICR = 0xffffffff;
+ HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff;
}
#endif /* HAL_USE_GPT */
diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h
index e518e58..88a6809 100644
--- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h
@@ -405,7 +405,7 @@ struct GPTDriver {
/**
* @brief Pointer to the GPT registers block.
*/
- GPT_TypeDef *gpt;
+ uint32_t gpt;
};
/*===========================================================================*/
@@ -426,7 +426,7 @@ struct GPTDriver {
* @notapi
*/
#define gpt_lld_change_interval(gptp, interval) { \
- gptp->gpt->TAILR = interval - 1; \
+ HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; \
}
/*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
index 30fdb8a..d87652b 100644
--- a/os/hal/ports/TIVA/LLD/hal_st_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
@@ -67,8 +67,8 @@
#elif TIVA_ST_TIMER_NUMBER == 5
#define ST_HANDLER TIVA_WGPT5A_HANDLER
#define ST_NUMBER TIVA_WGPT5A_NUMBER
-#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5))
-#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5)))
+#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5))
+#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5)))
#else
#error "TIVA_ST_USE_TIMER specifies an unsupported timer"
@@ -184,10 +184,10 @@ OSAL_IRQ_HANDLER(ST_HANDLER)
OSAL_IRQ_PROLOGUE();
- mis = TIVA_ST_TIM->MIS;
- TIVA_ST_TIM->ICR = mis;
+ mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS);
+ HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis;
- if (mis & GPTM_IMR_TAMIM) {
+ if (mis & TIMER_IMR_TAMIM) {
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
@@ -218,15 +218,17 @@ void st_lld_init(void)
ST_WAIT_CLOCK();
/* Initializing the counter in free running down mode.*/
- TIVA_ST_TIM->CTL = 0;
- TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */
- TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */
- GPTM_TAMR_TAMIE | /* Match interrupt enable */
- GPTM_TAMR_TASNAPS); /* Snapshot mode */
-
- TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1;
- TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */
- GPTM_CTL_TASTALL); /* Timer A stall when paused */
+ HWREG(TIVA_ST_TIM + TIMER_O_CTL) = 0;
+ HWREG(TIVA_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */
+ HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = (
+ TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */
+ TIMER_TAMR_TAMIE | /* Match interrupt enable */
+ TIMER_TAMR_TASNAPS); /* Snapshot mode */
+
+ HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1;
+ HWREG(TIVA_ST_TIM + TIMER_O_CTL) = (
+ TIMER_CTL_TAEN | /* Timer A enable */
+ TIMER_CTL_TASTALL); /* Timer A stall when paused */
/* IRQ enabled.*/
nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY);
diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h
index 35bf008..cd076d6 100644
--- a/os/hal/ports/TIVA/LLD/hal_st_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h
@@ -29,7 +29,6 @@
#include "mcuconf.h"
#include "tiva_registry.h"
-#include "tiva_gpt.h"
/*===========================================================================*/
/* Driver constants. */
@@ -82,37 +81,37 @@
#if !TIVA_HAS_WGPT0
#error "WGPT0 not present"
#endif
-#define TIVA_ST_TIM WGPT0
+#define TIVA_ST_TIM WTIMER0_BASE
#elif TIVA_ST_TIMER_NUMBER == 1
#if !TIVA_HAS_WGPT1
#error "WGPT1 not present"
#endif
-#define TIVA_ST_TIM WGPT1
+#define TIVA_ST_TIM WTIMER1_BASE
#elif TIVA_ST_TIMER_NUMBER == 2
#if !TIVA_HAS_WGPT2
#error "WGPT2 not present"
#endif
-#define TIVA_ST_TIM WGPT2
+#define TIVA_ST_TIM WTIMER2_BASE
#elif TIVA_ST_TIMER_NUMBER == 3
#if !TIVA_HAS_WGPT3
#error "WGPT3 not present"
#endif
-#define TIVA_ST_TIM WGPT3
+#define TIVA_ST_TIM WTIMER3_BASE
#elif TIVA_ST_TIMER_NUMBER == 4
#if !TIVA_HAS_WGPT4
#error "WGPT4 not present"
#endif
-#define TIVA_ST_TIM WGPT4
+#define TIVA_ST_TIM WTIMER4_BASE
#elif TIVA_ST_TIMER_NUMBER == 5
#if !TIVA_HAS_WGPT5
#error "WGPT5 not present"
#endif
-#define TIVA_ST_TIM WGPT5
+#define TIVA_ST_TIM WTIMER5_BASE
#else
#error "TIVA_ST_USE_TIMER specifies an unsupported timer"
@@ -124,37 +123,37 @@
#if !TIVA_HAS_GPT0
#error "GPT0 not present"
#endif
-#define TIVA_ST_TIM GPT0
+#define TIVA_ST_TIM TIMER0_BASE
#elif TIVA_ST_TIMER_NUMBER == 1
#if !TIVA_HAS_GPT1
#error "GPT1 not present"
#endif
-#define TIVA_ST_TIM GPT1
+#define TIVA_ST_TIM TIMER1_BASE
#elif TIVA_ST_TIMER_NUMBER == 2
#if !TIVA_HAS_GPT2
#error "GPT2 not present"
#endif
-#define TIVA_ST_TIM GPT2
+#define TIVA_ST_TIM TIMER2_BASE
#elif TIVA_ST_TIMER_NUMBER == 3
#if !TIVA_HAS_GPT3
#error "GPT3 not present"
#endif
-#define TIVA_ST_TIM GPT3
+#define TIVA_ST_TIM TIMER3_BASE
#elif TIVA_ST_TIMER_NUMBER == 4
#if !TIVA_HAS_GPT4
#error "GPT4 not present"
#endif
-#define TIVA_ST_TIM GPT4
+#define TIVA_ST_TIM TIMER4_BASE
#elif TIVA_ST_TIMER_NUMBER == 5
#if !TIVA_HAS_GPT5
#error "GPT5 not present"
#endif
-#define TIVA_ST_TIM GPT5
+#define TIVA_ST_TIM TIMER5_BASE
#else
#error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer"
@@ -164,11 +163,6 @@
#error "wrong value defined for TIVA_ST_USE_WIDE_TIMER"
#endif
-#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \
- !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ST"
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -202,7 +196,7 @@ extern "C" {
*/
static inline systime_t st_lld_get_counter(void)
{
- return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR);
+ return (systime_t) (((systime_t) 0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAV));
}
/**
@@ -216,9 +210,9 @@ static inline systime_t st_lld_get_counter(void)
*/
static inline void st_lld_start_alarm(systime_t time)
{
- TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time);
- TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS;
- TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM;
+ HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time);
+ HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS);
+ HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM;
}
/**
@@ -228,7 +222,7 @@ static inline void st_lld_start_alarm(systime_t time)
*/
static inline void st_lld_stop_alarm(void)
{
- TIVA_ST_TIM->IMR = 0;
+ HWREG(TIVA_ST_TIM + TIMER_O_IMR) = 0;
}
/**
@@ -240,7 +234,7 @@ static inline void st_lld_stop_alarm(void)
*/
static inline void st_lld_set_alarm(systime_t time)
{
- TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time);
+ HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time);
}
/**
@@ -252,7 +246,7 @@ static inline void st_lld_set_alarm(systime_t time)
*/
static inline systime_t st_lld_get_alarm(void)
{
- return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR);
+ return (systime_t) (((systime_t)0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR));
}
/**
@@ -266,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void)
*/
static inline bool st_lld_is_alarm_active(void)
{
- return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0);
+ return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0);
}
#endif /* HAL_ST_LLD_H */
diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
index cb69861..cf70dca 100644
--- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
@@ -30,6 +30,33 @@
/* Driver local definitions. */
/*===========================================================================*/
+// interrupt states
+#define STATE_IDLE 0
+#define STATE_WRITE_NEXT 1
+#define STATE_WRITE_FINAL 2
+#define STATE_WAIT_ACK 3
+#define STATE_SEND_ACK 4
+#define STATE_READ_ONE 5
+#define STATE_READ_FIRST 6
+#define STATE_READ_NEXT 7
+#define STATE_READ_FINAL 8
+#define STATE_READ_WAIT 9
+
+#define TIVA_I2C_SIGNLE_SEND (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_START (I2C_MCS_RUN | I2C_MCS_START)
+#define TIVA_I2C_BURST_SEND_CONTINUE (I2C_MCS_RUN)
+#define TIVA_I2C_BURST_SEND_FINISH (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_STOP (I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_ERROR_STOP (I2C_MCS_STOP)
+
+#define TIVA_I2C_SINGLE_RECEIVE (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_START (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_CONTINUE (I2C_MCS_RUN | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_FINISH (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (I2C_MCS_STOP)
+
+#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -125,19 +152,19 @@ I2CDriver I2CD10;
*/
static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
{
- I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t i2c = i2cp->i2c;
uint32_t status;
// clear MIS bit in MICR by writing 1
- dp->MICR = 1;
+ HWREG(i2c + I2C_O_MICR) = 1;
// read interrupt status
- status = dp->MCS;
+ status = HWREG(i2c + I2C_O_MCS);
- if (status & TIVA_MCS_ERROR) {
+ if (status & I2C_MCS_ERROR) {
i2cp->errors |= I2C_BUS_ERROR;
}
- if (status & TIVA_MCS_ARBLST) {
+ if (status & I2C_MCS_ARBLST) {
i2cp->errors |= I2C_ARBITRATION_LOST;
}
@@ -152,11 +179,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
if (i2cp->txbytes == 1) {
i2cp->intstate = STATE_WRITE_FINAL;
}
- dp->MDR = *(i2cp->txbuf);
+ HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
i2cp->txbuf++;
i2cp->txbytes--;
// start transmission
- dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE;
break;
}
case STATE_WRITE_FINAL: {
@@ -169,12 +196,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
else {
i2cp->intstate = STATE_READ_FIRST;
}
- dp->MDR = *(i2cp->txbuf);
+ HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
i2cp->txbuf++;
// txbytes - 1
i2cp->txbytes--;
// start transmission
- dp->MCS = TIVA_I2C_BURST_SEND_FINISH;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH;
break;
}
case STATE_WAIT_ACK: {
@@ -189,10 +216,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
i2cp->addr |= 1;
// set slave address
- dp->MSA = i2cp->addr;
- i2cp->rxbytes--;
+ HWREG(i2c + I2C_O_MSA) = i2cp->addr;
+ i2cp->rxbytes--;
//start receiving
- dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
break;
}
@@ -208,10 +235,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
i2cp->addr |= 1;
// set slave address
- dp->MSA = i2cp->addr;
- i2cp->rxbytes--;
+ HWREG(i2c + I2C_O_MSA) = i2cp->addr;
+ i2cp->rxbytes--;
//start receiving
- dp->MCS = TIVA_I2C_BURST_RECEIVE_START;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START;
break;
}
@@ -219,27 +246,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
if(i2cp->rxbytes == 2) {
i2cp->intstate = STATE_READ_FINAL;
}
- *(i2cp->rxbuf) = dp->MDR;
+ *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
i2cp->rxbuf++;
i2cp->rxbytes--;
//start receiving
- dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE;
break;
}
case STATE_READ_FINAL: {
i2cp->intstate = STATE_READ_WAIT;
- *(i2cp->rxbuf) = dp->MDR;
+ *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
i2cp->rxbuf++;
- i2cp->rxbytes--;
+ i2cp->rxbytes--;
//start receiving
- dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH;
break;
}
case STATE_READ_WAIT: {
i2cp->intstate = STATE_IDLE;
- *(i2cp->rxbuf) = dp->MDR;
+ *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
i2cp->rxbuf++;
_i2c_wakeup_isr(i2cp);
break;
@@ -430,61 +457,61 @@ void i2c_lld_init(void) {
#if TIVA_I2C_USE_I2C0
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
- I2CD1.i2c = I2C0;
+ I2CD1.i2c = I2C0_BASE;
#endif /* TIVA_I2C_USE_I2C0 */
#if TIVA_I2C_USE_I2C1
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
- I2CD2.i2c = I2C1;
+ I2CD2.i2c = I2C1_BASE;
#endif /* TIVA_I2C_USE_I2C1 */
#if TIVA_I2C_USE_I2C2
i2cObjectInit(&I2CD3);
I2CD3.thread = NULL;
- I2CD3.i2c = I2C2;
+ I2CD3.i2c = I2C2_BASE;
#endif /* TIVA_I2C_USE_I2C2 */
#if TIVA_I2C_USE_I2C3
i2cObjectInit(&I2CD4);
I2CD4.thread = NULL;
- I2CD4.i2c = I2C3;
+ I2CD4.i2c = I2C3_BASE;
#endif /* TIVA_I2C_USE_I2C3 */
#if TIVA_I2C_USE_I2C4
i2cObjectInit(&I2CD5);
I2CD5.thread = NULL;
- I2CD5.i2c = I2C4;
+ I2CD5.i2c = I2C4_BASE;
#endif /* TIVA_I2C_USE_I2C4 */
#if TIVA_I2C_USE_I2C5
i2cObjectInit(&I2CD6);
I2CD6.thread = NULL;
- I2CD6.i2c = I2C5;
+ I2CD6.i2c = I2C5_BASE;
#endif /* TIVA_I2C_USE_I2C5 */
#if TIVA_I2C_USE_I2C6
i2cObjectInit(&I2CD7);
I2CD7.thread = NULL;
- I2CD7.i2c = I2C6;
+ I2CD7.i2c = I2C6_BASE;
#endif /* TIVA_I2C_USE_I2C6 */
#if TIVA_I2C_USE_I2C7
i2cObjectInit(&I2CD8);
I2CD8.thread = NULL;
- I2CD8.i2c = I2C7;
+ I2CD8.i2c = I2C7_BASE;
#endif /* TIVA_I2C_USE_I2C7 */
#if TIVA_I2C_USE_I2C8
i2cObjectInit(&I2CD9);
I2CD9.thread = NULL;
- I2CD9.i2c = I2C8;
+ I2CD9.i2c = I2C8_BASE;
#endif /* TIVA_I2C_USE_I2C8 */
#if TIVA_I2C_USE_I2C9
i2cObjectInit(&I2CD10);
I2CD10.thread = NULL;
- I2CD10.i2c = I2C9;
+ I2CD10.i2c = I2C9_BASE;
#endif /* TIVA_I2C_USE_I2C9 */
}
@@ -497,15 +524,15 @@ void i2c_lld_init(void) {
*/
void i2c_lld_start(I2CDriver *i2cp)
{
- I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t i2c = i2cp->i2c;
/* If in stopped state then enables the I2C clocks.*/
if (i2cp->state == I2C_STOP) {
#if TIVA_I2C_USE_I2C0
if (&I2CD1 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 0);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 0);
- while (!(SYSCTL->PRI2C & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 0)))
;
nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY);
@@ -514,9 +541,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C1
if (&I2CD2 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 1);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 1);
- while (!(SYSCTL->PRI2C & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 1)))
;
nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY);
@@ -525,9 +552,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C2
if (&I2CD3 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 2);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 2);
- while (!(SYSCTL->PRI2C & (1 << 2)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 2)))
;
nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY);
@@ -536,9 +563,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C3
if (&I2CD4 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 3);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 3);
- while (!(SYSCTL->PRI2C & (1 << 3)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 3)))
;
nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY);
@@ -547,9 +574,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C4
if (&I2CD5 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 4);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 4);
- while (!(SYSCTL->PRI2C & (1 << 4)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 4)))
;
nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY);
@@ -558,9 +585,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C5
if (&I2CD6 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 5);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 5);
- while (!(SYSCTL->PRI2C & (1 << 5)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 5)))
;
nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY);
@@ -569,9 +596,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C6
if (&I2CD7 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 6);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 6);
- while (!(SYSCTL->PRI2C & (1 << 6)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 6)))
;
nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY);
@@ -580,9 +607,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C7
if (&I2CD8 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 7);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 7);
- while (!(SYSCTL->PRI2C & (1 << 7)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 7)))
;
nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY);
@@ -591,9 +618,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C8
if (&I2CD9 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 8);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 8);
- while (!(SYSCTL->PRI2C & (1 << 8)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 8)))
;
nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY);
@@ -602,9 +629,9 @@ void i2c_lld_start(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C9
if (&I2CD10 == i2cp) {
- SYSCTL->RCGCI2C |= (1 << 9);
+ HWREG(SYSCTL_RCGCI2C) |= (1 << 9);
- while (!(SYSCTL->PRI2C & (1 << 9)))
+ while (!(HWREG(SYSCTL_PRI2C) & (1 << 9)))
;
nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY);
@@ -612,8 +639,8 @@ void i2c_lld_start(I2CDriver *i2cp)
#endif /* TIVA_I2C_USE_I2C7 */
}
- dp->MCR = 0x10;
- dp->MTPR = MTPR_VALUE;
+ HWREG(i2c + I2C_O_MCR) = 0x10;
+ HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE;
}
/**
@@ -625,7 +652,8 @@ void i2c_lld_start(I2CDriver *i2cp)
*/
void i2c_lld_stop(I2CDriver *i2cp)
{
- I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t i2c = i2cp->i2c;
+
/* If not in stopped state then disables the I2C clock.*/
if (i2cp->state != I2C_STOP) {
@@ -635,76 +663,76 @@ void i2c_lld_stop(I2CDriver *i2cp)
#if TIVA_I2C_USE_I2C0
if (&I2CD1 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 0);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0);
nvicDisableVector(TIVA_I2C0_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C0 */
#if TIVA_I2C_USE_I2C1
if (&I2CD2 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 1);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1);
nvicDisableVector(TIVA_I2C1_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C1 */
#if TIVA_I2C_USE_I2C2
if (&I2CD3 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 2);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2);
nvicDisableVector(TIVA_I2C2_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C2 */
#if TIVA_I2C_USE_I2C3
if (&I2CD4 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 3);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3);
nvicDisableVector(TIVA_I2C3_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C3 */
#if TIVA_I2C_USE_I2C4
if (&I2CD5 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 4);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4);
nvicDisableVector(TIVA_I2C4_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C4 */
#if TIVA_I2C_USE_I2C5
if (&I2CD6 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 5);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5);
nvicDisableVector(TIVA_I2C5_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C5 */
#if TIVA_I2C_USE_I2C6
if (&I2CD7 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 6);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6);
nvicDisableVector(TIVA_I2C6_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C6 */
#if TIVA_I2C_USE_I2C7
if (&I2CD8 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 7);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7);
nvicDisableVector(TIVA_I2C7_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C7 */
#if TIVA_I2C_USE_I2C8
if (&I2CD9 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 8);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8);
nvicDisableVector(TIVA_I2C8_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C8 */
#if TIVA_I2C_USE_I2C9
if (&I2CD10 == i2cp) {
- SYSCTL->RCGCI2C &= ~(1 << 9);
+ HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9);
nvicDisableVector(TIVA_I2C9_NUMBER);
}
#endif /* TIVA_I2C_USE_I2C9 */
- dp->MCR = 0;
- dp->MTPR = 0;
+ HWREG(i2c + I2C_O_MCR) = 0;
+ HWREG(i2c + I2C_O_MTPR) = 0;
}
}
@@ -733,7 +761,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
uint8_t *rxbuf, size_t rxbytes,
systime_t timeout)
{
- I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t i2c = i2cp->i2c;
systime_t start, end;
i2cp->rxbuf = rxbuf;
@@ -759,7 +787,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* If the bus is not busy then the operation can continue, note, the
loop is exited in the locked state.*/
- if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+ if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
break;
/* If the system time went outside the allowed window then a timeout
@@ -771,10 +799,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
}
/* set slave address */
- dp->MSA = addr;
+ HWREG(i2c + I2C_O_MSA) = addr;
/* Starts the operation.*/
- dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
/* Waits for the operation completion or a timeout.*/
return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
@@ -808,7 +836,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
uint8_t *rxbuf, size_t rxbytes,
systime_t timeout)
{
- I2C_TypeDef *dp = i2cp->i2c;
+ uint32_t i2c = i2cp->i2c;
systime_t start, end;
i2cp->rxbuf = rxbuf;
@@ -833,7 +861,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* If the bus is not busy then the operation can continue, note, the
loop is exited in the locked state.*/
- if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+ if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
break;
/* If the system time went outside the allowed window then a timeout
@@ -848,13 +876,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
i2cp->addr = addr << 1 | 0;
/* set slave address */
- dp->MSA = i2cp->addr;
+ HWREG(i2c + I2C_O_MSA) = i2cp->addr;
/* enable interrupts */
- dp->MIMR = TIVA_MIMR_IM;
+ HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM;
/* put data in register */
- dp->MDR = *(i2cp->txbuf);
+ HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
/* check if 1 or more bytes */
if (i2cp->txbytes == 1) {
@@ -867,7 +895,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
i2cp->intstate = STATE_READ_FIRST;
}
// single byte send
- dp->MCS = TIVA_I2C_SIGNLE_SEND;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND;
}
else {
if (i2cp->txbytes == 2) {
@@ -879,7 +907,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
i2cp->intstate = STATE_WRITE_NEXT;
}
// multiple bytes start send
- dp->MCS = TIVA_I2C_BURST_SEND_START;
+ HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START;
}
i2cp->txbuf++;
diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
index 460d231..4eabda8 100644
--- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
@@ -31,80 +31,6 @@
/* Driver constants. */
/*===========================================================================*/
-#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
-
-#define TIVA_MSA_RS (1 << 0)
-#define TIVA_MSA_SA (127 << 1)
-
-#define TIVA_MCS_BUSY (1 << 0)
-#define TIVA_MCS_ERROR (1 << 1)
-#define TIVA_MCS_ADRACK (1 << 2)
-#define TIVA_MCS_DATACK (1 << 3)
-#define TIVA_MCS_ARBLST (1 << 4)
-#define TIVA_MCS_IDLE (1 << 5)
-#define TIVA_MCS_BUSBSY (1 << 6)
-#define TIVA_MCS_CLKTO (1 << 7)
-
-#define TIVA_MCS_RUN (1 << 0)
-#define TIVA_MCS_START (1 << 1)
-#define TIVA_MCS_STOP (1 << 2)
-#define TIVA_MCS_ACK (1 << 3)
-#define TIVA_MCS_HS (1 << 4)
-
-#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START)
-#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN)
-#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP)
-
-#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP)
-
-#define TIVA_MDR_DATA (255 << 0)
-
-#define TIVA_MTPR_TPR (127 << 0)
-#define TIVA_MTPR_HS (1 << 7)
-
-#define TIVA_MIMR_IM (1 << 0)
-#define TIVA_MIMR_CLKIM (1 << 1)
-
-#define TIVA_MRIS_RIS (1 << 0)
-#define TIVA_MRIS_CLKRIS (1 << 1)
-
-#define TIVA_MMIS_MIS (1 << 0)
-#define TIVA_MMIS_CLKMIS (1 << 1)
-
-#define TIVA_MICR_IC (1 << 0)
-#define TIVA_MICR_CLKIC (1 << 1)
-
-#define TIVA_MCR_LPBK (1 << 0)
-#define TIVA_MCR_MFE (1 << 4)
-#define TIVA_MCR_SFE (1 << 5)
-#define TIVA_MCR_GFE (1 << 6)
-
-#define TIVA_MCLKOCNT_CNTL (255 << 0)
-
-#define TIVA_MBMON_SCL (1 << 0)
-#define TIVA_MBMON_SDA (1 << 1)
-
-#define TIVA_MCR2_GFPW (7 << 4)
-
-// interrupt states
-#define STATE_IDLE 0
-#define STATE_WRITE_NEXT 1
-#define STATE_WRITE_FINAL 2
-#define STATE_WAIT_ACK 3
-#define STATE_SEND_ACK 4
-#define STATE_READ_ONE 5
-#define STATE_READ_FIRST 6
-#define STATE_READ_NEXT 7
-#define STATE_READ_FINAL 8
-#define STATE_READ_WAIT 9
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -440,7 +366,7 @@ struct I2CDriver {
/**
* @brief Pointer to the I2Cx registers block.
*/
- I2C_TypeDef *i2c;
+ uint32_t i2c;
};
/*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
index 04177b6..cf64bbb 100644
--- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c
+++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
@@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
*/
static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
{
- ETH->MIIDATA = value;
- ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
+ HWREG(EMAC_O_MIIDATA) = value;
+ HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
- while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+ while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
;
}
@@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
*/
static uint32_t mii_read(MACDriver *macp, uint32_t reg)
{
- ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
+ HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
- while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+ while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
;
- return ETH->MIIDATA;
+ return HWREG(EMAC_O_MIIDATA);
}
/**
@@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp)
#endif
for (i = 0; i < 31; i++) {
macp->phyaddr = i << 11;
- ETH->MIIDATA = (i << 6) | MACMIIADDR_CR;
+ HWREG(EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
return;
@@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p)
{
/* MAC address configuration, only a single address comparator is used,
hash table not used.*/
- ETH->ADDR0H = ((uint32_t)p[5] << 8) |
+ HWREG(EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) |
((uint32_t)p[4] << 0);
- ETH->ADDR0L = ((uint32_t)p[3] << 24) |
+ HWREG(EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) |
((uint32_t)p[2] << 16) |
((uint32_t)p[1] << 8) |
((uint32_t)p[0] << 0);
- ETH->ADDR1H = 0x0000FFFF;
- ETH->ADDR1L = 0xFFFFFFFF;
- ETH->ADDR2H = 0x0000FFFF;
- ETH->ADDR2L = 0xFFFFFFFF;
- ETH->ADDR3H = 0x0000FFFF;
- ETH->ADDR3L = 0xFFFFFFFF;
- ETH->HASHTBLH = 0;
- ETH->HASHTBLL = 0;
+ HWREG(EMAC_O_ADDR1H) = 0x0000FFFF;
+ HWREG(EMAC_O_ADDR1L) = 0xFFFFFFFF;
+ HWREG(EMAC_O_ADDR2H) = 0x0000FFFF;
+ HWREG(EMAC_O_ADDR2L) = 0xFFFFFFFF;
+ HWREG(EMAC_O_ADDR3H) = 0x0000FFFF;
+ HWREG(EMAC_O_ADDR3L) = 0xFFFFFFFF;
+ HWREG(EMAC_O_HASHTBLH) = 0;
+ HWREG(EMAC_O_HASHTBLL) = 0;
}
/*===========================================================================*/
@@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
CH_IRQ_PROLOGUE();
- dmaris = ETH->DMARIS;
- ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/
+ dmaris = HWREG(EMAC_O_DMARIS);
+ HWREG(EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
if (dmaris & (1 << 6)) {
/* Data Received.*/
@@ -275,26 +275,26 @@ void mac_lld_init(void)
}
/* Enable MAC clock */
- SYSCTL->RCGCEMAC = 1;
- while (SYSCTL->PREMAC != 0x01)
+ HWREG(SYSCTL_RCGCEMAC) = 1;
+ while (HWREG(SYSCTL_PREMAC) != 0x01)
;
/* Set PHYHOLD bit */
- ETH->PC |= 1;
+ HWREG(EMAC_O_PC) |= 1;
/* Enable PHY clock */
- SYSCTL->RCGCEPHY = 1;
- while (SYSCTL->PREPHY != 0x01)
+ HWREG(SYSCTL_RCGCEPHY) = 1;
+ while (HWREG(SYSCTL_PREPHY) != 0x01)
;
/* Enable power to PHY */
- SYSCTL->PCEPHY |= 1;
- while (SYSCTL->PREPHY != 0x01)
+ HWREG(SYSCTL_PCEPHY) |= 1;
+ while (HWREG(SYSCTL_PREPHY) != 0x01)
;
#if BOARD_PHY_RMII
- ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28);
+ HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
#else
- ETH->PC = EMAC_PHY_CONFIG;
+ HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG;
#endif
/*
@@ -310,12 +310,12 @@ void mac_lld_init(void)
/* Set done bit after writing EMACPC register */
mii_write(&ETHD1, TIVA_CFG1, (1 << 15) | mii_read(&ETHD1, TIVA_CFG1));
- while(ETH->DMABUSMOD & 1)
+ while(HWREG(EMAC_O_DMABUSMOD) & 1)
;
/* Reset MAC */
- ETH->DMABUSMOD |= 1;
- while (ETH->DMABUSMOD & 1)
+ HWREG(EMAC_O_DMABUSMOD) |= 1;
+ while (HWREG(EMAC_O_DMABUSMOD) & 1)
;
/* PHY address setup.*/
@@ -344,10 +344,10 @@ void mac_lld_init(void)
#endif
/* Disable MAC clock */
- SYSCTL->RCGCEMAC = 0;
+ HWREG(SYSCTL_RCGCEMAC) = 0;
/* Disable PHY clock */
- SYSCTL->RCGCEPHY = 0;
+ HWREG(SYSCTL_RCGCEPHY) = 0;
}
/**
@@ -374,13 +374,13 @@ void mac_lld_start(MACDriver *macp)
macp->txptr = (tiva_eth_tx_descriptor_t *)td;
/* Enable MAC clock */
- SYSCTL->RCGCEMAC = 1;
- while (SYSCTL->PREMAC != 0x01)
+ HWREG(SYSCTL_RCGCEMAC) = 1;
+ while (HWREG(SYSCTL_PREMAC) != 0x01)
;
/* Enable PHY clock */
- SYSCTL->RCGCEPHY = 1;
- while (!SYSCTL->PREPHY)
+ HWREG(SYSCTL_RCGCEPHY) = 1;
+ while (!HWREG(SYSCTL_PREPHY))
;
/* ISR vector enabled.*/
@@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp)
#endif
/* MAC configuration.*/
- ETH->FRAMEFLTR = 0;
- ETH->FLOWCTL = 0;
- ETH->VLANTG = 0;
+ HWREG(EMAC_O_FRAMEFLTR) = 0;
+ HWREG(EMAC_O_FLOWCTL) = 0;
+ HWREG(EMAC_O_VLANTG) = 0;
/* MAC address setup.*/
if (macp->config->mac_address == NULL)
@@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp)
Note that the complete setup of the MAC is performed when the link
status is detected.*/
#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
- ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2);
+ HWREG(EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
#else
- ETH->CFG = (1 << 3) | (1 << 2);
+ HWREG(EMAC_O_CFG) = (1 << 3) | (1 << 2);
#endif
/* DMA configuration:
Descriptor chains pointers.*/
- ETH->RXDLADDR = (uint32_t)rd;
- ETH->TXDLADDR = (uint32_t)td;
+ HWREG(EMAC_O_RXDLADDR) = (uint32_t)rd;
+ HWREG(EMAC_O_TXDLADDR) = (uint32_t)td;
/* Enabling required interrupt sources.*/
- ETH->DMARIS &= 0xFFFF;
- ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0);
+ HWREG(EMAC_O_DMARIS) &= 0xFFFF;
+ HWREG(EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
/* DMA general settings.*/
- ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8);
+ HWREG(EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
/* Transmit FIFO flush.*/
- ETH->DMAOPMODE = (1 << 20);
- while (ETH->DMAOPMODE & (1 << 20))
+ HWREG(EMAC_O_DMAOPMODE) = (1 << 20);
+ while (HWREG(EMAC_O_DMAOPMODE) & (1 << 20))
;
/* DMA final configuration and start.*/
- ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) |
+ HWREG(EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
(1 << 13) | (1 << 1);
}
@@ -449,16 +449,16 @@ void mac_lld_stop(MACDriver *macp)
#endif
/* MAC and DMA stopped.*/
- ETH->CFG = 0;
- ETH->DMAOPMODE = 0;
- ETH->DMAIM = 0;
- ETH->DMARIS &= 0xFFFF;
+ HWREG(EMAC_O_CFG) = 0;
+ HWREG(EMAC_O_DMAOPMODE) = 0;
+ HWREG(EMAC_O_DMAIM) = 0;
+ HWREG(EMAC_O_DMARIS) &= 0xFFFF;
/* MAC clocks stopped.*/
- SYSCTL->RCGCEMAC = 0;
+ HWREG(SYSCTL_RCGCEMAC) = 0;
/* PHY clock stopped.*/
- SYSCTL->RCGCEPHY = 0;
+ HWREG(SYSCTL_RCGCEPHY) = 0;
/* ISR vector disabled.*/
nvicDisableVector(TIVA_MAC_NUMBER);
@@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
tdp->physdesc->locked = 0;
/* If the DMA engine is stalled then a restart request is issued.*/
- if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) {
- ETH->DMARIS = (1 << 2);
- ETH->TXPOLLD = 1; /* Any value is OK.*/
+ if ((HWREG(EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
+ HWREG(EMAC_O_DMARIS) = (1 << 2);
+ HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
}
osalSysUnlock();
@@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
/* If the DMA engine is stalled then a restart request is issued.*/
- if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) {
- ETH->DMARIS = (1 << 7);
- ETH->TXPOLLD = 1; /* Any value is OK.*/
+ if ((HWREG(EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
+ HWREG(EMAC_O_DMARIS) = (1 << 7);
+ HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
}
osalSysUnlock();
@@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
{
uint32_t maccfg, bmsr, bmcr;
- maccfg = ETH->CFG;
+ maccfg = HWREG(EMAC_O_CFG);
/* PHY CR and SR registers read.*/
(void)mii_read(macp, MII_BMSR);
@@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
}
/* Changes the mode in the MAC.*/
- ETH->CFG = maccfg;
+ HWREG(EMAC_O_CFG) = maccfg;
/* Returns the link status.*/
return macp->link_up = true;
diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h
index 98036bb..98036bb 100644
--- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h
+++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h
diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
index ad7c587..964f45b 100644
--- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c
+++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c
@@ -30,13 +30,6 @@
/* Driver local definitions. */
/*===========================================================================*/
-#define PWM_INT_CMPBD (1 << 5)
-#define PWM_INT_CMPBU (1 << 4)
-#define PWM_INT_CMPAD (1 << 3)
-#define PWM_INT_CMPAU (1 << 2)
-#define PWM_INT_CNTLOAD (1 << 1)
-#define PWM_INT_CNTZERO (1 << 0)
-
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -59,6 +52,8 @@ PWMDriver PWMD2;
/* Driver local variables and types. */
/*===========================================================================*/
+static uint32_t pwm_generator_offsets[] = { PWM_GEN_0_OFFSET, PWM_GEN_1_OFFSET, PWM_GEN_2_OFFSET, PWM_GEN_3_OFFSET};
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -75,35 +70,36 @@ PWMDriver PWMD2;
static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i)
{
uint32_t isc;
+ uint32_t pwm = pwmp->pwm;
- isc = pwmp->pwm->PWM[i].ISC;
- pwmp->pwm->PWM[i].ISC = isc;
+ isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC);
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc;
- if (((isc & PWM_INT_CMPAD) != 0) &&
+ if (((isc & PWM_X_ISC_INTCMPAD) != 0) &&
(pwmp->config->channels[i * 2 + 0].callback != NULL)) {
pwmp->config->channels[i * 2 + 0].callback(pwmp);
}
- if (((isc & PWM_INT_CMPAU) != 0) &&
+ if (((isc & PWM_X_ISC_INTCMPAU) != 0) &&
(pwmp->config->channels[i * 2 + 0].callback != NULL)) {
pwmp->config->channels[i * 2 + 0].callback(pwmp);
}
- if (((isc & PWM_INT_CMPBD) != 0) &&
+ if (((isc & PWM_X_ISC_INTCMPBD) != 0) &&
(pwmp->config->channels[i * 2 + 1].callback != NULL)) {
pwmp->config->channels[i * 2 + 1].callback(pwmp);
}
- if (((isc & PWM_INT_CMPBU) != 0) &&
+ if (((isc & PWM_X_ISC_INTCMPBU) != 0) &&
(pwmp->config->channels[i * 2 + 1].callback != NULL)) {
pwmp->config->channels[i * 2 + 1].callback(pwmp);
}
- if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) {
+ if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) {
pwmp->config->callback(pwmp);
}
- if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) {
+ if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) {
pwmp->config->callback(pwmp);
}
}
@@ -311,13 +307,13 @@ void pwm_lld_init(void)
#if TIVA_PWM_USE_PWM0
pwmObjectInit(&PWMD1);
PWMD1.channels = PWM_CHANNELS;
- PWMD1.pwm = PWM0;
+ PWMD1.pwm = PWM0_BASE;
#endif
#if TIVA_PWM_USE_PWM1
pwmObjectInit(&PWMD2);
PWMD2.channels = PWM_CHANNELS;
- PWMD2.pwm = PWM1;
+ PWMD2.pwm = PWM1_BASE;
#endif
}
@@ -335,14 +331,15 @@ void pwm_lld_start(PWMDriver *pwmp)
uint8_t i;
uint32_t invert = 0;
uint32_t enable = 0;
+ uint32_t pwm = pwmp->pwm;
if (pwmp->state == PWM_STOP) {
/* Clock activation.*/
#if TIVA_PWM_USE_PWM0
if (&PWMD1 == pwmp) {
- SYSCTL->RCGCPWM |= (1 << 0);
+ HWREG(SYSCTL_RCGCPWM) |= (1 << 0);
- while (!(SYSCTL->PRPWM & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRPWM) & (1 << 0)))
;
nvicEnableVector(TIVA_PWM0FAULT_NUMBER,
@@ -356,9 +353,9 @@ void pwm_lld_start(PWMDriver *pwmp)
#if TIVA_PWM_USE_PWM1
if (&PWMD2 == pwmp) {
- SYSCTL->RCGCPWM |= (1 << 1);
+ HWREG(SYSCTL_RCGCPWM) |= (1 << 1);
- while (!(SYSCTL->PRPWM & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRPWM) & (1 << 1)))
;
nvicEnableVector(TIVA_PWM1FAULT_NUMBER,
@@ -372,20 +369,20 @@ void pwm_lld_start(PWMDriver *pwmp)
}
else {
/* Driver re-configuration scenario, it must be stopped first.*/
- pwmp->pwm->PWM[0].CTL = 0;
- pwmp->pwm->PWM[1].CTL = 0;
- pwmp->pwm->PWM[2].CTL = 0;
- pwmp->pwm->PWM[3].CTL = 0;
+ HWREG(pwm + PWM_O_0_CTL) = 0;
+ HWREG(pwm + PWM_O_1_CTL) = 0;
+ HWREG(pwm + PWM_O_2_CTL) = 0;
+ HWREG(pwm + PWM_O_3_CTL) = 0;
}
/* Timer configuration.*/
for (i = 0; i < (PWM_CHANNELS >> 1); i++) {
- pwmp->pwm->PWM[i].CTL = 0;
- pwmp->pwm->PWM[i].GEN[0] = 0x08C;
- pwmp->pwm->PWM[i].GEN[1] = 0x80C;
- pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1);
- pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1);
- pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1);
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CTL) = 0;
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENA) = 0x08C;
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENB) = 0x80C;
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_LOAD) = (uint16_t)(pwmp->config->frequency - 1);
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPA) = (uint16_t)(pwmp->period - 1);
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPB) = (uint16_t)(pwmp->period - 1);
}
/* Output enables and polarities setup.*/
@@ -407,9 +404,9 @@ void pwm_lld_start(PWMDriver *pwmp)
}
}
- pwmp->pwm->INVERT = invert;
- pwmp->pwm->ENABLE = enable;
- pwmp->pwm->ISC = 0xFFFFFFFF;
+ HWREG(pwm + PWM_O_INVERT) = invert;
+ HWREG(pwm + PWM_O_ENABLE) = enable;
+ HWREG(pwm + PWM_O_ISC) = 0xFFFFFFFF;
}
/**
@@ -421,12 +418,14 @@ void pwm_lld_start(PWMDriver *pwmp)
*/
void pwm_lld_stop(PWMDriver *pwmp)
{
+ uint32_t pwm = pwmp->pwm;
+
/* If in ready state then disables the PWM clock.*/
if (pwmp->state == PWM_READY) {
- pwmp->pwm->PWM[0].CTL = 0;
- pwmp->pwm->PWM[1].CTL = 0;
- pwmp->pwm->PWM[2].CTL = 0;
- pwmp->pwm->PWM[3].CTL = 0;
+ HWREG(pwm + PWM_O_0_CTL) = 0;
+ HWREG(pwm + PWM_O_1_CTL) = 0;
+ HWREG(pwm + PWM_O_2_CTL) = 0;
+ HWREG(pwm + PWM_O_3_CTL) = 0;
#if TIVA_PWM_USE_PWM0
if (&PWMD1 == pwmp) {
@@ -435,7 +434,7 @@ void pwm_lld_stop(PWMDriver *pwmp)
nvicDisableVector(TIVA_PWM0GEN1_NUMBER);
nvicDisableVector(TIVA_PWM0GEN2_NUMBER);
nvicDisableVector(TIVA_PWM0GEN3_NUMBER);
- SYSCTL->RCGCPWM &= ~(1 << 0);
+ HWREG(SYSCTL_RCGCPWM) &= ~(1 << 0);
}
#endif
@@ -446,7 +445,7 @@ void pwm_lld_stop(PWMDriver *pwmp)
nvicDisableVector(TIVA_PWM1GEN1_NUMBER);
nvicDisableVector(TIVA_PWM1GEN2_NUMBER);
nvicDisableVector(TIVA_PWM1GEN3_NUMBER);
- SYSCTL->RCGCPWM &= ~(1 << 1);
+ HWREG(SYSCTL_RCGCPWM) &= ~(1 << 1);
}
#endif
}
@@ -469,9 +468,16 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width)
{
+ uint32_t pwm = pwmp->pwm;
+
/* Changing channel duty cycle on the fly.*/
- pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width;
- pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0);
+ if (channel & 1)
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = width;
+ else
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = width;
+
+
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0);
}
/**
@@ -488,8 +494,14 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel)
{
- pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0;
- pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0);
+ uint32_t pwm = pwmp->pwm;
+
+ if (channel & 1)
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = 0;
+ else
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = 0;
+
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0);
}
/**
@@ -505,18 +517,19 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp)
{
uint32_t inten;
uint8_t i;
+ uint32_t pwm = pwmp->pwm;
/* If the IRQ is not already enabled care must be taken to clear it,
it is probably already pending because the timer is running.*/
for(i = 0; i < (PWM_CHANNELS >> 1); i++) {
- inten = pwmp->pwm->PWM[i].INTEN;
+ inten = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN);
if ((inten & 0x03) == 0) {
- pwmp->pwm->PWM[i].INTEN |= 0x03;
- pwmp->pwm->PWM[i].ISC = 0x03;
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN) |= 0x03;
+ HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = 0x03;
}
}
- pwmp->pwm->INTEN = 0x3f;
+ HWREG(pwm + PWM_O_INTEN) = 0x3f;
}
/**
@@ -530,11 +543,14 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp)
*/
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp)
{
- pwmp->pwm->PWM[0].INTEN &= ~(0x03);
- pwmp->pwm->PWM[1].INTEN &= ~(0x03);
- pwmp->pwm->PWM[2].INTEN &= ~(0x03);
- pwmp->pwm->PWM[3].INTEN &= ~(0x03);
- pwmp->pwm->INTEN &= ~(0x3F);
+ uint32_t pwm = pwmp->pwm;
+
+ HWREG(pwm + PWM_O_0_INTEN) = ~(0x03);
+ HWREG(pwm + PWM_O_1_INTEN) = ~(0x03);
+ HWREG(pwm + PWM_O_2_INTEN) = ~(0x03);
+ HWREG(pwm + PWM_O_3_INTEN) = ~(0x03);
+
+ HWREG(pwm + PWM_O_INTEN) &= ~(0x3F);
}
/**
@@ -551,13 +567,14 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp)
void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel)
{
- uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN;
+ uint32_t pwm = pwmp->pwm;
+ uint32_t inten = HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC);
/* If the IRQ is not already enabled care must be taken to clear it,
it is probably already pending because the timer is running.*/
if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) {
- pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2));
- pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2));
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) |= (0x03 << (((channel & 1) * 2) + 2));
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC) = (0x03 << (((channel & 1) * 2) + 2));
}
}
@@ -575,7 +592,9 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel)
{
- pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2));
+ uint32_t pwm = pwmp->pwm;
+
+ HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) = ~(0x03 << (((channel & 1) * 2) + 2));
}
#endif /* HAL_USE_PWM */
diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h
index ac64fe1..7ddbd4d 100644
--- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h
+++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h
@@ -304,7 +304,7 @@ struct PWMDriver {
/**
* @brief Pointer to the PWMx registers block.
*/
- PWM_TypeDef *pwm;
+ uint32_t pwm;
};
/*===========================================================================*/
@@ -328,10 +328,10 @@ struct PWMDriver {
* @notapi
*/
#define pwm_lld_change_period(pwmp, period) \
- ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \
- ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \
- ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \
- ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1))
+ HWREG((pwmp)->pwm + PWM_O_0_LOAD) = (uint16_t)((period) - 1); \
+ HWREG((pwmp)->pwm + PWM_O_1_LOAD) = (uint16_t)((period) - 1); \
+ HWREG((pwmp)->pwm + PWM_O_2_LOAD) = (uint16_t)((period) - 1); \
+ HWREG((pwmp)->pwm + PWM_O_3_LOAD) = (uint16_t)((period) - 1)
/*===========================================================================*/
/* External declarations. */
diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
index ded2b99..42efca6 100644
--- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
@@ -77,19 +77,19 @@ static uint16_t dummyrx;
*/
static void spi_serve_interrupt(SPIDriver *spip)
{
- SSI_TypeDef *ssi = spip->ssi;
- uint32_t mis = ssi->MIS;
- uint32_t dmachis = UDMA->CHIS;
+ uint32_t ssi = spip->ssi;
+ uint32_t mis = HWREG(ssi + SSI_O_MIS);
+ uint32_t dmachis = HWREG(UDMA_CHIS);
/* SPI error handling.*/
- if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) {
+ if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) {
TIVA_SPI_SSI_ERROR_HOOK(spip);
}
- if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) ==
- ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) {
+ if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) ==
+ (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) {
/* Clear DMA Channel interrupts.*/
- UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr);
+ HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr);
/* Portable SPI ISR code defined in the high level driver, note, it is a
macro.*/
@@ -180,7 +180,7 @@ void spi_lld_init(void)
#if TIVA_SPI_USE_SSI0
spiObjectInit(&SPID1);
- SPID1.ssi = SSI0;
+ SPID1.ssi = SSI0_BASE;
SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL;
SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL;
SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING;
@@ -189,7 +189,7 @@ void spi_lld_init(void)
#if TIVA_SPI_USE_SSI1
spiObjectInit(&SPID2);
- SPID2.ssi = SSI1;
+ SPID2.ssi = SSI1_BASE;
SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL;
SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL;
SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING;
@@ -198,7 +198,7 @@ void spi_lld_init(void)
#if TIVA_SPI_USE_SSI2
spiObjectInit(&SPID3);
- SPID3.ssi = SSI2;
+ SPID3.ssi = SSI2_BASE;
SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL;
SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL;
SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING;
@@ -207,7 +207,7 @@ void spi_lld_init(void)
#if TIVA_SPI_USE_SSI3
spiObjectInit(&SPID4);
- SPID4.ssi = SSI3;
+ SPID4.ssi = SSI3_BASE;
SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL;
SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL;
SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING;
@@ -235,8 +235,8 @@ void spi_lld_start(SPIDriver *spip)
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
- SYSCTL->RCGCSSI |= (1 << 0);
- while (!(SYSCTL->PRSSI & (1 << 0)))
+ HWREG(SYSCTL_RCGCSSI) |= (1 << 0);
+ while (!(HWREG(SYSCTL_PRSSI) & (1 << 0)))
;
nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY);
@@ -251,8 +251,8 @@ void spi_lld_start(SPIDriver *spip)
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
- SYSCTL->RCGCSSI |= (1 << 1);
- while (!(SYSCTL->PRSSI & (1 << 1)))
+ HWREG(SYSCTL_RCGCSSI) |= (1 << 1);
+ while (!(HWREG(SYSCTL_PRSSI) & (1 << 1)))
;
nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY);
@@ -267,8 +267,8 @@ void spi_lld_start(SPIDriver *spip)
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
- SYSCTL->RCGCSSI |= (1 << 2);
- while (!(SYSCTL->PRSSI & (1 << 2)))
+ HWREG(SYSCTL_RCGCSSI) |= (1 << 2);
+ while (!(HWREG(SYSCTL_PRSSI) & (1 << 2)))
;
nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY);
@@ -283,40 +283,40 @@ void spi_lld_start(SPIDriver *spip)
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
- SYSCTL->RCGCSSI |= (1 << 3);
- while (!(SYSCTL->PRSSI & (1 << 3)))
+ HWREG(SYSCTL_RCGCSSI) |= (1 << 3);
+ while (!(HWREG(SYSCTL_PRSSI) & (1 << 3)))
;
nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY);
}
#endif
- UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8));
- UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8));
+ HWREG(UDMA_CHMAP0 + (spip->dmarxnr / 8) * 4) |= (spip->rxchnmap << (spip->dmarxnr % 8));
+ HWREG(UDMA_CHMAP0 + (spip->dmatxnr / 8) * 4) |= (spip->txchnmap << (spip->dmatxnr % 8));
}
/* Set master operation mode.*/
- spip->ssi->CR1 = 0;
+ HWREG(spip->ssi + SSI_O_CR1) = 0;
/* Clock configuration - System Clock.*/
- spip->ssi->CC = 0;
+ HWREG(spip->ssi + SSI_O_CC) = 0;
/* Clear pending interrupts.*/
- spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC;
+ HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC;
/* Enable Receive Time-Out and Receive Overrun Interrupts.*/
- spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM;
+ HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM;
/* Configure the clock prescale divisor.*/
- spip->ssi->CPSR = spip->config->cpsr;
+ HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr;
/* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/
- spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0);
+ HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO;
/* Enable SSI.*/
- spip->ssi->CR1 |= TIVA_CR1_SSE;
+ HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE;
/* Enable RX and TX DMA channels.*/
- spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE);
+ HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE);
}
/**
@@ -329,9 +329,9 @@ void spi_lld_start(SPIDriver *spip)
void spi_lld_stop(SPIDriver *spip)
{
if (spip->state != SPI_STOP) {
- spip->ssi->CR1 = 0;
- spip->ssi->CR0 = 0;
- spip->ssi->CPSR = 0;
+ HWREG(spip->ssi + SSI_O_CR1) = 0;
+ HWREG(spip->ssi + SSI_O_CR0) = 0;
+ HWREG(spip->ssi + SSI_O_CPSR) = 0;
udmaChannelRelease(spip->dmarxnr);
udmaChannelRelease(spip->dmatxnr);
@@ -399,20 +399,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
- if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+ if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
/* Configure for 8-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = &dummyrx;
- primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -420,17 +420,17 @@ void spi_lld_ignore(SPIDriver *spip, size_t n)
else {
/* Configure for 16-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = &dummyrx;
- primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -470,20 +470,20 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
- if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+ if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
/* Configure for 8-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = rxbuf+n-1;
primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -491,17 +491,17 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
else {
/* Configure for 16-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -539,20 +539,20 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
- if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+ if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
/* Configure for 8-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].srcendp = &dummyrx;
- primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -560,17 +560,17 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf)
else {
/* Configure for 16-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].srcendp = &dummyrx;
- primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -608,20 +608,20 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
- if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+ if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) {
/* Configure for 8-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = rxbuf+n-1;
primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
- UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+ UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -629,17 +629,17 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
else {
/* Configure for 16-bit transfers.*/
primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
- primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
- primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR);
+ primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
- primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+ primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR);
primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
- UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+ UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
@@ -674,10 +674,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf)
*/
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame)
{
- spip->ssi->DR = (uint32_t)frame;
- while ((spip->ssi->SR & TIVA_SR_RNE) == 0)
+ HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame;
+ while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0)
;
- return (uint16_t)spip->ssi->DR;
+ return (uint16_t)HWREG(spip->ssi + SSI_O_DR);
}
#endif /* HAL_USE_SPI */
diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
index 2adc9ed..dd49e84 100644
--- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
@@ -32,89 +32,9 @@
/*===========================================================================*/
/**
- * @name Control 0
- * @{
- */
-#define TIVA_CR0_DSS_MASK 0x0F
-#define TIVA_CR0_DSS(n) ((n-1) << 0)
-
-#define TIVA_CR0_FRF_MASK (3 << 4)
-#define TIVA_CR0_FRF(n) ((n) << 4)
-
-#define TIVA_CR0_SPO (1 << 6)
-#define TIVA_CR0_SPH (1 << 7)
-
-#define TIVA_CR0_SRC_MASK (0xFF << 8)
-#define TIVA_CR0_SRC(n) ((n) << 8)
-/** @} */
-
-/**
- * @name Control 1
- * @{
- */
-#define TIVA_CR1_LBM (1 << 0)
-#define TIVA_CR1_SSE (1 << 1)
-#define TIVA_CR1_MS (1 << 2)
-#define TIVA_CR1_SOD (1 << 3)
-#define TIVA_CR1_EOT (1 << 4)
-/** @} */
-
-/**
- * @name Status
- * @{
- */
-#define TIVA_SR_TFE (1 << 0)
-#define TIVA_SR_TNF (1 << 1)
-#define TIVA_SR_RNE (1 << 2)
-#define TIVA_SR_RFF (1 << 3)
-#define TIVA_SR_BSY (1 << 4)
-/** @} */
-
-/**
- * @name Interrupt Mask
- * @{
- */
-#define TIVA_IM_RORIM (1 << 0)
-#define TIVA_IM_RTIM (1 << 1)
-#define TIVA_IM_RXIM (1 << 2)
-#define TIVA_IM_TXIM (1 << 3)
-/** @} */
-
-/**
- * @name Interrupt Status
- * @{
- */
-#define TIVA_IS_RORIS (1 << 0)
-#define TIVA_IS_RTIS (1 << 1)
-#define TIVA_IS_RXIS (1 << 2)
-#define TIVA_IS_TXIS (1 << 3)
-/** @} */
-
-/**
- * @name Masked Interrupt Status
- * @{
- */
-#define TIVA_MIS_RORMIS (1 << 0)
-#define TIVA_MIS_RTMIS (1 << 1)
-#define TIVA_MIS_RXMIS (1 << 2)
-#define TIVA_MIS_TXMIS (1 << 3)
-/** @} */
-
-/**
- * @name Interrupt Clear
- * @{
- */
-#define TIVA_ICR_RORIC (1 << 0)
-#define TIVA_ICR_RTIC (1 << 1)
-/** @} */
-
-/**
- * @name DMA Control
- * @{
+ * @brief CR0 Serial Clock Rate helper.
*/
-#define TIVA_DMACTL_RXDMAE (1 << 0)
-#define TIVA_DMACTL_TXDMAE (1 << 1)
-/** @} */
+#define SSI_CR0_SCR(n) ((n) << 8)
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -320,7 +240,7 @@ struct SPIDriver {
/**
* @brief Pointer to the SSI registers block.
*/
- SSI_TypeDef *ssi;
+ uint32_t ssi;
/**
* @brief Receive DMA channel number.
*/
diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
index 89d29da..2e3b213 100644
--- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
@@ -34,58 +34,42 @@
/* Driver exported variables. */
/*===========================================================================*/
-/**
- * @brief UART0 serial driver identifier.
- */
+/** @brief UART0 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
-/**
- * @brief UART1 serial driver identifier.
- */
+/** @brief UART1 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
SerialDriver SD2;
#endif
-/**
- * @brief UART2 serial driver identifier.
- */
+/** @brief UART2 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
SerialDriver SD3;
#endif
-/**
- * @brief UART3 serial driver identifier.
- */
+/** @brief UART3 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
SerialDriver SD4;
#endif
-/**
- * @brief UART4 serial driver identifier.
- */
+/** @brief UART4 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
SerialDriver SD5;
#endif
-/**
- * @brief UART5 serial driver identifier.
- */
+/** @brief UART5 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
SerialDriver SD6;
#endif
-/**
- * @brief UART6 serial driver identifier.
- */
+/** @brief UART6 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
SerialDriver SD7;
#endif
-/**
- * @brief UART7 serial driver identifier.
- */
+/** @brief UART7 serial driver identifier.*/
#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
SerialDriver SD8;
#endif
@@ -94,14 +78,14 @@ SerialDriver SD8;
/* Driver local variables. */
/*===========================================================================*/
-/**
- * @brief Driver default configuration.
- */
+/** @brief Driver default configuration.*/
static const SerialConfig sd_default_config =
{
SERIAL_DEFAULT_BITRATE,
- TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8,
- TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E
+ 0,
+ UART_LCRH_FEN | UART_LCRH_WLEN_8,
+ UART_IFLS_TX4_8 | UART_IFLS_RX7_8,
+ UART_CC_CS_SYSCLK
};
/*===========================================================================*/
@@ -111,23 +95,55 @@ static const SerialConfig sd_default_config =
/**
* @brief UART initialization.
*
- * @param[in] sdp communication channel associated to the UART
+ * @param[in] sdp pointer to a @p SerialDriver object
* @param[in] config the architecture-dependent serial driver configuration
*/
static void uart_init(SerialDriver *sdp, const SerialConfig *config)
{
- UART_TypeDef *u = sdp->uart;
- uint32_t div; /* baud rate divisor */
-
- /* disable the UART before any of the control registers are reprogrammed */
- u->CTL &= ~TIVA_CTL_UARTEN;
- div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2;
- u->IBRD = div / 64; /* integer portion of the baud rate divisor */
- u->FBRD = div % 64; /* fractional portion of the baud rate divisor */
- u->LCRH = config->sc_lcrh; /* set data format */
- u->IFLS = config->sc_ifls;
- u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN;
- u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */
+ uint32_t u = sdp->uart;
+ uint32_t brd;
+ uint32_t speed = config->speed;
+ uint32_t clock_source;
+
+ if (config->ctl & UART_CTL_HSE) {
+ /* High speed mode is enabled, half the baud rate to compensate
+ * for high speed mode.*/
+ speed = (speed + 1) / 2;
+ }
+
+ if ((config->cc & UART_CC_CS_SYSCLK) == UART_CC_CS_SYSCLK) {
+ /* UART is clocked using the SYSCLK.*/
+ clock_source = TIVA_SYSCLK * 8;
+ }
+ else {
+ /* UART is clocked using the PIOSC.*/
+ clock_source = 16000000 * 8;
+ }
+
+ /* Calculate the baud rate divisor */
+ brd = ((clock_source / speed) + 1) / 2;
+
+ /* Disable UART.*/
+ HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
+
+ /* Set baud rate.*/
+ HWREG(u + UART_O_IBRD) = brd / 64;
+ HWREG(u + UART_O_FBRD) = brd % 64;
+
+ /* Line control/*/
+ HWREG(u + UART_O_LCRH) = config->lcrh;
+
+ /* Select clock source.*/
+ HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M;
+
+ /* FIFO configuration.*/
+ HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M);
+
+ /* Note that some bits are enforced.*/
+ HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
+
+ /* Enable interrupts.*/
+ HWREG(u + UART_O_IM) = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM;
}
/**
@@ -135,9 +151,9 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config)
*
* @param[in] u pointer to an UART I/O block
*/
-static void uart_deinit(UART_TypeDef *u)
+static void uart_deinit(uint32_t u)
{
- u->CTL &= ~TIVA_CTL_UARTEN;
+ HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
}
/**
@@ -150,13 +166,13 @@ static void set_error(SerialDriver *sdp, uint16_t err)
{
eventflags_t sts = 0;
- if (err & TIVA_MIS_FEMIS)
+ if (err & UART_MIS_FEMIS)
sts |= SD_FRAMING_ERROR;
- if (err & TIVA_MIS_PEMIS)
+ if (err & UART_MIS_PEMIS)
sts |= SD_PARITY_ERROR;
- if (err & TIVA_MIS_BEMIS)
+ if (err & UART_MIS_BEMIS)
sts |= SD_BREAK_DETECTED;
- if (err & TIVA_MIS_OEMIS)
+ if (err & UART_MIS_OEMIS)
sts |= SD_OVERRUN_ERROR;
osalSysLockFromISR();
chnAddFlagsI(sdp, sts);
@@ -174,44 +190,44 @@ static void set_error(SerialDriver *sdp, uint16_t err)
*/
static void serial_serve_interrupt(SerialDriver *sdp)
{
- UART_TypeDef *u = sdp->uart;
- uint16_t mis = u->MIS;
+ uint32_t u = sdp->uart;
+ uint16_t mis = HWREG(u + UART_O_MIS);
- u->ICR = mis; /* clear interrupts */
+ HWREG(u + UART_O_ICR) = mis; /* clear interrupts */
- if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) {
+ if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) {
set_error(sdp, mis);
}
- if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) {
+ if ((mis & UART_MIS_RXMIS) || (mis & UART_MIS_RTMIS)) {
osalSysLockFromISR();
if (iqIsEmptyI(&sdp->iqueue)) {
chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
}
osalSysUnlockFromISR();
- while ((u->FR & TIVA_FR_RXFE) == 0) {
+ while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) {
osalSysLockFromISR();
- if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) {
+ if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) {
chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
}
osalSysUnlockFromISR();
}
}
- if (mis & TIVA_MIS_TXMIS) {
- while ((u->FR & TIVA_FR_TXFF) == 0) {
+ if (mis & UART_MIS_TXMIS) {
+ while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
msg_t b;
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
osalSysUnlockFromISR();
if (b < Q_OK) {
- u->IM &= ~TIVA_IM_TXIM;
+ HWREG(u + UART_O_IM) &= ~UART_IM_TXIM;
osalSysLockFromISR();
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
osalSysUnlockFromISR();
break;
}
- u->DR = b;
+ HWREG(u + UART_O_DR) = b;
}
}
}
@@ -221,17 +237,18 @@ static void serial_serve_interrupt(SerialDriver *sdp)
*/
static void fifo_load(SerialDriver *sdp)
{
- UART_TypeDef *u = sdp->uart;
+ uint32_t u = sdp->uart;
- while ((u->FR & TIVA_FR_TXFF) == 0) {
+ while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
msg_t b = oqGetI(&sdp->oqueue);
if (b < Q_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
return;
}
- u->DR = b;
+ HWREG(u + UART_O_DR) = b;
}
- u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */
+
+ HWREG(u + UART_O_IM) |= UART_IM_TXIM; /* transmit interrupt enable */
}
/**
@@ -452,42 +469,42 @@ void sd_lld_init(void)
{
#if TIVA_SERIAL_USE_UART0
sdObjectInit(&SD1, NULL, notify1);
- SD1.uart = UART0;
+ SD1.uart = UART0_BASE;
#endif
#if TIVA_SERIAL_USE_UART1
sdObjectInit(&SD2, NULL, notify2);
- SD2.uart = UART1;
+ SD2.uart = UART1_BASE;
#endif
#if TIVA_SERIAL_USE_UART2
sdObjectInit(&SD3, NULL, notify3);
- SD3.uart = UART2;
+ SD3.uart = UART2_BASE;
#endif
#if TIVA_SERIAL_USE_UART3
sdObjectInit(&SD4, NULL, notify4);
- SD4.uart = UART3;
+ SD4.uart = UART3_BASE;
#endif
#if TIVA_SERIAL_USE_UART4
sdObjectInit(&SD5, NULL, notify5);
- SD5.uart = UART4;
+ SD5.uart = UART4_BASE;
#endif
#if TIVA_SERIAL_USE_UART5
sdObjectInit(&SD6, NULL, notify6);
- SD6.uart = UART5;
+ SD6.uart = UART5_BASE;
#endif
#if TIVA_SERIAL_USE_UART6
sdObjectInit(&SD7, NULL, notify7);
- SD7.uart = UART6;
+ SD7.uart = UART6_BASE;
#endif
#if TIVA_SERIAL_USE_UART7
sdObjectInit(&SD8, NULL, notify8);
- SD8.uart = UART7;
+ SD8.uart = UART7_BASE;
#endif
}
@@ -507,9 +524,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
if (sdp->state == SD_STOP) {
#if TIVA_SERIAL_USE_UART0
if (&SD1 == sdp) {
- SYSCTL->RCGCUART |= (1 << 0);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 0);
- while (!(SYSCTL->PRUART & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 0)))
;
nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY);
@@ -517,9 +534,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART1
if (&SD2 == sdp) {
- SYSCTL->RCGCUART |= (1 << 1);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 1);
- while (!(SYSCTL->PRUART & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 1)))
;
nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY);
@@ -527,9 +544,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART2
if (&SD3 == sdp) {
- SYSCTL->RCGCUART |= (1 << 2);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 2);
- while (!(SYSCTL->PRUART & (1 << 2)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 2)))
;
nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY);
@@ -537,9 +554,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART3
if (&SD4 == sdp) {
- SYSCTL->RCGCUART |= (1 << 3);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 3);
- while (!(SYSCTL->PRUART & (1 << 3)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 3)))
;
nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY);
@@ -547,9 +564,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART4
if (&SD5 == sdp) {
- SYSCTL->RCGCUART |= (1 << 4);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 4);
- while (!(SYSCTL->PRUART & (1 << 4)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 4)))
;
nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY);
@@ -557,9 +574,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART5
if (&SD6 == sdp) {
- SYSCTL->RCGCUART |= (1 << 5);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 5);
- while (!(SYSCTL->PRUART & (1 << 5)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 5)))
;
nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY);
@@ -567,9 +584,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART6
if (&SD7 == sdp) {
- SYSCTL->RCGCUART |= (1 << 6);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 6);
- while (!(SYSCTL->PRUART & (1 << 6)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 6)))
;
nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY);
@@ -577,9 +594,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
#endif
#if TIVA_SERIAL_USE_UART7
if (&SD8 == sdp) {
- SYSCTL->RCGCUART |= (1 << 7);
+ HWREG(SYSCTL_RCGCUART) |= (1 << 7);
- while (!(SYSCTL->PRUART & (1 << 7)))
+ while (!(HWREG(SYSCTL_PRUART) & (1 << 7)))
;
nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY);
@@ -602,56 +619,56 @@ void sd_lld_stop(SerialDriver *sdp)
uart_deinit(sdp->uart);
#if TIVA_SERIAL_USE_UART0
if (&SD1 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); /* disable UART0 module */
nvicDisableVector(TIVA_UART0_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART1
if (&SD2 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 1); /* disable UART1 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); /* disable UART1 module */
nvicDisableVector(TIVA_UART1_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART2
if (&SD3 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 2); /* disable UART2 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); /* disable UART2 module */
nvicDisableVector(TIVA_UART2_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART3
if (&SD4 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 3); /* disable UART3 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); /* disable UART3 module */
nvicDisableVector(TIVA_UART3_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART4
if (&SD5 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 4); /* disable UART4 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); /* disable UART4 module */
nvicDisableVector(TIVA_UART4_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART5
if (&SD6 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 5); /* disable UART5 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); /* disable UART5 module */
nvicDisableVector(TIVA_UART5_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART6
if (&SD7 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 6); /* disable UART6 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); /* disable UART6 module */
nvicDisableVector(TIVA_UART6_NUMBER);
return;
}
#endif
#if TIVA_SERIAL_USE_UART7
if (&SD8 == sdp) {
- SYSCTL->RCGCUART &= ~(1 << 7); /* disable UART7 module */
+ HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); /* disable UART7 module */
nvicDisableVector(TIVA_UART7_NUMBER);
return;
}
diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
index 203ef6a..d52828c 100644
--- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
@@ -31,163 +31,6 @@
/* Driver constants. */
/*===========================================================================*/
-/**
- * @name FR register bits definitions
- * @{
- */
-
-#define TIVA_FR_CTS (1 << 0)
-
-#define TIVA_FR_BUSY (1 << 3)
-
-#define TIVA_FR_RXFE (1 << 4)
-
-#define TIVA_FR_TXFF (1 << 5)
-
-#define TIVA_FR_RXFF (1 << 6)
-
-#define TIVA_FR_TXFE (1 << 7)
-
-/**
- * @}
- */
-
-/**
- * @name LCRH register bits definitions
- * @{
- */
-
-#define TIVA_LCRH_BRK (1 << 0)
-
-#define TIVA_LCRH_PEN (1 << 1)
-
-#define TIVA_LCRH_EPS (1 << 2)
-
-#define TIVA_LCRH_STP2 (1 << 3)
-
-#define TIVA_LCRH_FEN (1 << 4)
-
-#define TIVA_LCRH_WLEN_MASK (3 << 5)
-#define TIVA_LCRH_WLEN_5 (0 << 5)
-#define TIVA_LCRH_WLEN_6 (1 << 5)
-#define TIVA_LCRH_WLEN_7 (2 << 5)
-#define TIVA_LCRH_WLEN_8 (3 << 5)
-
-#define TIVA_LCRH_SPS (1 << 7)
-
-/**
- * @}
- */
-
-/**
- * @name CTL register bits definitions
- * @{
- */
-
-#define TIVA_CTL_UARTEN (1 << 0)
-
-#define TIVA_CTL_SIREN (1 << 1)
-
-#define TIVA_CTL_SIRLP (1 << 2)
-
-#define TIVA_CTL_SMART (1 << 3)
-
-#define TIVA_CTL_EOT (1 << 4)
-
-#define TIVA_CTL_HSE (1 << 5)
-
-#define TIVA_CTL_LBE (1 << 7)
-
-#define TIVA_CTL_TXE (1 << 8)
-
-#define TIVA_CTL_RXE (1 << 9)
-
-#define TIVA_CTL_RTS (1 << 11)
-
-#define TIVA_CTL_RTSEN (1 << 14)
-
-#define TIVA_CTL_CTSEN (1 << 15)
-
-/**
- * @}
- */
-
-/**
- * @name IFLS register bits definitions
- * @{
- */
-
-#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0)
-#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0)
-#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0)
-
-#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3)
-#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3)
-#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3)
-
-/**
- * @}
- */
-
-/**
- * @name MIS register bits definitions
- * @{
- */
-
-#define TIVA_MIS_CTSMIS (1 << 1)
-
-#define TIVA_MIS_RXMIS (1 << 4)
-
-#define TIVA_MIS_TXMIS (1 << 5)
-
-#define TIVA_MIS_RTMIS (1 << 6)
-
-#define TIVA_MIS_FEMIS (1 << 7)
-
-#define TIVA_MIS_PEMIS (1 << 8)
-
-#define TIVA_MIS_BEMIS (1 << 9)
-
-#define TIVA_MIS_OEMIS (1 << 10)
-
-#define TIVA_MIS_9BITMIS (1 << 12)
-
-/**
- * @}
- */
-
-/**
- * @name IM register bits definitions
- * @{
- */
-
-#define TIVA_IM_CTSIM (1 << 1)
-
-#define TIVA_IM_RXIM (1 << 4)
-
-#define TIVA_IM_TXIM (1 << 5)
-
-#define TIVA_IM_RTIM (1 << 6)
-
-#define TIVA_IM_FEIM (1 << 7)
-
-#define TIVA_IM_PEIM (1 << 8)
-
-#define TIVA_IM_BEIM (1 << 9)
-
-#define TIVA_IM_OEIM (1 << 10)
-
-#define TIVA_IM_9BITIM (1 << 12)
-
-/**
- * @}
- */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -388,22 +231,32 @@
* @brief Tiva Serial Driver configuration structure.
* @details An instance of this structure must be passed to @p sdStart()
* in order to configure and start a serial driver operations.
+ * @note This structure content is architecture dependent, each driver
+ * implementation defines its own version and the custom static
+ * initializers.
*/
typedef struct {
/**
* @brief Bit rate.
*/
- uint32_t sc_speed;
+ uint32_t speed;
/* End of the mandatory fields. */
/**
- * @brief Initialization value for the LCRH (Line Control) register.
+ * @brief Initialization value for the CTL register.
+ */
+ uint16_t ctl;
+ /**
+ * @brief Initialization value for the LCRH register.
+ */
+ uint8_t lcrh;
+ /**
+ * @brief Initialization value for the IFLS register.
*/
- uint32_t sc_lcrh;
+ uint8_t ifls;
/**
- * @brief Initialization value for the IFLS (Interrupt FIFO Level Select)
- * register.
+ * @brief Initialization value for the CC register.
*/
- uint32_t sc_ifls;
+ uint8_t cc;
} SerialConfig;
/**
@@ -423,7 +276,7 @@ typedef struct {
uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the USART registers block.*/ \
- UART_TypeDef *uart;
+ uint32_t uart;
/*===========================================================================*/
/* Driver macros. */
diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
index 38dcef0..ddd01e0 100644
--- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c
+++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c
@@ -60,14 +60,14 @@ static void serve_interrupt(WDGDriver *wdgp)
{
uint32_t mis;
- mis = wdgp->wdt->MIS;
+ mis = HWREG(wdgp->wdt + WDT_O_MIS);
- if (mis & MIS_WDTMIS) {
+ if (mis & WDT_MIS_WDTMIS) {
/* Invoke callback, if any */
if (wdgp->config->callback) {
if (wdgp->config->callback(wdgp)) {
/* Clear interrupt */
- wdgp->wdt->ICR = 0;
+ HWREG(wdgp->wdt + WDT_O_ICR) = 0;
wdgTivaSyncWrite(wdgp);
}
}
@@ -113,12 +113,12 @@ void wdg_lld_init(void)
{
#if TIVA_WDG_USE_WDT0
WDGD1.state = WDG_STOP;
- WDGD1.wdt = WDT0;
+ WDGD1.wdt = WATCHDOG0_BASE;
#endif /* TIVA_WDG_USE_WDT0 */
#if TIVA_WDG_USE_WDT1
WDGD2.state = WDG_STOP;
- WDGD2.wdt = WDT1;
+ WDGD2.wdt = WATCHDOG1_BASE;
#endif /* TIVA_WDG_USE_WDT1 */
/* The shared vector is initialized on driver initialization and never
@@ -137,32 +137,32 @@ void wdg_lld_start(WDGDriver *wdgp)
{
#if TIVA_WDG_USE_WDT0
if (&WDGD1 == wdgp) {
- SYSCTL->RCGCWD |= (1 << 0);
+ HWREG(SYSCTL_RCGCWD) |= (1 << 0);
- while (!(SYSCTL->PRWD & (1 << 0)))
+ while (!(HWREG(SYSCTL_PRWD) & (1 << 0)))
;
}
#endif /* TIVA_WDG_USE_WDT0 */
#if TIVA_WDG_USE_WDT1
if (&WDGD2 == wdgp) {
- SYSCTL->RCGCWD |= (1 << 1);
+ HWREG(SYSCTL_RCGCWD) |= (1 << 1);
- while (!(SYSCTL->PRWD & (1 << 1)))
+ while (!(HWREG(SYSCTL_PRWD) & (1 << 1)))
;
}
#endif /* TIVA_WDG_USE_WDT1 */
- wdgp->wdt->LOAD = wdgp->config->load;
+ HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load;
wdgTivaSyncWrite(wdgp);
- wdgp->wdt->TEST = wdgp->config->test;
+ HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test;
wdgTivaSyncWrite(wdgp);
- wdgp->wdt->CTL |= CTL_RESEN;
+ HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN;
wdgTivaSyncWrite(wdgp);
- wdgp->wdt->CTL |= CTL_INTEN;
+ HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN;
wdgTivaSyncWrite(wdgp);
}
@@ -177,15 +177,15 @@ void wdg_lld_stop(WDGDriver *wdgp)
{
#if TIVA_WDG_USE_WDT0
if (&WDGD1 == wdgp) {
- SYSCTL->SRWD |= (1 << 0);
- SYSCTL->SRWD &= ~(1 << 0);
+ HWREG(SYSCTL_SRWD) |= (1 << 0);
+ HWREG(SYSCTL_SRWD) &= ~(1 << 0);
}
#endif /* TIVA_WDG_USE_WDT0 */
#if TIVA_WDG_USE_WDT1
if (&WDGD2 == wdgp) {
- SYSCTL->SRWD |= (1 << 1);
- SYSCTL->SRWD &= ~(1 << 1);
+ HWREG(SYSCTL_SRWD) |= (1 << 1);
+ HWREG(SYSCTL_SRWD) &= ~(1 << 1);
}
#endif /* TIVA_WDG_USE_WDT1 */
}
@@ -219,7 +219,7 @@ void wdg_lld_reset(WDGDriver *wdgp)
#endif /* defined(TM4C123_USE_REVISION_6_FIX) ||
defined(TM4C123_USE_REVISION_7_FIX) */
- wdgp->wdt->LOAD = wdgp->config->load;
+ HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load;
wdgTivaSyncWrite(wdgp);
}
@@ -234,7 +234,7 @@ void wdg_lld_reset(WDGDriver *wdgp)
void wdgTivaSyncWrite(WDGDriver *wdgp)
{
if (&WDGD2 == wdgp) {
- while (!(wdgp->wdt->CTL & CTL_WRC)) {
+ while (!(HWREG(wdgp->wdt + WDT_O_CTL) & CTL_WRC)) {
;
}
}
diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h
index f88fa26..77badb3 100644
--- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h
+++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h
@@ -32,23 +32,6 @@
/* Driver constants. */
/*===========================================================================*/
-#define LOCK_UNLOCK 0x1ACCE551U
-#define LOCK_LOCK 0x00000000U
-
-#define LOCK_IS_UNLOCKED 0U
-#define LOCK_IS_LOCKED 1U
-
-#define TEST_STALL (1 << 8)
-
-#define MIS_WDTMIS (1 << 0)
-#define RIS_WDTRIS (1 << 0)
-#define ICR_WDTICR (1 << 0)
-
-#define CTL_INTEN (1 << 0)
-#define CTL_RESEN (1 << 1)
-#define CTL_INTTYPE (1 << 2)
-#define CTL_WRC (1 << 31)
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -146,7 +129,7 @@ struct WDGDriver
/**
* @brief Pointer to the WDT registers block.
*/
- WDT_TypeDef *wdt;
+ uint32_t wdt;
};
/*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h
deleted file mode 100644
index 114831b..0000000
--- a/os/hal/ports/TIVA/LLD/tiva_gpt.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- Copyright (C) 2014..2016 Marco Veeneman
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file tiva_gpt.h
- * @brief TIVA GPT registers layout header.
- *
- * @addtogroup TIVA_GPT
- * @{
- */
-
-#ifndef TIVA_GPT_H_
-#define TIVA_GPT_H_
-
-// cfg
-#define GPTM_CFG_CFG_MASK (7 << 0)
-#define GPTM_CFG_CFG_WHOLE (0 << 0)
-#define GPTM_CFG_CFG_RTC (1 << 0)
-#define GPTM_CFG_CFG_SPLIT (4 << 0)
-
-// tamr
-#define GPTM_TAMR_TAMR_MASK (3 << 0)
-#define GPTM_TAMR_TAMR_ONESHOT (1 << 0)
-#define GPTM_TAMR_TAMR_PERIODIC (2 << 0)
-#define GPTM_TAMR_TAMR_CAPTURE (3 << 0)
-
-#define GPTM_TAMR_TACMR (1 << 2)
-
-#define GPTM_TAMR_TAAMS (1 << 3)
-
-#define GPTM_TAMR_TACDIR (1 << 4)
-
-#define GPTM_TAMR_TAMIE (1 << 5)
-
-#define GPTM_TAMR_TAWOT (1 << 6)
-
-#define GPTM_TAMR_TASNAPS (1 << 7)
-
-#define GPTM_TAMR_TAILD (1 << 8)
-
-#define GPTM_TAMR_TAPWMIE (1 << 9)
-
-#define GPTM_TAMR_TAMRSU (1 << 10)
-
-#define GPTM_TAMR_TAPLO (1 << 11)
-
-// ctl
-#define GPTM_CTL_TAEN (1 << 0)
-
-#define GPTM_CTL_TASTALL (1 << 1)
-
-#define GPTM_CTL_TAEVENT_MASK (3 << 2)
-#define GPTM_CTL_TAEVENT_POS (0 << 2)
-#define GPTM_CTL_TAEVENT_NEG (1 << 2)
-#define GPTM_CTL_TAEVENT_BOTH (3 << 2)
-
-#define GPTM_CTL_RTCEN (1 << 4)
-
-#define GPTM_CTL_TAOTE (1 << 5)
-
-#define GPTM_CTL_TAPWML (1 << 6)
-
-#define GPTM_CTL_TBEN (1 << 8)
-
-#define GPTM_CTL_TBSTALL (1 << 9)
-
-#define GPTM_CTL_TBEVENT_MASK (3 << 10)
-#define GPTM_CTL_TBEVENT_POS (0 << 10)
-#define GPTM_CTL_TBEVENT_NEG (1 << 10)
-#define GPTM_CTL_TBEVENT_BOTH (3 << 10)
-
-#define GPTM_CTL_TBOTE (1 << 13)
-
-#define GPTM_CTL_TBPWML (1 << 14)
-
-// imr
-#define GPTM_IMR_TATOIM (1 << 0)
-
-#define GPTM_IMR_CAMIM (1 << 1)
-
-#define GPTM_IMR_CAEIM (1 << 2)
-
-#define GPTM_IMR_RTCIM (1 << 3)
-
-#define GPTM_IMR_TAMIM (1 << 4)
-
-#define GPTM_IMR_TBTOIM (1 << 8)
-
-#define GPTM_IMR_CBMIM (1 << 9)
-
-#define GPTM_IMR_CBEIM (1 << 10)
-
-#define GPTM_IMR_TBMIM (1 << 11)
-
-#define GPTM_IMR_WUEIM (1 << 16)
-
-// icr
-#define GPTM_ICR_TATOCINT (1 << 0)
-
-#define GPTM_ICR_CAMCINT (1 << 1)
-
-#define GPTM_ICR_CAECINT (1 << 2)
-
-#define GPTM_ICR_RTCCINT (1 << 3)
-
-#define GPTM_ICR_TAMCINT (1 << 4)
-
-#define GPTM_ICR_TBTOCINT (1 << 8)
-
-#define GPTM_ICR_CBMCINT (1 << 9)
-
-#define GPTM_ICR_CBECINT (1 << 10)
-
-#define GPTM_ICR_TBMCINT (1 << 11)
-
-#define GPTM_ICR_WUECINT (1 << 16)
-
-#endif /* TIVA_GPT_H_ */
-
-/*
- * @}
- */
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
index 9f122b2..bb379cb 100644
--- a/os/hal/ports/TIVA/LLD/tiva_udma.c
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
@@ -75,8 +75,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER)
/* TODO Do we need to halt the system on a DMA error?*/
- if (UDMA->ERRCLR) {
- UDMA->ERRCLR = 1;
+ if (HWREG(UDMA_ERRCLR)) {
+ HWREG(UDMA_ERRCLR) = 1;
}
OSAL_IRQ_EPILOGUE();
@@ -96,18 +96,18 @@ void udmaInit(void)
udma_channel_mask = 0;
/* Enable UDMA module.*/
- SYSCTL->RCGCDMA = 1;
- while (!(SYSCTL->PRDMA & (1 << 0)))
+ HWREG(SYSCTL_RCGCDMA) = 1;
+ while (!(HWREG(SYSCTL_PRDMA) & (1 << 0)))
;
nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY);
nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY);
/* Enable UDMA controller.*/
- UDMA->CFG = 1;
+ HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
/* Set address of control table.*/
- UDMA->CTLBASE = (uint32_t)udmaControlTable.primary;
+ HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary;
}
/**
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
index 6479b08..0157277 100644
--- a/os/hal/ports/TIVA/LLD/tiva_udma.h
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
@@ -22,52 +22,9 @@
/*===========================================================================*/
/**
- * @name CHCTL register defines.
- * @{
+ * @brief CHCTL XFERSIZE helper.
*/
-#define UDMA_CHCTL_DSTINC_MASK 0xC0000000
-#define UDMA_CHCTL_DSTINC_0 0xC0000000
-#define UDMA_CHCTL_DSTINC_8 0x00000000
-#define UDMA_CHCTL_DSTINC_16 0x40000000
-#define UDMA_CHCTL_DSTINC_32 0x80000000
-#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000
-#define UDMA_CHCTL_DSTSIZE_8 0x00000000
-#define UDMA_CHCTL_DSTSIZE_16 0x10000000
-#define UDMA_CHCTL_DSTSIZE_32 0x20000000
-#define UDMA_CHCTL_SRCINC_MASK 0x0C000000
-#define UDMA_CHCTL_SRCINC_0 0x0C000000
-#define UDMA_CHCTL_SRCINC_8 0x00000000
-#define UDMA_CHCTL_SRCINC_16 0x04000000
-#define UDMA_CHCTL_SRCINC_32 0x08000000
-#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000
-#define UDMA_CHCTL_SRCSIZE_8 0x00000000
-#define UDMA_CHCTL_SRCSIZE_16 0x01000000
-#define UDMA_CHCTL_SRCSIZE_32 0x02000000
-#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000
-#define UDMA_CHCTL_ARBSIZE_1 0x00000000
-#define UDMA_CHCTL_ARBSIZE_2 0x00004000
-#define UDMA_CHCTL_ARBSIZE_4 0x00008000
-#define UDMA_CHCTL_ARBSIZE_8 0x0000C000
-#define UDMA_CHCTL_ARBSIZE_16 0x00010000
-#define UDMA_CHCTL_ARBSIZE_32 0x00014000
-#define UDMA_CHCTL_ARBSIZE_64 0x00018000
-#define UDMA_CHCTL_ARBSIZE_128 0x0001C000
-#define UDMA_CHCTL_ARBSIZE_256 0x00020000
-#define UDMA_CHCTL_ARBSIZE_512 0x00024000
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000
-#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0
#define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4)
-#define UDMA_CHCTL_NXTUSEBURST 0x00000008
-#define UDMA_CHCTL_XFERMODE_MASK 0x00000007
-#define UDMA_CHCTL_XFERMODE_STOP 0x00000000
-#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001
-#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002
-#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003
-#define UDMA_CHCTL_XFERMODE_MSG 0x00000004
-#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005
-#define UDMA_CHCTL_XFERMODE_PSG 0x00000006
-#define UDMA_CHCTL_XFERMODE_APSG 0x00000007
-/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -137,43 +94,43 @@ typedef struct __attribute__((packed, aligned(1024)))
/*===========================================================================*/
#define dmaChannelEnable(dmach) {\
- UDMA->ENASET = (1 << dmach);\
+ HWREG(UDMA_ENASET) = (1 << dmach);\
}
#define dmaChannelDisable(dmach) { \
- UDMA->ENACLR = (1 << dmach); \
+ HWREG(UDMA_ENACLR) = (1 << dmach); \
}
#define dmaChannelPrimary(dmach) {\
- UDMA->ALTCLR = (1 << dmach); \
+ HWREG(UDMA_ALTCLR) = (1 << dmach); \
}
#define dmaChannelAlternate(dmach) { \
- UDMA->ALTSET = (1 << dmach); \
+ HWREG(UDMA_ALTSET) = (1 << dmach); \
}
#define dmaChannelSingleBurst(dmach) { \
- UDMA->USEBURSTCLR = (1 << dmach); \
+ HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \
}
#define dmaChannelBurstOnly(dmach) { \
- UDMA->USEBURSTSET = (1 << dmach); \
+ HWREG(UDMA_USEBURSTSET) = (1 << dmach); \
}
#define dmaChannelPriorityHigh(dmach) { \
- UDMA->PRIOSET = (1 << dmach); \
+ HWREG(UDMA_PRIOSET) = (1 << dmach); \
}
#define dmaChannelPriorityDefault(dmach) { \
- UDMA->PRIOCLR = (1 << dmach); \
+ HWREG(UDMA_PRIOCLR) = (1 << dmach); \
}
#define dmaChannelEnableRequest(dmach) {\
- UDMA->REQMASKCLR = (1 << dmach); \
+ HWREG(UDMA_REQMASKCLR) = (1 << dmach); \
}
#define dmaChannelDisableRequest(dmach) {\
- UDMA->REQMASKSET = (1 << dmach); \
+ HWREG(UDMA_REQMASKSET) = (1 << dmach); \
}
/*===========================================================================*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 20:38:27 +0000