diff options
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_i2c_lld.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_pal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h | 8 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h | 14 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_pal_lld.h | 2 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c | 77 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h | 71 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_rng_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_serial_lld.h | 7 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_spi_lld.h | 14 | ||||
| -rw-r--r-- | os/hal/ports/NRF51/NRF51822/hal_st_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c | 293 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h | 347 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/platform.mk | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/platform.mk | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/platform.mk | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/platform.mk | 1 |
18 files changed, 824 insertions, 37 deletions
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h index 3576b60..bfc5008 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h @@ -157,14 +157,10 @@ struct I2CDriver { */
i2cflags_t errors;
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
mutex_t mutex;
-#elif CH_CFG_USE_SEMAPHORES
- semaphore_t semaphore;
-#endif
#endif /* I2C_USE_MUTUAL_EXCLUSION */
#if defined(I2C_DRIVER_EXT_FIELDS)
I2C_DRIVER_EXT_FIELDS
diff --git a/os/hal/ports/KINETIS/LLD/hal_pal_lld.c b/os/hal/ports/KINETIS/LLD/hal_pal_lld.c index b307833..51f8a2e 100644 --- a/os/hal/ports/KINETIS/LLD/hal_pal_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_pal_lld.c @@ -108,7 +108,7 @@ void _pal_lld_setpadmode(ioportid_t port, PORT_TypeDef *portcfg = NULL;
- chDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
+ osalDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
if (mode == PAL_MODE_OUTPUT_PUSHPULL)
port->PDDR |= ((uint32_t) 1 << pad);
@@ -126,7 +126,7 @@ void _pal_lld_setpadmode(ioportid_t port, else if (port == IOPORT5)
portcfg = PORTE;
- chDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");
+ osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");
switch (mode) {
case PAL_MODE_RESET:
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c index 159aef9..e8d9778 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -420,7 +420,7 @@ void usb_lld_init(void) { }
}
usbfrac_match_found:
- chDbgAssert(i<2 && j <8,"USB Init error");
+ osalDbgAssert(i<2 && j <8,"USB Init error");
#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
#error USB clock setting not implemented for this KINETIS_MCG_MODE
diff --git a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h b/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h index 748be0a..9b4cc9b 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h @@ -70,21 +70,21 @@ * @brief GPTD1 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER0_IRQ_PRIORITY 7
+#define NRF51_GPT_TIMER0_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD2 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER1_IRQ_PRIORITY 7
+#define NRF51_GPT_TIMER1_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD3 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER2_IRQ_PRIORITY 7
+#define NRF51_GPT_TIMER2_IRQ_PRIORITY 3
#endif
/** @} */
@@ -97,7 +97,6 @@ #error "GPT driver activated but no TIMER peripheral assigned"
#endif
-#if 0
#if NRF51_GPT_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER0"
@@ -112,7 +111,6 @@ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER2"
#endif
-#endif
/*===========================================================================*/
/* Driver data structures and types. */
diff --git a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h b/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h index 555ced1..e2c3d07 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h @@ -66,14 +66,14 @@ * @brief I2C0 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_I2C_I2C0_IRQ_PRIORITY 10
+#define NRF51_I2C_I2C0_IRQ_PRIORITY 3
#endif
/**
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_I2C_I2C1_IRQ_PRIORITY 10
+#define NRF51_I2C_I2C1_IRQ_PRIORITY 3
#endif
/** @} */
@@ -81,6 +81,16 @@ /* Derived constants and error checks. */
/*===========================================================================*/
+#if NRF51_I2C_USE_I2C0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C0"
+#endif
+
+#if NRF51_I2C_USE_I2C1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h b/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h index e5b62ee..5032916 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h @@ -80,7 +80,7 @@ /**
* @brief Value identifying an invalid line.
*/
-#define PAL_NOLINE FFU
+#define PAL_NOLINE ((ioline_t)-1)
/** @} */
/**
diff --git a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c b/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c index 76bc572..456dcff 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c +++ b/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c @@ -68,25 +68,27 @@ PWMDriver PWMD3; /*===========================================================================*/
static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- // Deal with PWM period
- if (pwmp->timer->EVENTS_COMPARE[pwmp->channels]) {
- pwmp->timer->EVENTS_COMPARE[pwmp->channels] = 0;
-
- if (pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- }
- }
-
// Deal with PWM channels
uint8_t n;
for (n = 0 ; n < pwmp->channels ; n++) {
if (pwmp->timer->EVENTS_COMPARE[n]) {
pwmp->timer->EVENTS_COMPARE[n] = 0;
+
if (pwmp->config->channels[n].callback != NULL) {
pwmp->config->channels[n].callback(pwmp);
}
}
}
+
+ // Deal with PWM period
+ if (pwmp->timer->EVENTS_COMPARE[pwmp->channels]) {
+ pwmp->timer->EVENTS_COMPARE[pwmp->channels] = 0;
+
+ if (pwmp->config->callback != NULL) {
+ pwmp->config->callback(pwmp);
+ }
+ }
+
}
/*===========================================================================*/
@@ -280,6 +282,47 @@ void pwm_lld_stop(PWMDriver *pwmp) { void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
+#if NRF51_PWM_USE_GPIOTE_PPI
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+
+ uint32_t outinit;
+ switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_LOW:
+ outinit = GPIOTE_CONFIG_OUTINIT_Low;
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ outinit = GPIOTE_CONFIG_OUTINIT_High;
+ break;
+ case PWM_OUTPUT_DISABLED:
+ default:
+ goto no_output_config;
+ }
+
+ const uint32_t gpio_pin = PAL_PAD(cfg_channel->ioline);
+ const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
+ const uint8_t *ppi_channel = cfg_channel->ppi_channel;
+ const uint32_t polarity = GPIOTE_CONFIG_POLARITY_Toggle;
+
+ // Create GPIO Task
+ NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Task |
+ ((gpio_pin << GPIOTE_CONFIG_PSEL_Pos ) & GPIOTE_CONFIG_PSEL_Msk) |
+ ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
+ ((outinit << GPIOTE_CONFIG_OUTINIT_Pos ) & GPIOTE_CONFIG_OUTINIT_Msk);
+
+ // Program tasks (one for duty cycle, one for periode)
+ NRF_PPI->CH[ppi_channel[0]].EEP =
+ (uint32_t)&pwmp->timer->EVENTS_COMPARE[channel];
+ NRF_PPI->CH[ppi_channel[0]].TEP =
+ (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
+ NRF_PPI->CH[ppi_channel[1]].EEP =
+ (uint32_t)&pwmp->timer->EVENTS_COMPARE[pwmp->channels];
+ NRF_PPI->CH[ppi_channel[1]].TEP =
+ (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
+ NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
+
+ no_output_config:
+#endif
+
pwmp->timer->CC[channel] = width;
}
@@ -297,6 +340,22 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
pwmp->timer->CC[channel] = 0;
+#if NRF51_PWM_USE_GPIOTE_PPI
+ const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
+ switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_LOW:
+ case PWM_OUTPUT_ACTIVE_HIGH: {
+ const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
+ const uint8_t *ppi_channel = cfg_channel->ppi_channel;
+ NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
+ NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Disabled;
+ break;
+ }
+ case PWM_OUTPUT_DISABLED:
+ default:
+ break;
+ }
+#endif
}
/**
diff --git a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h b/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h index 0ddd65c..e2982d8 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h @@ -52,14 +52,28 @@ /* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief TIMER0 as driver implementation
+ */
#if !defined(NRF51_PWM_USE_TIMER0)
#define NRF51_PWM_USE_TIMER0 FALSE
#endif
+/**
+ * @brief TIMER1 as driver implementation
+ */
#if !defined(NRF51_PWM_USE_TIMER1)
#define NRF51_PWM_USE_TIMER1 FALSE
#endif
+/**
+ * @brief TIMER2 as driver implementation
+ */
#if !defined(NRF51_PWM_USE_TIMER2)
#define NRF51_PWM_USE_TIMER2 FALSE
#endif
@@ -68,29 +82,30 @@ * @brief TIMER0 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER0_PRIORITY 12
+#define NRF51_PWM_TIMER0_PRIORITY 3
#endif
/**
* @brief TIMER1 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER1_PRIORITY 12
+#define NRF51_PWM_TIMER1_PRIORITY 3
#endif
/**
* @brief TIMER2 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER2_PRIORITY 12
+#define NRF51_PWM_TIMER2_PRIORITY 3
#endif
-/** @} */
-
/**
- * @name Configuration options
- * @{
+ * @brief Allow driver to use GPIOTE/PPI to control PAL line
*/
+#if !defined(NRF51_PWM_USE_GPIOTE_PPI)
+#define NRF51_PWM_USE_GPIOTE_PPI FALSE
+#endif
+
/** @} */
/*===========================================================================*/
@@ -105,6 +120,22 @@ #error "TIMER0 used for ST and PWM"
#endif
+#if NRF51_PWM_USE_TIMER0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER0_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER0"
+#endif
+
+#if NRF51_PWM_USE_TIMER1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER1_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER1"
+#endif
+
+#if NRF51_PWM_USE_TIMER2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER2_PRIORITY)
+#error "Invalid IRQ priority assigned to TIMER2"
+#endif
+
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -145,6 +176,32 @@ typedef struct { */
pwmcallback_t callback;
/* End of the mandatory fields.*/
+
+ /**
+ * @brief PAL line to toggle.
+ * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
+ * @note When NRF51_PWM_USE_GPIOTE_PPI is used and channel enabled,
+ * it wont be possible to access this PAL line using the PAL
+ * driver.
+ */
+ ioline_t ioline;
+
+#if NRF51_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
+ /**
+ * @brief Unique GPIOTE channel to use. (1 channel)
+ * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
+ * @note Only 4 GPIOTE channels are available on nRF51.
+ */
+ uint8_t gpiote_channel;
+
+ /**
+ * @brief Unique PPI channels to use. (2 channels)
+ * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
+ * @note Only 16 PPI channels are available on nRF51
+ * (When Softdevice is enabled, only channels 0-7 are available)
+ */
+ uint8_t ppi_channel[2];
+#endif
} PWMChannelConfig;
/**
diff --git a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h b/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h index 475770b..0ad0bc6 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h @@ -61,7 +61,7 @@ * @brief RNG1 interrupt priority level setting. */ #if !defined(NRF51_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define NRF51_RNG_RNG1_IRQ_PRIORITY 10 +#define NRF51_RNG_RNG1_IRQ_PRIORITY 3 #endif @@ -69,6 +69,10 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +#if NRF51_RNG_USE_RNG1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_RNG_RNG1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to RNG1" +#endif /*===========================================================================*/ /* Driver data structures and types. */ diff --git a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h b/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h index 304c07d..79955b1 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h @@ -62,7 +62,7 @@ * @brief UART0 interrupt priority level setting.
*/
#if !defined(NRF51_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SERIAL_UART0_PRIORITY 12
+#define NRF51_SERIAL_UART0_PRIORITY 3
#endif
/* Value indicating that no pad is connected to this UART register. */
@@ -75,6 +75,11 @@ /* Derived constants and error checks. */
/*===========================================================================*/
+#if NRF51_SERIAL_USE_UART0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SERIAL_UART0_PRIORITY)
+#error "Invalid IRQ priority assigned to UART0"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h b/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h index d339a91..4d1c452 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h @@ -39,14 +39,14 @@ * @brief SPI0 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SPI_SPI0_IRQ_PRIORITY 10
+#define NRF51_SPI_SPI0_IRQ_PRIORITY 3
#endif
/**
* @brief SPI1 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SPI_SPI1_IRQ_PRIORITY 10
+#define NRF51_SPI_SPI1_IRQ_PRIORITY 3
#endif
/**
@@ -65,6 +65,16 @@ #error "SPI driver activated but no SPI peripheral assigned"
#endif
+#if NRF51_SPI_USE_SPI0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI0"
+#endif
+
+#if NRF51_SPI_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/NRF51/NRF51822/hal_st_lld.h b/os/hal/ports/NRF51/NRF51822/hal_st_lld.h index bde9950..8d12d2e 100644 --- a/os/hal/ports/NRF51/NRF51822/hal_st_lld.h +++ b/os/hal/ports/NRF51/NRF51822/hal_st_lld.h @@ -71,7 +71,7 @@ */
#if !defined(NRF51_ST_PRIORITY) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
-#define NRF51_ST_PRIORITY 8
+#define NRF51_ST_PRIORITY 1
#else
#define NRF51_ST_PRIORITY 1
#endif
@@ -123,6 +123,10 @@ #endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ST_PRIORITY)
+#error "Invalid IRQ priority assigned to ST driver"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c new file mode 100644 index 0000000..ea051f7 --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -0,0 +1,293 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIMv1/hal_qei_lld.c
+ * @brief STM32 QEI subsystem low level driver header.
+ *
+ * @addtogroup QEI
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief QEID1 driver identifier.
+ * @note The driver QEID1 allocates the complex timer TIM1 when enabled.
+ */
+#if STM32_QEI_USE_TIM1 || defined(__DOXYGEN__)
+QEIDriver QEID1;
+#endif
+
+/**
+ * @brief QEID2 driver identifier.
+ * @note The driver QEID1 allocates the timer TIM2 when enabled.
+ */
+#if STM32_QEI_USE_TIM2 || defined(__DOXYGEN__)
+QEIDriver QEID2;
+#endif
+
+/**
+ * @brief QEID3 driver identifier.
+ * @note The driver QEID1 allocates the timer TIM3 when enabled.
+ */
+#if STM32_QEI_USE_TIM3 || defined(__DOXYGEN__)
+QEIDriver QEID3;
+#endif
+
+/**
+ * @brief QEID4 driver identifier.
+ * @note The driver QEID4 allocates the timer TIM4 when enabled.
+ */
+#if STM32_QEI_USE_TIM4 || defined(__DOXYGEN__)
+QEIDriver QEID4;
+#endif
+
+/**
+ * @brief QEID5 driver identifier.
+ * @note The driver QEID5 allocates the timer TIM5 when enabled.
+ */
+#if STM32_QEI_USE_TIM5 || defined(__DOXYGEN__)
+QEIDriver QEID5;
+#endif
+
+/**
+ * @brief QEID8 driver identifier.
+ * @note The driver QEID8 allocates the timer TIM8 when enabled.
+ */
+#if STM32_QEI_USE_TIM8 || defined(__DOXYGEN__)
+QEIDriver QEID8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level QEI driver initialization.
+ *
+ * @notapi
+ */
+void qei_lld_init(void) {
+
+#if STM32_QEI_USE_TIM1
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID1);
+ QEID1.tim = STM32_TIM1;
+#endif
+
+#if STM32_QEI_USE_TIM2
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID2);
+ QEID2.tim = STM32_TIM2;
+#endif
+
+#if STM32_QEI_USE_TIM3
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID3);
+ QEID3.tim = STM32_TIM3;
+#endif
+
+#if STM32_QEI_USE_TIM4
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID4);
+ QEID4.tim = STM32_TIM4;
+#endif
+
+#if STM32_QEI_USE_TIM5
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID5);
+ QEID5.tim = STM32_TIM5;
+#endif
+
+#if STM32_QEI_USE_TIM8
+ /* Driver initialization.*/
+ qeiObjectInit(&QEID8);
+ QEID8.tim = STM32_TIM8;
+#endif
+}
+
+/**
+ * @brief Configures and activates the QEI peripheral.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ *
+ * @notapi
+ */
+void qei_lld_start(QEIDriver *qeip) {
+
+ if (qeip->state == QEI_STOP) {
+ /* Clock activation and timer reset.*/
+#if STM32_QEI_USE_TIM1
+ if (&QEID1 == qeip) {
+ rccEnableTIM1(FALSE);
+ rccResetTIM1();
+ }
+#endif
+#if STM32_QEI_USE_TIM2
+ if (&QEID2 == qeip) {
+ rccEnableTIM2(FALSE);
+ rccResetTIM2();
+ }
+#endif
+#if STM32_QEI_USE_TIM3
+ if (&QEID3 == qeip) {
+ rccEnableTIM3(FALSE);
+ rccResetTIM3();
+ }
+#endif
+#if STM32_QEI_USE_TIM4
+ if (&QEID4 == qeip) {
+ rccEnableTIM4(FALSE);
+ rccResetTIM4();
+ }
+#endif
+
+#if STM32_QEI_USE_TIM5
+ if (&QEID5 == qeip) {
+ rccEnableTIM5(FALSE);
+ rccResetTIM5();
+ }
+#endif
+#if STM32_QEI_USE_TIM8
+ if (&QEID8 == qeip) {
+ rccEnableTIM8(FALSE);
+ rccResetTIM8();
+ }
+#endif
+ }
+ /* Timer configuration.*/
+ qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR2 = 0;
+ qeip->tim->PSC = 0;
+ qeip->tim->DIER = 0;
+ qeip->tim->ARR = 0xFFFF;
+
+ /* Set Capture Compare 1 and Capture Compare 2 as input. */
+ qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+ if (qeip->config->mode == QEI_MODE_QUADRATURE) {
+ if (qeip->config->resolution == QEI_BOTH_EDGES)
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ else
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ } else {
+ /* Direction/Clock mode.
+ * Direction input on TI1, Clock input on TI2. */
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ }
+
+ if (qeip->config->dirinv == QEI_DIRINV_TRUE)
+ qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC2E;
+ else
+ qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E;
+}
+
+/**
+ * @brief Deactivates the QEI peripheral.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ *
+ * @notapi
+ */
+void qei_lld_stop(QEIDriver *qeip) {
+
+ if (qeip->state == QEI_READY) {
+ qeip->tim->CR1 = 0; /* Timer disabled. */
+
+ /* Clock deactivation.*/
+#if STM32_QEI_USE_TIM1
+ if (&QEID1 == qeip) {
+ rccDisableTIM1(FALSE);
+ }
+#endif
+#if STM32_QEI_USE_TIM2
+ if (&QEID2 == qeip) {
+ rccDisableTIM2(FALSE);
+ }
+#endif
+#if STM32_QEI_USE_TIM3
+ if (&QEID3 == qeip) {
+ rccDisableTIM3(FALSE);
+ }
+#endif
+#if STM32_QEI_USE_TIM4
+ if (&QEID4 == qeip) {
+ rccDisableTIM4(FALSE);
+ }
+#endif
+#if STM32_QEI_USE_TIM5
+ if (&QEID5 == qeip) {
+ rccDisableTIM5(FALSE);
+ }
+#endif
+ }
+#if STM32_QEI_USE_TIM8
+ if (&QEID8 == qeip) {
+ rccDisableTIM8(FALSE);
+ }
+#endif
+}
+
+/**
+ * @brief Enables the input capture.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ *
+ * @notapi
+ */
+void qei_lld_enable(QEIDriver *qeip) {
+
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+}
+
+/**
+ * @brief Disables the input capture.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ *
+ * @notapi
+ */
+void qei_lld_disable(QEIDriver *qeip) {
+
+ qeip->tim->CR1 = 0; /* Timer disabled. */
+}
+
+#endif /* HAL_USE_QEI */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h new file mode 100644 index 0000000..d0cb683 --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h @@ -0,0 +1,347 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIMv1/hal_qei_lld.h
+ * @brief STM32 QEI subsystem low level driver header.
+ *
+ * @addtogroup QEI
+ * @{
+ */
+
+#ifndef HAL_QEI_LLD_H
+#define HAL_QEI_LLD_H
+
+#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
+
+#include "stm32_tim.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief QEID1 driver enable switch.
+ * @details If set to @p TRUE the support for QEID1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM1 FALSE
+#endif
+
+/**
+ * @brief QEID2 driver enable switch.
+ * @details If set to @p TRUE the support for QEID2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM2 FALSE
+#endif
+
+/**
+ * @brief QEID3 driver enable switch.
+ * @details If set to @p TRUE the support for QEID3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM3 FALSE
+#endif
+
+/**
+ * @brief QEID4 driver enable switch.
+ * @details If set to @p TRUE the support for QEID4 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM4 FALSE
+#endif
+
+/**
+ * @brief QEID5 driver enable switch.
+ * @details If set to @p TRUE the support for QEID5 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM5 FALSE
+#endif
+
+/**
+ * @brief QEID8 driver enable switch.
+ * @details If set to @p TRUE the support for QEID8 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__)
+#define STM32_QEI_USE_TIM8 FALSE
+#endif
+
+/**
+ * @brief QEID1 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM1_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief QEID2 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM2_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief QEID3 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM3_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief QEID4 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM4_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief QEID5 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM5_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief QEID8 interrupt priority level setting.
+ */
+#if !defined(STM32_QEI_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QEI_TIM8_IRQ_PRIORITY 7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1
+#error "TIM1 not present in the selected device"
+#endif
+
+#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2
+#error "TIM2 not present in the selected device"
+#endif
+
+#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3
+#error "TIM3 not present in the selected device"
+#endif
+
+#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4
+#error "TIM4 not present in the selected device"
+#endif
+
+#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
+#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8
+#error "TIM8 not present in the selected device"
+#endif
+
+#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \
+ !STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \
+ !STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8
+#error "QEI driver activated but no TIM peripheral assigned"
+#endif
+
+#if STM32_QEI_USE_TIM1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM1"
+#endif
+
+#if STM32_QEI_USE_TIM2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM2"
+#endif
+
+#if STM32_QEI_USE_TIM3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM3"
+#endif
+
+#if STM32_QEI_USE_TIM4 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM4"
+#endif
+
+#if STM32_QEI_USE_TIM5 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM5"
+#endif
+
+#if STM32_QEI_USE_TIM8 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM8"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief QEI count mode.
+ */
+typedef enum {
+ QEI_MODE_QUADRATURE = 0, /**< Quadrature encoder mode. */
+ QEI_MODE_DIRCLOCK = 1, /**< Direction/Clock mode. */
+} qeimode_t;
+
+/**
+ * @brief QEI resolution.
+ */
+typedef enum {
+ QEI_SINGLE_EDGE = 0, /**< Count only on edges from first channel. */
+ QEI_BOTH_EDGES = 1, /**< Count on both edges (resolution doubles).*/
+} qeiresolution_t;
+
+/**
+ * @brief QEI direction inversion.
+ */
+typedef enum {
+ QEI_DIRINV_FALSE = 0, /**< Do not invert counter direction. */
+ QEI_DIRINV_TRUE = 1, /**< Invert counter direction. */
+} qeidirinv_t;
+
+/**
+ * @brief QEI counter type.
+ */
+typedef uint16_t qeicnt_t;
+
+/**
+ * @brief QEI delta type.
+ */
+typedef int32_t qeidelta_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Count mode.
+ */
+ qeimode_t mode;
+ /**
+ * @brief Resolution.
+ */
+ qeiresolution_t resolution;
+ /**
+ * @brief Direction inversion.
+ */
+ qeidirinv_t dirinv;
+ /* End of the mandatory fields.*/
+} QEIConfig;
+
+/**
+ * @brief Structure representing an QEI driver.
+ */
+struct QEIDriver {
+ /**
+ * @brief Driver state.
+ */
+ qeistate_t state;
+ /**
+ * @brief Last count value.
+ */
+ qeicnt_t last;
+ /**
+ * @brief Current configuration data.
+ */
+ const QEIConfig *config;
+#if defined(QEI_DRIVER_EXT_FIELDS)
+ QEI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the TIMx registers block.
+ */
+ stm32_tim_t *tim;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the counter value.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ * @return The current counter value.
+ *
+ * @notapi
+ */
+#define qei_lld_get_count(qeip) ((qeip)->tim->CNT)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__)
+extern QEIDriver QEID1;
+#endif
+
+#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__)
+extern QEIDriver QEID2;
+#endif
+
+#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__)
+extern QEIDriver QEID3;
+#endif
+
+#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__)
+extern QEIDriver QEID4;
+#endif
+
+#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__)
+extern QEIDriver QEID5;
+#endif
+
+#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__)
+extern QEIDriver QEID8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void qei_lld_init(void);
+ void qei_lld_start(QEIDriver *qeip);
+ void qei_lld_stop(QEIDriver *qeip);
+ void qei_lld_enable(QEIDriver *qeip);
+ void qei_lld_disable(QEIDriver *qeip);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_QEI */
+
+#endif /* HAL_QEI_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index c796984..377acdf 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -2,6 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk index d2aeae0..a8f21bc 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform.mk @@ -6,6 +6,7 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index baa7578..92f033c 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -2,7 +2,8 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index bc18dc6..c312e72 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -8,6 +8,7 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
|