diff options
Diffstat (limited to 'os/hal/ports')
63 files changed, 2755 insertions, 2561 deletions
diff --git a/os/hal/ports/MSP430X/hal_adc_lld.c b/os/hal/ports/MSP430X/hal_adc_lld.c new file mode 100644 index 0000000..42d3cbe --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.c @@ -0,0 +1,354 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.c
+ * @brief MSP430X ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC1 driver identifier.
+ */
+#if (MSP430X_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void restart_dma(ADCDriver * adcp) {
+ /* TODO timeouts? */
+ /* Restart DMA transfer */
+ if (adcp->dma.registers == NULL) {
+ /* Acquire a DMA stream because dmaTransfer can be called from ISRs */
+ osalSysLockFromISR();
+ dmaAcquireI(&(adcp->dma), adcp->dma.index);
+ osalSysUnlockFromISR();
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+}
+
+static void dma_callback(void * args) {
+ ADCDriver * adcp = (ADCDriver *)args;
+
+ if (adcp->grpp == NULL)
+ return;
+
+ adcp->count++;
+
+ if (adcp->count == adcp->depth / 2) {
+ /* half-full interrupt */
+ _adc_isr_half_code(adcp);
+ }
+
+ if (adcp->count == adcp->depth) {
+ /* full interrupt */
+
+ /* adc_lld_stop_conversion is called automatically here if needed */
+ _adc_isr_full_code(adcp);
+ /* after isr_full, adcp->grpp is only non-NULL if it's a circular group */
+ if (adcp->grpp) {
+ /* Reset the buffer pointer */
+ adcp->req.dest_addr = adcp->samples;
+
+ restart_dma(adcp);
+
+ /* Reset the count */
+ adcp->count = 0;
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+ }
+ else {
+ /* Advance the buffer pointer */
+ adcp->req.dest_addr = adcp->samples + (adcp->req.size * adcp->count);
+
+ restart_dma(adcp);
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+}
+
+static void populate_tlv(ADCDriver * adcp) {
+ uint8_t * tlv_addr = (uint8_t *)TLV_START;
+
+ while (*tlv_addr != TLV_TAGEND && tlv_addr < (uint8_t *)TLV_END) {
+ if (*tlv_addr == TLV_ADC12CAL) {
+ adcp->adc_cal = (msp430x_adc_cal_t *)(tlv_addr + 2);
+ }
+ else if (*tlv_addr == TLV_REFCAL) {
+ adcp->ref_cal = (msp430x_ref_cal_t *)(tlv_addr + 2);
+ }
+ tlv_addr += (tlv_addr[1] + 2);
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+PORT_IRQ_HANDLER(ADC12_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ switch (__even_in_range(ADC12IV, ADC12IV_ADC12TOVIFG)) {
+
+ case ADC12IV_ADC12OVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+ break;
+ }
+ case ADC12IV_ADC12TOVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
+ break;
+ }
+ default:
+ osalDbgAssert(false, "unhandled ADC exception");
+ _adc_isr_error_code(&ADCD1, ADC_ERR_UNKNOWN);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if MSP430X_ADC_USE_ADC1 == TRUE
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.regs = (msp430x_adc_reg_t *)(&ADC12CTL0);
+ populate_tlv(&ADCD1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_STOP) {
+ /* Enables the peripheral.*/
+ adcp->regs->ctl[0] = ADC12ON | ADC12MSC;
+ adcp->regs->ctl[1] =
+ MSP430X_ADC1_PDIV | MSP430X_ADC1_DIV | MSP430X_ADC1_SSEL | ADC12SHP;
+ adcp->regs->ctl[3] = ADC12ICH3MAP | ADC12ICH2MAP | ADC12ICH1MAP |
+ ADC12ICH0MAP | ADC12TCMAP | ADC12BATMAP;
+ adcp->regs->ier[2] = ADC12TOVIE | ADC12OVIE;
+ adcp->req.trigger = DMA_TRIGGER_MNEM(ADC12IFG);
+#if MSP430X_ADC_COMPACT_SAMPLES == TRUE
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTBYTE;
+#else
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTWORD;
+#endif
+ adcp->req.addr_mode = MSP430X_DMA_SRCINCR | MSP430X_DMA_DSTINCR;
+ adcp->req.transfer_mode = MSP430X_DMA_SINGLE;
+ adcp->req.callback.callback = dma_callback;
+ adcp->req.callback.args = adcp;
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ bool b;
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ b = dmaAcquireI(&adcp->dma, adcp->config->dma_index);
+ osalDbgAssert(!b, "stream already allocated");
+ }
+ else {
+#endif
+ adcp->dma.registers = NULL;
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+ }
+ /* Configures the peripheral.*/
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_READY) {
+/* Resets the peripheral.*/
+
+/* Disables the peripheral.*/
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(adcp->dma));
+ }
+#endif
+ adcp->regs->ctl[0] = 0;
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver * adcp) {
+
+ /* always use sequential transfer mode - this is fine */
+ adcp->regs->ctl[1] |= ADC12CONSEQ0;
+
+ /* set resolution */
+ adcp->regs->ctl[2] |= adcp->grpp->res;
+ /* start from MEM0 */
+ adcp->regs->ctl[3] &= ~(ADC12CSTARTADD_31);
+
+ /* Configure voltage reference */
+ while (REFCTL0 & REFGENBUSY)
+ ;
+ REFCTL0 = adcp->grpp->vref_src;
+
+ for (int i = 0; i < adcp->grpp->num_channels; i++) {
+ osalDbgAssert(adcp->grpp->channels[i] < 32, "invalid channel number");
+ adcp->regs->mctl[i] = adcp->grpp->ref | adcp->grpp->channels[i];
+ }
+
+ adcp->regs->mctl[adcp->grpp->num_channels - 1] |= ADC12EOS;
+
+ adcp->req.source_addr = adcp->regs->mem;
+ adcp->req.dest_addr = adcp->samples;
+ adcp->req.size = adcp->grpp->num_channels;
+ adcp->count = 0;
+
+/* TODO timeouts? */
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+#else
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+#endif
+
+ adcp->regs->ctl[0] |= adcp->grpp->rate | ADC12MSC | ADC12ENC | ADC12SC;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver * adcp) {
+
+ /* TODO stop DMA transfers here */
+ adcp->regs->ctl[0] &= ~(ADC12ENC | ADC12SC);
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+#endif
+ if (adcp->dma.registers != NULL) {
+ dmaRelease(&(adcp->dma));
+ adcp->dma.registers = NULL;
+ }
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+}
+
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint32_t tmp;
+ uint16_t fact;
+ if (grpp->ref == MSP430X_ADC_VSS_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VEREF_P_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VCC ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VEREF_P ||
+ grpp->ref == MSP430X_ADC_VEREF_N_VREF_BUF) {
+ /* Retrieve proper reference correction factor from TLV */
+ fact = (&(ADCD1.ref_cal->CAL_ADC_12VREF_FACTOR))[grpp->vref_src >> 4];
+ /* Calculate corrected value */
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+ }
+
+ /* Gain correction */
+ fact = ADCD1.adc_cal->CAL_ADC_GAIN_FACTOR;
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+
+ /* Offset correction */
+ sample += ADCD1.adc_cal->CAL_ADC_OFFSET;
+
+ return sample;
+}
+
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint16_t t30;
+ uint16_t t85;
+
+ /* Retrieve proper T = 30 correction value from TLV */
+ t30 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[grpp->vref_src >> 3];
+ /* Retrieve proper T = 85 correction value from TLV */
+ t85 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[(grpp->vref_src >> 3) + 1];
+
+ return ((((int32_t)sample - (int32_t)t30) * (85 - 30)) / (t85 - t30)) + 30;
+}
+
+#endif /* HAL_USE_ADC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_adc_lld.h b/os/hal/ports/MSP430X/hal_adc_lld.h new file mode 100644 index 0000000..1cca36b --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.h
+ * @brief MSP430X ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_SHT_4 = 0x0000,
+ MSP430X_ADC_SHT_8 = 0x1100,
+ MSP430X_ADC_SHT_16 = 0x2200,
+ MSP430X_ADC_SHT_32 = 0x3300,
+ MSP430X_ADC_SHT_64 = 0x4400,
+ MSP430X_ADC_SHT_96 = 0x5500,
+ MSP430X_ADC_SHT_128 = 0x6600,
+ MSP430X_ADC_SHT_192 = 0x7700,
+ MSP430X_ADC_SHT_256 = 0x8800,
+ MSP430X_ADC_SHT_384 = 0x9900,
+ MSP430X_ADC_SHT_512 = 0xAA00
+} MSP430XADCSampleRates;
+/** @} */
+
+/**
+ * @name Resolution
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_RES_8BIT = 0x0000,
+ MSP430X_ADC_RES_10BIT = 0x0010,
+ MSP430X_ADC_RES_12BIT = 0x0020
+} MSP430XADCResolution;
+/** @} */
+
+/**
+ * @name References
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_VSS_VCC = 0x0000,
+ MSP430X_ADC_VSS_VREF_BUF = 0x0100,
+ MSP430X_ADC_VSS_VEREF_N = 0x0200,
+ MSP430X_ADC_VSS_VEREF_P_BUF = 0x0300,
+ MSP430X_ADC_VSS_VEREF_P = 0x0400,
+ MSP430X_ADC_VEREF_P_BUF_VCC = 0x0500,
+ MSP430X_ADC_VEREF_P_VCC = 0x0600,
+ MSP430X_ADC_VEREF_P_VREF_BUF = 0x0700,
+ MSP430X_ADC_VREF_BUF_VCC = 0x0900,
+ MSP430X_ADC_VREF_BUF_VEREF_P = 0x0B00,
+ MSP430X_ADC_VEREF_N_VCC = 0x0C00,
+ MSP430X_ADC_VEREF_N_VREF_BUF = 0x0D00,
+ MSP430X_ADC_VEREF_N_VEREF_P = 0x0E00,
+ MSP430X_ADC_VEREF_N_VEREF_P_BUF = 0x0F00
+} MSP430XADCReferences;
+
+typedef enum {
+ MSP430X_REF_1V2 = 0x0000,
+ MSP430X_REF_2V0 = 0x0010,
+ MSP430X_REF_2V5 = 0x0020,
+ MSP430X_REF_1V2_EXT = 0x0002,
+ MSP430X_REF_2V0_EXT = 0x0012,
+ MSP430X_REF_2V5_EXT = 0x0022
+} MSP430XREFSources;
+
+#define MSP430X_REF_NONE MSP430X_REF_1V2
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name MSP430X configuration options
+ * @{
+ */
+/**
+ * @brief Stores ADC samples in an 8 bit integer.
+ * @note 10 and 12 bit sampling modes must not be used when this option is
+ * enabled.
+ */
+#if !defined(MSP430X_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define MSP430X_ADC_COMPACT_SAMPLES FALSE
+#endif
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(MSP430X_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define MSP430X_ADC_USE_ADC1 TRUE
+#endif
+
+/**]
+ * @brief Exclusive DMA enable switch.
+ * @details If set to @p TRUE the support for exclusive DMA is included.
+ * @note This increases the size of the compiled executable somewhat.
+ * @note The default is @p FALSE.
+ */
+#if !defined(MSP430X_ADC_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE
+#endif
+
+#if MSP430X_ADC_USE_ADC1
+
+/**
+ * @brief ADC1 clock source configuration
+ */
+#if !defined(MSP430X_ADC1_CLK_SRC)
+#define MSP430X_ADC1_CLK_SRC MSP430X_MODCLK
+#endif
+
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if MSP430X_ADC_USE_ADC1
+
+#if !defined(__MSP430_HAS_ADC12_B__)
+#error "No ADC present or ADC version not supported"
+#endif
+
+#if (MSP430X_ADC1_CLK_SRC == MSP430X_MODCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_MODCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_0
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_ACLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_ACLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_1
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_MCLK)
+#define MSP$30X_ADC1_CLK_FREQ MSP430X_MCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_2
+#elif (MSP430X_ADC1_CLK_SRC == MSP430SMCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_SMCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_3
+#else
+#error "Invalid ADC1 clock source requested!"
+#endif
+
+#if !defined(MSP430X_ADC1_FREQ)
+#warning "ADC clock frequency not defined - assuming 1 for all dividers"
+#define MSP430X_ADC1_DIV_CALC(x) (x == 1)
+#else
+#define MSP430X_ADC1_DIV_CALC(x) \
+ ((MSP430X_ADC1_CLK_FREQ / x) == MSP430X_ADC1_FREQ)
+#endif
+
+/**
+ * @brief ADC1 prescaler calculations
+ */
+#if MSP430X_ADC1_DIV_CALC(1)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(2)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(3)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(4)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(5)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(6)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(7)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(8)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(12)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(16)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(20)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(24)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(28)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(32)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(64)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(96)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(128)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(160)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(192)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(224)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(256)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(320)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(384)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(448)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(512)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_7
+#else
+#error "MSP430X_ADC1_FREQ not achievable with MSP430X_ADC1_CLK_SRC"
+#endif
+
+#endif /* MSP430X_ADC_USE_ADC1 */
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+#if !MSP430X_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
+typedef uint16_t adcsample_t;
+#else
+typedef uint8_t adcsample_t;
+#endif
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint8_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_UNKNOWN = 0, /**< Unknown error has occurred */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver * adcp, adcsample_t * buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver * adcp, adcerror_t err);
+
+/**
+ * @brief MSP430X ADC register structure.
+ */
+typedef struct {
+ uint16_t ctl[4];
+ uint16_t lo;
+ uint16_t hi;
+ uint16_t ifgr[3];
+ uint16_t ier[3];
+ uint16_t iv;
+ uint16_t padding[3];
+ uint16_t mctl[32];
+ uint16_t mem[32];
+} msp430x_adc_reg_t;
+
+/**
+ * @brief MSP430X ADC calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_GAIN_FACTOR;
+ uint16_t CAL_ADC_OFFSET;
+ uint16_t CAL_ADC_12T30;
+ uint16_t CAL_ADC_12T85;
+ uint16_t CAL_ADC_20T30;
+ uint16_t CAL_ADC_20T85;
+ uint16_t CAL_ADC_25T30;
+ uint16_t CAL_ADC_25T85;
+} msp430x_adc_cal_t;
+
+/**
+ * @brief MSP430X REF calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_12VREF_FACTOR;
+ uint16_t CAL_ADC_20VREF_FACTOR;
+ uint16_t CAL_ADC_25VREF_FACTOR;
+} msp430x_ref_cal_t;
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * MSP430X ADC cell registers interface, please refer to the MSP430X
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Sequence of analog channels belonging to the conversion group.
+ * @note Only the first num_channels are valid.
+ */
+ uint8_t channels[32];
+ /**
+ * @brief Sample resolution
+ */
+ MSP430XADCResolution res;
+ /**
+ * @brief Sampling time in clock cycles
+ */
+ MSP430XADCSampleRates rate;
+ /**
+ * @brief Voltage references to use
+ */
+ MSP430XADCReferences ref;
+ /**
+ * @brief VREF source
+ */
+ MSP430XREFSources vref_src;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
+ /**
+ * @brief The index of the DMA channel.
+ * @note This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA
+ * is not used.
+ */
+ uint8_t dma_index;
+#endif
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig * config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t * samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup * grpp;
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Base address of ADC12_B registers
+ */
+ msp430x_adc_reg_t * regs;
+ /**
+ * @brief DMA request structure
+ */
+ msp430x_dma_req_t req;
+ /**
+ * @brief ADC calibration structure from TLV
+ */
+ msp430x_adc_cal_t * adc_cal;
+ /**
+ * @brief REF calibration structure from TLV
+ */
+ msp430x_ref_cal_t * ref_cal;
+ /**
+ * @brief Count of times DMA callback has been called
+ */
+ uint8_t count;
+ /**
+ * @brief DMA stream
+ */
+ msp430x_dma_ch_t dma;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (MSP430X_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void adc_lld_init(void);
+void adc_lld_start(ADCDriver * adcp);
+void adc_lld_stop(ADCDriver * adcp);
+void adc_lld_start_conversion(ADCDriver * adcp);
+void adc_lld_stop_conversion(ADCDriver * adcp);
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample);
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp, adcsample_t sample);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC == TRUE */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.c b/os/hal/ports/MSP430X/hal_dma_lld.c index 43e1d6c..82bf39f 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.c +++ b/os/hal/ports/MSP430X/hal_dma_lld.c @@ -44,9 +44,8 @@ static msp430x_dma_ch_reg_t * const dma_channels = (msp430x_dma_ch_reg_t *)&DMA0CTL;
static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];
-#if CH_CFG_USE_SEMAPHORES
-static semaphore_t dma_lock;
-#endif
+static threads_queue_t dma_queue;
+static unsigned int queue_length;
/*===========================================================================*/
/* Driver local functions. */
@@ -88,9 +87,9 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { index = (DMAIV >> 1) - 1;
if (index < MSP430X_DMA_CHANNELS) {
-#if CH_CFG_USE_SEMAPHORES
- chSemSignalI(&dma_lock);
-#endif
+ osalSysLockFromISR();
+ osalThreadDequeueNextI(&dma_queue, MSG_OK);
+ osalSysUnlockFromISR();
msp430x_dma_cb_t * cb = &callbacks[index];
@@ -113,9 +112,7 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { * @init
*/
void dmaInit(void) {
-#if CH_CFG_USE_SEMAPHORES
- chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);
-#endif
+ osalThreadQueueObjectInit(&dma_queue);
}
/**
@@ -125,134 +122,124 @@ void dmaInit(void) { * semaphores are enabled, the calling thread will sleep until a
* channel is available or the request times out. If semaphores are
* disabled, the calling thread will busy-wait instead of sleeping.
+ *
+ * @sclass
*/
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {
-/* Check if a DMA channel is available */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);
- if (semresult != MSG_OK)
- return true;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- systime_t start = chVTGetSystemTimeX();
-
- do {
-#endif
- /* Grab the correct DMA channel to use */
- int i = 0;
- for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
- if (!(dma_channels[i].ctl & DMAEN)) {
- break;
- }
- }
-#if !(CH_CFG_USE_SEMAPHORES)
- while (chVTTimeElapsedSinceX(start) < timeout)
- ;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- if (i == MSP430X_DMA_CHANNELS) {
- return true;
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout) {
+
+ osalDbgCheckClassS();
+
+ /* Check if a DMA channel is available */
+ if (queue_length >= MSP430X_DMA_CHANNELS) {
+ msg_t queueresult = osalThreadEnqueueTimeoutS(&dma_queue, timeout);
+ if (queueresult != MSG_OK)
+ return -1;
+ }
+
+ /* Grab the correct DMA channel to use */
+ int i = 0;
+ for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
+ if (!(dma_channels[i].ctl & DMAEN)) {
+ break;
}
-#endif
+ }
+
+ /* Make the request */
+ init_request(request, i);
+
+ return i;
+}
- /* Make the request */
- init_request(request, i);
+/**
+ * @brief Acquires exclusive control of a DMA channel.
+ * @pre The channel must not be already acquired or an error is returned.
+ * @note If the channel is in use by the DMA engine, blocks until acquired.
+ * @post This channel must be interacted with using only the functions
+ * defined in this module.
+ *
+ * @param[out] channel The channel handle. Must be pre-allocated.
+ * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
+ * @return The operation status.
+ * @retval false no error, channel acquired.
+ * @retval true error, channel already acquired.
+ *
+ * @iclass
+ */
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index) {
+
+ osalDbgCheckClassI();
- return false;
+ /* Is the channel already acquired? */
+ osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
+ if (dma_channels[index].ctl & DMADT_4) {
+ return true;
}
- /**
- * @brief Acquires exclusive control of a DMA channel.
- * @pre The channel must not be already acquired or an error is returned.
- * @note If the channel is in use by the DMA engine, blocks until acquired.
- * @post This channel must be interacted with using only the functions
- * defined in this module.
- *
- * @param[out] channel The channel handle. Must be pre-allocated.
- * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
- * @return The operation status.
- * @retval false no error, channel acquired.
- * @retval true error, channel already acquired.
- */
- bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {
- /* Acquire the channel in an idle mode */
-
- /* Is the channel already acquired? */
- osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
- if (dma_channels[index].ctl & DMADT_4) {
- return true;
- }
+ /* Increment the DMA counter */
+ queue_length++;
-/* Increment the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWait(&dma_lock);
- if (semresult != MSG_OK)
- return true;
-#endif
+ while (dma_channels[index].ctl & DMAEN)
+ ;
- while (dma_channels[index].ctl & DMAEN)
- ;
+ /* Acquire the channel in an idle mode */
+ dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
+ dma_channels[index].sz = 0;
+ dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
- dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
- dma_channels[index].sz = 0;
- dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
+ channel->registers = dma_channels + index;
+ channel->index = index;
+ channel->cb = callbacks + index;
+
+ return false;
+}
- channel->registers = dma_channels + index;
- channel->index = index;
- channel->cb = callbacks + index;
+/**
+ * @brief Initiates a DMA transfer operation using an acquired channel.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ *
+ * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
+ * @param[in] request pointer to a DMA request object.
+ */
+void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
- return false;
- }
+ dma_trigger_set(channel->index, request->trigger);
+ /**(channel->ctl) = request->trigger;*/
- /**
- * @brief Initiates a DMA transfer operation using an acquired channel.
- * @pre The channel must have been acquired using @p dmaAcquire().
- *
- * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
- * @param[in] request pointer to a DMA request object.
- */
- void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
-
- dma_trigger_set(channel->index, request->trigger);
- /**(channel->ctl) = request->trigger;*/
-
- channel->cb->callback = request->callback.callback;
- channel->cb->args = request->callback.args;
-
- chSysLock();
- channel->registers->ctl &= (~DMAEN);
- channel->registers->sa = (uintptr_t)request->source_addr;
- channel->registers->da = (uintptr_t)request->dest_addr;
- channel->registers->sz = request->size;
- channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
- request->transfer_mode | DMADT_4 | DMAEN |
- DMAREQ; /* repeated transfers */
- chSysUnlock();
- }
+ channel->cb->callback = request->callback.callback;
+ channel->cb->args = request->callback.args;
- /**
- * @brief Releases exclusive control of a DMA channel.
- * @details The channel is released from control and returned to the DMA
- * engine
- * pool. Trying to release an unallocated channel is an illegal
- * operation and is trapped if assertions are enabled.
- * @pre The channel must have been acquired using @p dmaAcquire().
- * @post The channel is returned to the DMA engine pool.
- */
- void dmaRelease(msp430x_dma_ch_t * channel) {
-
- osalDbgCheck(channel != NULL);
-
- /* Release the channel in an idle mode */
- channel->registers->ctl = DMAABORT;
-
-/* release the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- chSemSignal(&dma_lock);
-#endif
- }
+ channel->registers->ctl &= (~DMAEN);
+ channel->registers->sa = (uintptr_t)request->source_addr;
+ channel->registers->da = (uintptr_t)request->dest_addr;
+ channel->registers->sz = request->size;
+ channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
+ request->transfer_mode | DMADT_4 | DMAEN |
+ DMAREQ; /* repeated transfers */
+}
+
+/**
+ * @brief Releases exclusive control of a DMA channel.
+ * @details The channel is released from control and returned to the DMA
+ * engine
+ * pool. Trying to release an unallocated channel is an illegal
+ * operation and is trapped if assertions are enabled.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ * @post The channel is returned to the DMA engine pool.
+ */
+void dmaRelease(msp430x_dma_ch_t * channel) {
+ syssts_t sts;
+
+ sts = osalSysGetStatusAndLockX();
+ osalDbgCheck(channel != NULL);
+
+ /* Release the channel in an idle mode */
+ channel->registers->ctl = DMAABORT;
+
+ /* release the DMA counter */
+ osalThreadDequeueAllI(&dma_queue, MSG_RESET);
+ queue_length = 0;
+ osalSysRestoreStatusX(sts);
+}
#endif /* HAL_USE_DMA == TRUE */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.h b/os/hal/ports/MSP430X/hal_dma_lld.h index d1495d2..f558e78 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.h +++ b/os/hal/ports/MSP430X/hal_dma_lld.h @@ -159,8 +159,8 @@ typedef struct { extern "C" {
#endif
void dmaInit(void);
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);
-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout);
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index);
void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);
void dmaRelease(msp430x_dma_ch_t * channel);
diff --git a/os/hal/ports/MSP430X/hal_lld.c b/os/hal/ports/MSP430X/hal_lld.c index 872fe97..812a0cf 100644 --- a/os/hal/ports/MSP430X/hal_lld.c +++ b/os/hal/ports/MSP430X/hal_lld.c @@ -82,6 +82,10 @@ void hal_lld_init(void) { } while (SFRIFG1 & OFIFG);
#endif
CSCTL0_H = 0xFF; /* Lock clock system */
+
+#if (HAL_USE_DMA == TRUE)
+ dmaInit();
+#endif
}
/** @} */
diff --git a/os/hal/ports/MSP430X/hal_lld.h b/os/hal/ports/MSP430X/hal_lld.h index 9549453..62f07e9 100644 --- a/os/hal/ports/MSP430X/hal_lld.h +++ b/os/hal/ports/MSP430X/hal_lld.h @@ -25,6 +25,8 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
+#include "hal_dma_lld.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
diff --git a/os/hal/ports/MSP430X/hal_serial_lld.c b/os/hal/ports/MSP430X/hal_serial_lld.c index 0d9aa1c..feb00ac 100644 --- a/os/hal/ports/MSP430X/hal_serial_lld.c +++ b/os/hal/ports/MSP430X/hal_serial_lld.c @@ -374,11 +374,11 @@ PORT_IRQ_HANDLER(USCI_A0_VECTOR) { if (oqIsEmptyI(&SD0.oqueue))
chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);
UCA0IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -432,11 +432,11 @@ PORT_IRQ_HANDLER(USCI_A1_VECTOR) { if (oqIsEmptyI(&SD1.oqueue))
chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);
UCA1IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -490,11 +490,11 @@ PORT_IRQ_HANDLER(USCI_A2_VECTOR) { if (oqIsEmptyI(&SD2.oqueue))
chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);
UCA2IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -548,11 +548,11 @@ PORT_IRQ_HANDLER(USCI_A3_VECTOR) { if (oqIsEmptyI(&SD3.oqueue))
chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);
UCA3IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.c b/os/hal/ports/MSP430X/hal_spi_lld.c index 70a357e..3a54b1e 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.c +++ b/os/hal/ports/MSP430X/hal_spi_lld.c @@ -104,21 +104,21 @@ static uint16_t dummyrx; static void init_transfer(SPIDriver * spip) {
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
+ if (spip->config->dmarx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmarx), &(spip->rx_req));
}
- if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ if (spip->config->dmatx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmatx), &(spip->tx_req));
}
#else
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
#endif
*(spip->ifg) |= UCTXIFG;
@@ -325,11 +325,11 @@ void spi_lld_start(SPIDriver * spip) { /* Claim DMA streams here */
bool b;
if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);
+ b = dmaAcquireI(&(spip->dmatx), spip->config->dmatx_index);
osalDbgAssert(!b, "stream already allocated");
}
if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);
+ b = dmaAcquireI(&(spip->dmarx), spip->config->dmarx_index);
osalDbgAssert(!b, "stream already allocated");
}
#endif /* MSP430X_SPI_EXCLUSIVE_DMA */
@@ -388,10 +388,11 @@ void spi_lld_start(SPIDriver * spip) { spip->regs->ctlw0 = UCSWRST;
spip->regs->brw = brw;
spip->regs->ctlw0 =
- (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |
+ ((spip->config->spi_mode ^ 0x02) << 14) | (spip->config->bit_order << 13) |
(spip->config->data_size << 12) | (UCMST) |
((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);
*(spip->ifg) = 0;
+ spi_lld_unselect(spip);
}
/**
@@ -406,8 +407,12 @@ void spi_lld_stop(SPIDriver * spip) { if (spip->state == SPI_READY) {
/* Disables the peripheral.*/
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE
- dmaRelease(&(spip->dmatx));
- dmaRelease(&(spip->dmarx));
+ if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmatx));
+ }
+ if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmarx));
+ }
#endif
spip->regs->ctlw0 = UCSWRST;
}
@@ -561,15 +566,12 @@ void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) { * @param[in] frame the data frame to send over the SPI bus
* @return The received data frame from the SPI bus.
*/
-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {
-
- osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");
+uint8_t spi_lld_polled_exchange(SPIDriver * spip, uint8_t frame) {
- while (!(*(spip->ifg) & UCTXIFG))
- ;
spip->regs->txbuf = frame;
while (!(*(spip->ifg) & UCRXIFG))
;
+ *(spip->ifg) &= ~(UCRXIFG | UCTXIFG);
return spip->regs->rxbuf;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.h b/os/hal/ports/MSP430X/hal_spi_lld.h index ebf14c8..949a8a0 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.h +++ b/os/hal/ports/MSP430X/hal_spi_lld.h @@ -118,7 +118,7 @@ * @note This increases the size of the compiled executable somewhat.
* @note The default is @p FALSE.
*/
-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)
+#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
#endif
@@ -630,7 +630,7 @@ extern "C" { const void *txbuf, void *rxbuf);
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/MSP430X/platform.mk b/os/hal/ports/MSP430X/platform.mk index 832814b..627a2f0 100644 --- a/os/hal/ports/MSP430X/platform.mk +++ b/os/hal/ports/MSP430X/platform.mk @@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_adc_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index 601deca..a2cf026 100644..100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -15,7 +15,7 @@ */ /** - * @file STM32/CRCv1/crc_lld.c + * @file STM32/CRCv1/hal_crc_lld.c * @brief STM32 CRC subsystem low level driver source. * * @addtogroup CRC @@ -185,15 +185,15 @@ void crc_lld_start(CRCDriver *crcp) { crcp->crc->CR |= CRC_CR_REV_OUT; } #else - osalDbgAssert(crcp->config->initial_val != default_config.initial_val, + osalDbgAssert(crcp->config->initial_val == default_config.initial_val, "hardware doesn't support programmable initial value"); - osalDbgAssert(crcp->config->poly_size != default_config.poly_size, + osalDbgAssert(crcp->config->poly_size == default_config.poly_size, "hardware doesn't support programmable polynomial size"); - osalDbgAssert(crcp->config->poly != default_config.poly, + osalDbgAssert(crcp->config->poly == default_config.poly, "hardware doesn't support programmable polynomial"); - osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data, + osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data, "hardware doesn't support reflect of input data"); - osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder, + osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder, "hardware doesn't support reflect of output remainder"); #endif @@ -299,7 +299,7 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { n--; } #else - osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses"); + osalDbgAssert(n == 0, "STM32 CRC Unit only supports WORD accesses"); #endif #endif diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h index ecdaf81..213d346 100644 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h @@ -15,15 +15,15 @@ */ /** - * @file STM32/CRCv1/crc_lld.h + * @file STM32/CRCv1/hal_crc_lld.h * @brief STM32 CRC subsystem low level driver header. * * @addtogroup CRC * @{ */ -#ifndef _CRC_LLD_H_ -#define _CRC_LLD_H_ +#ifndef HAL_CRC_LLD_H_ +#define HAL_CRC_LLD_H_ #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) @@ -244,6 +244,6 @@ extern "C" { #endif /* HAL_USE_CRC */ -#endif /* _CRC_LLD_H_ */ +#endif /* HAL_CRC_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c index aba029f..6751202 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_dma2d.c + * @file hal_stm32_dma2d.c * @brief DMA2D/Chrom-ART driver. */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h index 01f0941..c06ab62 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_dma2d.h + * @file hal_stm32_dma2d.h * @brief DMA2D/Chrom-ART driver. * * @addtogroup dma2d * @{ */ -#ifndef _STM32_DMA2D_H_ -#define _STM32_DMA2D_H_ +#ifndef HAL_STM32_DMA2D_H_ +#define HAL_STM32_DMA2D_H_ /** * @brief Using the DMA2D driver. @@ -659,6 +659,6 @@ extern "C" { #endif /* STM32_DMA2D_USE_DMA2D */ -#endif /* _STM32_DMA2D_H_ */ +#endif /* HAL_STM32_DMA2D_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index 40ad05c..b4c2938 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc.c + * @file hal_fsmc.c * @brief FSMC Driver subsystem low level driver source template. * * @addtogroup FSMC @@ -125,7 +125,7 @@ void fsmc_start(FSMCDriver *fsmcp) { rccResetFSMC(); #endif rccEnableFSMC(FALSE); -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); #endif } @@ -153,7 +153,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { /* Disables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 if (&FSMCD1 == fsmcp) { -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif rccDisableFSMC(FALSE); @@ -164,7 +164,6 @@ void fsmc_stop(FSMCDriver *fsmcp) { } } -#if !STM32_NAND_USE_EXT_INT /** * @brief FSMC shared interrupt handler. * @@ -185,7 +184,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { #endif CH_IRQ_EPILOGUE(); } -#endif /* !STM32_NAND_USE_EXT_INT */ #endif /* HAL_USE_FSMC */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index f9d8a60..f4837f5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc.h + * @file hal_fsmc.h * @brief FSMC Driver subsystem low level driver header. * * @addtogroup FSMC * @{ */ -#ifndef _FSMC_H_ -#define _FSMC_H_ +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ #if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) @@ -230,6 +230,9 @@ typedef struct { defined(STM32F7)) #define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) #endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -247,15 +250,6 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif -/** - * @brief Internal FSMC interrupt enable switch - * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. - * You have to use EXTI module instead to workaround this issue. - */ -#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_EXT_INT FALSE -#endif - /** @} */ /*===========================================================================*/ @@ -344,6 +338,6 @@ extern "C" { #endif /* HAL_USE_FSMC */ -#endif /* _FSMC_H_ */ +#endif /* HAL_FSMC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c index 95f47d5..ac83477 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c @@ -18,7 +18,7 @@ */ /** - * @file fsmc_sdram.c + * @file hal_fsmc_sdram.c * @brief SDRAM Driver subsystem low level driver source. * * @addtogroup SDRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h index cef6772..b419168 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h @@ -18,15 +18,15 @@ */ /** - * @file fsmc_sdram.h + * @file hal_fsmc_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM * @{ */ -#ifndef _FMC_SDRAM_H_ -#define _FMC_SDRAM_H_ +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx)) @@ -166,6 +166,6 @@ extern "C" { #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ -#endif /* _FMC_SDRAM_H_ */ +#endif /* HAL_FMC_SDRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c index 6f710d4..333362f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc_sram.c + * @file hal_fsmc_sram.c * @brief SRAM Driver subsystem low level driver source. * * @addtogroup SRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h index 529bdc7..5e749a8 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc_sram.h + * @file hal_fsmc_sram.h * @brief SRAM Driver subsystem low level driver header. * * @addtogroup SRAM * @{ */ -#ifndef _FSMC_SRAM_H_ -#define _FSMC_SRAM_H_ +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ #include "hal_fsmc.h" @@ -167,6 +167,6 @@ extern "C" { #endif /* STM32_USE_FSMC_SRAM */ -#endif /* _FSMC_SRAM_H_ */ +#endif /* HAL_FSMC_SRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c index b37c026..f39ff35 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c @@ -15,7 +15,7 @@ */ /** - * @file nand_lld.c + * @file hal_nand_lld.c * @brief NAND Driver subsystem low level driver source. * * @addtogroup NAND @@ -117,13 +117,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_enable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_enable(); -#else + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); + FSMC_SR_ILEN | FSMC_SR_IFEN); nandp->nand->SR |= FSMC_SR_IREN; -#endif } /** @@ -134,11 +131,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_disable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_disable(); -#else + nandp->nand->SR &= ~FSMC_SR_IREN; -#endif } /** @@ -152,10 +146,8 @@ static void nand_isr_handler (NANDDriver *nandp) { osalSysLockFromISR(); -#if !STM32_NAND_USE_EXT_INT osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ nandp->nand->SR &= ~FSMC_SR_IRS; -#endif switch (nandp->state){ case NAND_READ: @@ -501,12 +493,13 @@ void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { */ uint8_t nand_lld_read_status(NANDDriver *nandp) { - uint8_t status[1] = {0x01}; /* presume worse */ + uint8_t status; + status = 1; /* presume worse */ nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - nand_lld_polled_read_data(nandp, status, 1); + nand_lld_polled_read_data(nandp, &status, 1); - return status[0]; + return status; } #endif /* HAL_USE_NAND */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index 8dca42f..de7a0c4 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -15,15 +15,15 @@ */ /** - * @file nand_lld.h + * @file hal_nand_lld.h * @brief NAND Driver subsystem low level driver header. * * @addtogroup NAND * @{ */ -#ifndef _NAND_LLD_H_ -#define _NAND_LLD_H_ +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ #include "hal_fsmc.h" #include "bitmap.h" @@ -120,10 +120,6 @@ #error "FSMC not present in the selected device" #endif -#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT -#error "External interrupt controller must be enabled to use this feature" -#endif - #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif @@ -133,11 +129,6 @@ /*===========================================================================*/ /** - * @brief NAND driver condition flags type. - */ -typedef uint32_t nandflags_t; - -/** * @brief Type of a structure representing an NAND driver. */ typedef struct NANDDriver NANDDriver; @@ -147,23 +138,12 @@ typedef struct NANDDriver NANDDriver; */ typedef void (*nandisrhandler_t)(NANDDriver *nandp); -#if STM32_NAND_USE_EXT_INT -/** - * @brief Type of function switching external interrupts on and off. - */ -typedef void (*nandisrswitch_t)(void); -#endif /* STM32_NAND_USE_EXT_INT */ - /** * @brief Driver configuration structure. * @note It could be empty on some architectures. */ typedef struct { /** - * @brief Pointer to lower level driver. - */ - //const FSMCDriver *fsmcp; - /** * @brief Number of erase blocks in NAND device. */ uint32_t blocks; @@ -197,16 +177,6 @@ typedef struct { * from STMicroelectronics. */ uint32_t pmem; -#if STM32_NAND_USE_EXT_INT - /** - * @brief Function enabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_enable; - /** - * @brief Function disabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_disable; -#endif /* STM32_NAND_USE_EXT_INT */ } NANDConfig; /** @@ -319,6 +289,6 @@ extern "C" { #endif /* HAL_USE_NAND */ -#endif /* _NAND_LLD_H_ */ +#endif /* HAL_NAND_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c index e5f9a09..f0fd289 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_ltdc.c + * @file hal_stm32_ltdc.c * @brief LCD-TFT Controller Driver. */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h index 16b38ca..5db89e2 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_ltdc.h + * @file hal_stm32_ltdc.h * @brief LCD-TFT Controller Driver. * * @addtogroup ltdc * @{ */ -#ifndef _STM32_LTDC_H_ -#define _STM32_LTDC_H_ +#ifndef HAL_STM32_LTDC_H_ +#define HAL_STM32_LTDC_H_ /** * @brief Using the LTDC driver. @@ -731,6 +731,6 @@ extern "C" { #endif /* STM32_LTDC_USE_LTDC */ -#endif /* _STM32_LTDC_H_ */ +#endif /* HAL_STM32_LTDC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h index 927eb6f..e72098e 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h @@ -22,8 +22,8 @@ 32-bit timers and timers with single capture/compare channels. */ -#ifndef __EICU_LLD_H -#define __EICU_LLD_H +#ifndef HAL_EICU_LLD_H +#define HAL_EICU_LLD_H #include "stm32_tim.h" @@ -551,4 +551,4 @@ extern "C" { #endif /* HAL_USE_EICU */ -#endif /* __EICU_LLD_H */ +#endif /* HAL_EICU_LLD_H */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index ffc4992..6138481 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -194,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) { #endif
}
/* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0;
qeip->tim->PSC = 0;
qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
+ qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else {
/* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
}
if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@@ -230,7 +230,7 @@ void qei_lld_start(QEIDriver *qeip) { void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
@@ -275,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) { */
void qei_lld_enable(QEIDriver *qeip) {
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
}
/**
@@ -287,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) { */
void qei_lld_disable(QEIDriver *qeip) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
}
#endif /* HAL_USE_QEI */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 8ab6176..c55fae2 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -24,7 +24,7 @@ /** - * @file STM32/timcap_lld.c + * @file STM32/hal_timcap_lld.c * @brief STM32 TIMCAP subsystem low level driver header. * * @addtogroup TIMCAP diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h index d39c438..643798a 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef _TIMCAP_LLD_H_ -#define _TIMCAP_LLD_H_ +#ifndef HAL_TIMCAP_LLD_H_ +#define HAL_TIMCAP_LLD_H_ #include "ch.h" #include "hal.h" diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h index ca2dc49..b88e620 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h @@ -15,7 +15,7 @@ */ /** - * @file stm32_otg.h + * @file hal_stm32_otg.h * @brief STM32 OTG registers layout header. * * @addtogroup USB @@ -23,8 +23,8 @@ */ -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ +#ifndef HAL_STM32_OTG_H_ +#define HAL_STM32_OTG_H_ /** * @brief Number of the implemented endpoints in OTG_FS. diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h index e8df749..5c0ac40 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h @@ -15,8 +15,8 @@ limitations under the License. */ -#ifndef USBH_LLD_H_ -#define USBH_LLD_H_ +#ifndef HAL_USBH_LLD_H_ +#define HAL_USBH_LLD_H_ #include "hal.h" @@ -150,4 +150,4 @@ uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh); #endif -#endif /* USBH_LLD_H_ */ +#endif /* HAL_USBH_LLD_H_ */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c index efe6421..d0788f4 100644 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c @@ -34,11 +34,11 @@ * @brief Generic interrupt serving code for multiple pins per interrupt * handler. */ -#define ext_lld_serve_port_interrupt(gpiop, start) \ +#define ext_lld_serve_port_interrupt(gpio, start) \ do { \ - uint32_t mis = gpiop->MIS; \ + uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ \ - gpiop->ICR = mis; \ + HWREG(gpio + GPIO_O_ICR) = mis; \ \ if (mis & (1 << 0)) { \ EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ @@ -89,7 +89,7 @@ EXTDriver EXTD1; /* Driver local variables and types. */ /*===========================================================================*/ -const ioportid_t gpio[] = +const ioportid_t gpio_table[] = { #if TIVA_HAS_GPIOA GPIOA, @@ -847,58 +847,58 @@ void ext_lld_stop(EXTDriver *extp) } #if TIVA_HAS_GPIOA - GPIOA->IM = 0; + HWREG(GPIOA + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOB - GPIOB->IM = 0; + HWREG(GPIOB + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOC - GPIOC->IM = 0; + HWREG(GPIOC + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOD - GPIOD->IM = 0; + HWREG(GPIOD + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOE - GPIOE->IM = 0; + HWREG(GPIOE + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOF - GPIOF->IM = 0; + HWREG(GPIOF + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOG - GPIOG->IM = 0; + HWREG(GPIOG + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOH - GPIOH->IM = 0; + HWREG(GPIOH + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOJ - GPIOJ->IM = 0; + HWREG(GPIOJ + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOK - GPIOK->IM = 0; + HWREG(GPIOK + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOL - GPIOL->IM = 0; + HWREG(GPIOL + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOM - GPIOM->IM = 0; + HWREG(GPIOM + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPION - GPION->IM = 0; + HWREG(GPION + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOP - GPIOP->IM = 0; + HWREG(GPIOP + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOQ - GPIOQ->IM = 0; + HWREG(GPIOQ + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOR - GPIOR->IM = 0; + HWREG(GPIOR + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOS - GPIOS->IM = 0; + HWREG(GPIOS + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOT - GPIOT->IM = 0; + HWREG(GPIOT + GPIO_O_IM) = 0; #endif } @@ -912,34 +912,34 @@ void ext_lld_stop(EXTDriver *extp) */ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - GPIO_TypeDef *gpiop; + uint32_t gpio; uint8_t pin; uint32_t im; pin = channel & 0x07; - gpiop = gpio[channel >> 3]; + gpio = gpio_table[channel >> 3]; /* Disable interrupts */ - im = gpiop->IM; - gpiop->IM = 0; + im = HWREG(gpio + GPIO_O_IM); + HWREG(gpio + GPIO_O_IM) = 0; /* Configure pin to be edge-sensitive.*/ - gpiop->IS &= ~(1 << pin); + HWREG(gpio + GPIO_O_IS) &= ~(1 << pin); /* Programming edge registers.*/ if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_BOTH_EDGES) { - gpiop->IBE |= (1 << pin); + HWREG(gpio + GPIO_O_IBE) |= (1 << pin); } else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_FALLING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV &= ~(1 << pin); + HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); + HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin); } else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_RISING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV |= (1 << pin); + HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); + HWREG(gpio + GPIO_O_IEV) |= (1 << pin); } /* Programming interrupt and event registers.*/ @@ -953,7 +953,7 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) } /* Restore interrupts */ - gpiop->IM = im; + HWREG(gpio + GPIO_O_IM) = im; } /** @@ -967,13 +967,13 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { (void)extp; - GPIO_TypeDef *gpiop; + uint32_t gpio; uint8_t pin; pin = channel & 0x07; - gpiop = gpio[channel >> 3]; + gpio = gpio_table[channel >> 3]; - gpiop->IM &= ~(1 << pin); + HWREG(gpio + GPIO_O_IM) &= ~(1 << pin); } #endif /* HAL_USE_EXT */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h index 08accb2..08accb2 100644 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c index 5460fd4..4df6665 100644 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -250,19 +250,19 @@ */ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) { - port->DATA = config->data; - port->DIR = config->dir; - port->AFSEL = config->afsel; - port->DR2R = config->dr2r; - port->DR4R = config->dr4r; - port->DR8R = config->dr8r; - port->ODR = config->odr; - port->PUR = config->pur; - port->PDR = config->pdr; - port->SLR = config->slr; - port->DEN = config->den; - port->AMSEL = config->amsel; - port->PCTL = config->pctl; + HWREG((port) + GPIO_O_DATA) = config->data; + HWREG((port) + GPIO_O_DIR) = config->dir; + HWREG((port) + GPIO_O_AFSEL) = config->afsel; + HWREG((port) + GPIO_O_DR2R) = config->dr2r; + HWREG((port) + GPIO_O_DR4R) = config->dr4r; + HWREG((port) + GPIO_O_DR8R) = config->dr8r; + HWREG((port) + GPIO_O_ODR) = config->odr; + HWREG((port) + GPIO_O_PUR) = config->pur; + HWREG((port) + GPIO_O_PDR) = config->pdr; + HWREG((port) + GPIO_O_SLR) = config->slr; + HWREG((port) + GPIO_O_DEN) = config->den; + HWREG((port) + GPIO_O_AMSEL) = config->amsel; + HWREG((port) + GPIO_O_PCTL) = config->pctl; } /** @@ -274,8 +274,9 @@ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) */ static void gpio_unlock(ioportid_t port, ioportmask_t mask) { - port->LOCK = TIVA_GPIO_LOCK_PWD; - port->CR = mask; + + HWREG((port) + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD; + HWREG((port) + GPIO_O_CR) = mask; } /*===========================================================================*/ @@ -299,13 +300,13 @@ void _pal_lld_init(const PALConfig *config) /* * Enables all GPIO clocks. */ - SYSCTL->RCGCGPIO = RCGCGPIO_MASK; + HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK; #if defined(TM4C123x) - SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; + HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK; #endif /* Wait until all GPIO modules are ready */ - while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK)) ; #if TIVA_HAS_GPIOA @@ -402,18 +403,18 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) uint32_t bit_mask = (1 << bit); if ((mask & 1) != 0) { - port->DIR = (port->DIR & ~bit_mask) | dir; - port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; - port->DR2R = (port->DR2R & ~bit_mask) | dr2r; - port->DR4R = (port->DR4R & ~bit_mask) | dr4r; - port->DR8R = (port->DR8R & ~bit_mask) | dr8r; - port->ODR = (port->ODR & ~bit_mask) | odr; - port->PUR = (port->PUR & ~bit_mask) | pur; - port->PDR = (port->PDR & ~bit_mask) | pdr; - port->SLR = (port->SLR & ~bit_mask) | slr; - port->DEN = (port->DEN & ~bit_mask) | den; - port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; - port->PCTL = (port->PCTL & ~pctl_mask) | pctl; + HWREG((port) + GPIO_O_DIR) = (HWREG((port) + GPIO_O_DIR) & ~bit_mask) | dir; + HWREG((port) + GPIO_O_AFSEL) = (HWREG((port) + GPIO_O_AFSEL) & ~bit_mask) | afsel; + HWREG((port) + GPIO_O_DR2R) = (HWREG((port) + GPIO_O_DR2R) & ~bit_mask) | dr2r; + HWREG((port) + GPIO_O_DR4R) = (HWREG((port) + GPIO_O_DR4R) & ~bit_mask) | dr4r; + HWREG((port) + GPIO_O_DR8R) = (HWREG((port) + GPIO_O_DR8R) & ~bit_mask) | dr8r; + HWREG((port) + GPIO_O_ODR) = (HWREG((port) + GPIO_O_ODR) & ~bit_mask) | odr; + HWREG((port) + GPIO_O_PUR) = (HWREG((port) + GPIO_O_PUR) & ~bit_mask) | pur; + HWREG((port) + GPIO_O_PDR) = (HWREG((port) + GPIO_O_PDR) & ~bit_mask) | pdr; + HWREG((port) + GPIO_O_SLR) = (HWREG((port) + GPIO_O_SLR) & ~bit_mask) | slr; + HWREG((port) + GPIO_O_DEN) = (HWREG((port) + GPIO_O_DEN) & ~bit_mask) | den; + HWREG((port) + GPIO_O_AMSEL) = (HWREG((port) + GPIO_O_AMSEL) & ~bit_mask) | amsel; + HWREG((port) + GPIO_O_PCTL) = (HWREG((port) + GPIO_O_PCTL) & ~pctl_mask) | pctl; } mask >>= 1; diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h index c0cd82b..4e7005b 100644 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -352,70 +352,70 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if defined(TM4C123x) +//#if defined(TM4C123x) #if TIVA_GPIO_GPIOA_USE_AHB -#define GPIOA GPIOA_AHB +#define GPIOA GPIO_PORTA_AHB_BASE #else -#define GPIOA GPIOA_APB +#define GPIOA GPIO_PORTA_BASE #endif #if TIVA_GPIO_GPIOB_USE_AHB -#define GPIOB GPIOB_AHB +#define GPIOB GPIO_PORTB_AHB_BASE #else -#define GPIOB GPIOB_APB +#define GPIOB GPIO_PORTB_BASE #endif #if TIVA_GPIO_GPIOC_USE_AHB -#define GPIOC GPIOC_AHB +#define GPIOC GPIO_PORTC_AHB_BASE #else -#define GPIOC GPIOC_APB +#define GPIOC GPIO_PORTC_BASE #endif #if TIVA_GPIO_GPIOD_USE_AHB -#define GPIOD GPIOD_AHB +#define GPIOD GPIO_PORTD_AHB_BASE #else -#define GPIOD GPIOD_APB +#define GPIOD GPIO_PORTD_BASE #endif #if TIVA_GPIO_GPIOE_USE_AHB -#define GPIOE GPIOE_AHB +#define GPIOE GPIO_PORTE_AHB_BASE #else -#define GPIOE GPIOE_APB +#define GPIOE GPIO_PORTE_BASE #endif #if TIVA_GPIO_GPIOF_USE_AHB -#define GPIOF GPIOF_AHB +#define GPIOF GPIO_PORTF_AHB_BASE #else -#define GPIOF GPIOF_APB +#define GPIOF GPIO_PORTF_BASE #endif #if TIVA_GPIO_GPIOG_USE_AHB -#define GPIOG GPIOG_AHB +#define GPIOG GPIO_PORTG_AHB_BASE #else -#define GPIOG GPIOG_APB +#define GPIOG GPIO_PORTG_BASE #endif #if TIVA_GPIO_GPIOH_USE_AHB -#define GPIOH GPIOH_AHB +#define GPIOH GPIO_PORTH_AHB_BASE #else -#define GPIOH GPIOH_APB +#define GPIOH GPIO_PORTH_BASE #endif #if TIVA_GPIO_GPIOJ_USE_AHB -#define GPIOJ GPIOJ_AHB +#define GPIOJ GPIO_PORTJ_AHB_BASE #else -#define GPIOJ GPIOJ_APB +#define GPIOJ GPIO_PORTJ_BASE #endif -#define GPIOK GPIOK_AHB -#define GPIOL GPIOL_AHB -#define GPIOM GPIOM_AHB -#define GPION GPION_AHB -#define GPIOP GPIOP_AHB -#define GPIOQ GPIOQ_AHB +#define GPIOK GPIO_PORTK_BASE +#define GPIOL GPIO_PORTL_BASE +#define GPIOM GPIO_PORTM_BASE +#define GPION GPIO_PORTN_BASE +#define GPIOP GPIO_PORTP_BASE +#define GPIOQ GPIO_PORTQ_BASE -#endif +//#endif /*===========================================================================*/ /* Driver data structures and types. */ @@ -550,7 +550,7 @@ typedef uint32_t iomode_t; /** * @brief Port Identifier. */ -typedef GPIO_TypeDef *ioportid_t; +typedef uint32_t ioportid_t; /*===========================================================================*/ /* Driver macros. */ @@ -573,7 +573,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readport(port) ((port)->DATA) +#define pal_lld_readport(port) (HWREG((port) + GPIO_O_DATA + (0xff << 2))) /** * @brief Reads the output latch. @@ -585,7 +585,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readlatch(port) ((port)->DATA) +#define pal_lld_readlatch(port) pal_lld_readport(port) /** * @brief Writes a bits mask on a I/O port. @@ -595,7 +595,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) +#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_DATA + (0xff << 2)) = (bits)) /** * @brief Sets a bits mask on a I/O port. @@ -608,7 +608,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) +#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0xFF) /** * @brief Clears a bits mask on a I/O port. @@ -621,7 +621,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) +#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0) /** * @brief Reads a group of bits. @@ -637,7 +637,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2)))) /** * @brief Writes a group of bits. @@ -654,7 +654,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))) = (bits)) /** * @brief Pads group mode setup. @@ -686,7 +686,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) +#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2)))) /** * @brief Writes a logical state on an output pad. @@ -704,7 +704,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit)) /** * @brief Sets a pad logical state to @p PAL_HIGH. @@ -718,7 +718,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (pad)) /** * @brief Clears a pad logical state to @p PAL_LOW. @@ -732,7 +732,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c index 870ba12..60d2b82 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c @@ -133,7 +133,7 @@ GPTDriver GPTD12; */ static void gpt_lld_serve_interrupt(GPTDriver *gptp) { - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; if (gptp->state == GPT_ONESHOT) { gptp->state = GPT_READY; @@ -388,62 +388,62 @@ void gpt_lld_init(void) { /* Driver initialization.*/ #if TIVA_GPT_USE_GPT0 - GPTD1.gpt = GPT0; + GPTD1.gpt = TIMER0_BASE; gptObjectInit(&GPTD1); #endif #if TIVA_GPT_USE_GPT1 - GPTD2.gpt = GPT1; + GPTD2.gpt = TIMER1_BASE; gptObjectInit(&GPTD2); #endif #if TIVA_GPT_USE_GPT2 - GPTD3.gpt = GPT2; + GPTD3.gpt = TIMER2_BASE; gptObjectInit(&GPTD3); #endif #if TIVA_GPT_USE_GPT3 - GPTD4.gpt = GPT3; + GPTD4.gpt = TIMER3_BASE; gptObjectInit(&GPTD4); #endif #if TIVA_GPT_USE_GPT4 - GPTD5.gpt = GPT4; + GPTD5.gpt = TIMER4_BASE; gptObjectInit(&GPTD5); #endif #if TIVA_GPT_USE_GPT5 - GPTD6.gpt = GPT5; + GPTD6.gpt = TIMER5_BASE; gptObjectInit(&GPTD6); #endif #if TIVA_GPT_USE_WGPT0 - GPTD7.gpt = WGPT0; + GPTD7.gpt = WTIMER0_BASE; gptObjectInit(&GPTD7); #endif #if TIVA_GPT_USE_WGPT1 - GPTD8.gpt = WGPT1; + GPTD8.gpt = WTIMER1_BASE; gptObjectInit(&GPTD8); #endif #if TIVA_GPT_USE_WGPT2 - GPTD9.gpt = WGPT2; + GPTD9.gpt = WTIMER2_BASE; gptObjectInit(&GPTD9); #endif #if TIVA_GPT_USE_WGPT3 - GPTD10.gpt = WGPT3; + GPTD10.gpt = WTIMER3_BASE; gptObjectInit(&GPTD10); #endif #if TIVA_GPT_USE_WGPT4 - GPTD11.gpt = WGPT4; + GPTD11.gpt = WTIMER4_BASE; gptObjectInit(&GPTD11); #endif #if TIVA_GPT_USE_WGPT5 - GPTD12.gpt = WGPT5; + GPTD12.gpt = WTIMER5_BASE; gptObjectInit(&GPTD12); #endif } @@ -461,9 +461,9 @@ void gpt_lld_start(GPTDriver *gptp) /* Clock activation.*/ #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 0); - while (!(SYSCTL->PRTIMER & (1 << 0))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) ; nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); @@ -472,9 +472,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 1); - while (!(SYSCTL->PRTIMER & (1 << 1))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) ; nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); @@ -483,9 +483,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 2); - while (!(SYSCTL->PRTIMER & (1 << 2))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) ; nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); @@ -494,9 +494,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 3); - while (!(SYSCTL->PRTIMER & (1 << 3))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) ; nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); @@ -505,9 +505,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 4); - while (!(SYSCTL->PRTIMER & (1 << 4))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) ; nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); @@ -516,9 +516,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 5); - while (!(SYSCTL->PRTIMER & (1 << 5))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) ; nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); @@ -527,9 +527,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0); - while (!(SYSCTL->PRWTIMER & (1 << 0))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) ; nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); @@ -538,9 +538,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1); - while (!(SYSCTL->PRWTIMER & (1 << 1))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) ; nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); @@ -549,9 +549,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2); - while (!(SYSCTL->PRWTIMER & (1 << 2))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) ; nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); @@ -560,9 +560,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3); - while (!(SYSCTL->PRWTIMER & (1 << 3))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) ; nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); @@ -571,9 +571,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4); - while (!(SYSCTL->PRWTIMER & (1 << 4))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) ; nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); @@ -582,9 +582,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5); - while (!(SYSCTL->PRWTIMER & (1 << 5))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) ; nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); @@ -593,9 +593,9 @@ void gpt_lld_start(GPTDriver *gptp) } /* Timer configuration.*/ - gptp->gpt->CTL = 0; - gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; - gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); + HWREG(gptp->gpt + TIMER_O_CTL) = 0; + HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT; + HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1); } /** @@ -608,91 +608,91 @@ void gpt_lld_start(GPTDriver *gptp) void gpt_lld_stop(GPTDriver *gptp) { if (gptp->state == GPT_READY) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL = 0; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) = 0; #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 5); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 5); } #endif } @@ -708,11 +708,11 @@ void gpt_lld_stop(GPTDriver *gptp) */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xfffffff; - gptp->gpt->IMR = GPTM_IMR_TATOIM; - gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff; + HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM; + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; } /** @@ -724,9 +724,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) */ void gpt_lld_stop_timer(GPTDriver *gptp) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL &= ~GPTM_CTL_TAEN; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN; } /** @@ -742,13 +742,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp) */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xffffffff; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; + while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM)) ; - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; } #endif /* HAL_USE_GPT */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h index e518e58..88a6809 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h @@ -405,7 +405,7 @@ struct GPTDriver { /** * @brief Pointer to the GPT registers block. */ - GPT_TypeDef *gpt; + uint32_t gpt; }; /*===========================================================================*/ @@ -426,7 +426,7 @@ struct GPTDriver { * @notapi */ #define gpt_lld_change_interval(gptp, interval) { \ - gptp->gpt->TAILR = interval - 1; \ + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; \ } /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index 30fdb8a..d87652b 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -67,8 +67,8 @@ #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_WGPT5A_HANDLER #define ST_NUMBER TIVA_WGPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -184,10 +184,10 @@ OSAL_IRQ_HANDLER(ST_HANDLER) OSAL_IRQ_PROLOGUE(); - mis = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->ICR = mis; + mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis; - if (mis & GPTM_IMR_TAMIM) { + if (mis & TIMER_IMR_TAMIM) { osalSysLockFromISR(); osalOsTimerHandlerI(); osalSysUnlockFromISR(); @@ -218,15 +218,17 @@ void st_lld_init(void) ST_WAIT_CLOCK(); /* Initializing the counter in free running down mode.*/ - TIVA_ST_TIM->CTL = 0; - TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ - - TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = 0; + HWREG(TIVA_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ + + HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ /* IRQ enabled.*/ nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h index 35bf008..cd076d6 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h @@ -29,7 +29,6 @@ #include "mcuconf.h" #include "tiva_registry.h" -#include "tiva_gpt.h" /*===========================================================================*/ /* Driver constants. */ @@ -82,37 +81,37 @@ #if !TIVA_HAS_WGPT0 #error "WGPT0 not present" #endif -#define TIVA_ST_TIM WGPT0 +#define TIVA_ST_TIM WTIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_WGPT1 #error "WGPT1 not present" #endif -#define TIVA_ST_TIM WGPT1 +#define TIVA_ST_TIM WTIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_WGPT2 #error "WGPT2 not present" #endif -#define TIVA_ST_TIM WGPT2 +#define TIVA_ST_TIM WTIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_WGPT3 #error "WGPT3 not present" #endif -#define TIVA_ST_TIM WGPT3 +#define TIVA_ST_TIM WTIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_WGPT4 #error "WGPT4 not present" #endif -#define TIVA_ST_TIM WGPT4 +#define TIVA_ST_TIM WTIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_WGPT5 #error "WGPT5 not present" #endif -#define TIVA_ST_TIM WGPT5 +#define TIVA_ST_TIM WTIMER5_BASE #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -124,37 +123,37 @@ #if !TIVA_HAS_GPT0 #error "GPT0 not present" #endif -#define TIVA_ST_TIM GPT0 +#define TIVA_ST_TIM TIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_GPT1 #error "GPT1 not present" #endif -#define TIVA_ST_TIM GPT1 +#define TIVA_ST_TIM TIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_GPT2 #error "GPT2 not present" #endif -#define TIVA_ST_TIM GPT2 +#define TIVA_ST_TIM TIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_GPT3 #error "GPT3 not present" #endif -#define TIVA_ST_TIM GPT3 +#define TIVA_ST_TIM TIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_GPT4 #error "GPT4 not present" #endif -#define TIVA_ST_TIM GPT4 +#define TIVA_ST_TIM TIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_GPT5 #error "GPT5 not present" #endif -#define TIVA_ST_TIM GPT5 +#define TIVA_ST_TIM TIMER5_BASE #else #error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" @@ -164,11 +163,6 @@ #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" #endif -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ST" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -202,7 +196,7 @@ extern "C" { */ static inline systime_t st_lld_get_counter(void) { - return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); + return (systime_t) (((systime_t) 0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAV)); } /** @@ -216,9 +210,9 @@ static inline systime_t st_lld_get_counter(void) */ static inline void st_lld_start_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); - TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; } /** @@ -228,7 +222,7 @@ static inline void st_lld_start_alarm(systime_t time) */ static inline void st_lld_stop_alarm(void) { - TIVA_ST_TIM->IMR = 0; + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = 0; } /** @@ -240,7 +234,7 @@ static inline void st_lld_stop_alarm(void) */ static inline void st_lld_set_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); } /** @@ -252,7 +246,7 @@ static inline void st_lld_set_alarm(systime_t time) */ static inline systime_t st_lld_get_alarm(void) { - return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); + return (systime_t) (((systime_t)0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR)); } /** @@ -266,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void) */ static inline bool st_lld_is_alarm_active(void) { - return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); + return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); } #endif /* HAL_ST_LLD_H */ diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index cb69861..cf70dca 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -30,6 +30,33 @@ /* Driver local definitions. */ /*===========================================================================*/ +// interrupt states +#define STATE_IDLE 0 +#define STATE_WRITE_NEXT 1 +#define STATE_WRITE_FINAL 2 +#define STATE_WAIT_ACK 3 +#define STATE_SEND_ACK 4 +#define STATE_READ_ONE 5 +#define STATE_READ_FIRST 6 +#define STATE_READ_NEXT 7 +#define STATE_READ_FINAL 8 +#define STATE_READ_WAIT 9 + +#define TIVA_I2C_SIGNLE_SEND (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_START (I2C_MCS_RUN | I2C_MCS_START) +#define TIVA_I2C_BURST_SEND_CONTINUE (I2C_MCS_RUN) +#define TIVA_I2C_BURST_SEND_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_STOP (I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_ERROR_STOP (I2C_MCS_STOP) + +#define TIVA_I2C_SINGLE_RECEIVE (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_START (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_CONTINUE (I2C_MCS_RUN | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (I2C_MCS_STOP) + +#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -125,19 +152,19 @@ I2CDriver I2CD10; */ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; uint32_t status; // clear MIS bit in MICR by writing 1 - dp->MICR = 1; + HWREG(i2c + I2C_O_MICR) = 1; // read interrupt status - status = dp->MCS; + status = HWREG(i2c + I2C_O_MCS); - if (status & TIVA_MCS_ERROR) { + if (status & I2C_MCS_ERROR) { i2cp->errors |= I2C_BUS_ERROR; } - if (status & TIVA_MCS_ARBLST) { + if (status & I2C_MCS_ARBLST) { i2cp->errors |= I2C_ARBITRATION_LOST; } @@ -152,11 +179,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if (i2cp->txbytes == 1) { i2cp->intstate = STATE_WRITE_FINAL; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE; break; } case STATE_WRITE_FINAL: { @@ -169,12 +196,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) else { i2cp->intstate = STATE_READ_FIRST; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; // txbytes - 1 i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH; break; } case STATE_WAIT_ACK: { @@ -189,10 +216,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; break; } @@ -208,10 +235,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START; break; } @@ -219,27 +246,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if(i2cp->rxbytes == 2) { i2cp->intstate = STATE_READ_FINAL; } - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE; break; } case STATE_READ_FINAL: { i2cp->intstate = STATE_READ_WAIT; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; - i2cp->rxbytes--; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH; break; } case STATE_READ_WAIT: { i2cp->intstate = STATE_IDLE; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; _i2c_wakeup_isr(i2cp); break; @@ -430,61 +457,61 @@ void i2c_lld_init(void) { #if TIVA_I2C_USE_I2C0 i2cObjectInit(&I2CD1); I2CD1.thread = NULL; - I2CD1.i2c = I2C0; + I2CD1.i2c = I2C0_BASE; #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 i2cObjectInit(&I2CD2); I2CD2.thread = NULL; - I2CD2.i2c = I2C1; + I2CD2.i2c = I2C1_BASE; #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 i2cObjectInit(&I2CD3); I2CD3.thread = NULL; - I2CD3.i2c = I2C2; + I2CD3.i2c = I2C2_BASE; #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 i2cObjectInit(&I2CD4); I2CD4.thread = NULL; - I2CD4.i2c = I2C3; + I2CD4.i2c = I2C3_BASE; #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 i2cObjectInit(&I2CD5); I2CD5.thread = NULL; - I2CD5.i2c = I2C4; + I2CD5.i2c = I2C4_BASE; #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 i2cObjectInit(&I2CD6); I2CD6.thread = NULL; - I2CD6.i2c = I2C5; + I2CD6.i2c = I2C5_BASE; #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 i2cObjectInit(&I2CD7); I2CD7.thread = NULL; - I2CD7.i2c = I2C6; + I2CD7.i2c = I2C6_BASE; #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 i2cObjectInit(&I2CD8); I2CD8.thread = NULL; - I2CD8.i2c = I2C7; + I2CD8.i2c = I2C7_BASE; #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 i2cObjectInit(&I2CD9); I2CD9.thread = NULL; - I2CD9.i2c = I2C8; + I2CD9.i2c = I2C8_BASE; #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 i2cObjectInit(&I2CD10); I2CD10.thread = NULL; - I2CD10.i2c = I2C9; + I2CD10.i2c = I2C9_BASE; #endif /* TIVA_I2C_USE_I2C9 */ } @@ -497,15 +524,15 @@ void i2c_lld_init(void) { */ void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; /* If in stopped state then enables the I2C clocks.*/ if (i2cp->state == I2C_STOP) { #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 0); + HWREG(SYSCTL_RCGCI2C) |= (1 << 0); - while (!(SYSCTL->PRI2C & (1 << 0))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 0))) ; nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); @@ -514,9 +541,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 1); + HWREG(SYSCTL_RCGCI2C) |= (1 << 1); - while (!(SYSCTL->PRI2C & (1 << 1))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 1))) ; nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); @@ -525,9 +552,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 2); + HWREG(SYSCTL_RCGCI2C) |= (1 << 2); - while (!(SYSCTL->PRI2C & (1 << 2))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 2))) ; nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); @@ -536,9 +563,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 3); + HWREG(SYSCTL_RCGCI2C) |= (1 << 3); - while (!(SYSCTL->PRI2C & (1 << 3))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 3))) ; nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); @@ -547,9 +574,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 4); + HWREG(SYSCTL_RCGCI2C) |= (1 << 4); - while (!(SYSCTL->PRI2C & (1 << 4))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 4))) ; nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); @@ -558,9 +585,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 5); + HWREG(SYSCTL_RCGCI2C) |= (1 << 5); - while (!(SYSCTL->PRI2C & (1 << 5))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 5))) ; nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); @@ -569,9 +596,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 6); + HWREG(SYSCTL_RCGCI2C) |= (1 << 6); - while (!(SYSCTL->PRI2C & (1 << 6))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 6))) ; nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); @@ -580,9 +607,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 7); + HWREG(SYSCTL_RCGCI2C) |= (1 << 7); - while (!(SYSCTL->PRI2C & (1 << 7))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 7))) ; nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); @@ -591,9 +618,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 8); + HWREG(SYSCTL_RCGCI2C) |= (1 << 8); - while (!(SYSCTL->PRI2C & (1 << 8))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 8))) ; nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); @@ -602,9 +629,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 9); + HWREG(SYSCTL_RCGCI2C) |= (1 << 9); - while (!(SYSCTL->PRI2C & (1 << 9))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 9))) ; nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); @@ -612,8 +639,8 @@ void i2c_lld_start(I2CDriver *i2cp) #endif /* TIVA_I2C_USE_I2C7 */ } - dp->MCR = 0x10; - dp->MTPR = MTPR_VALUE; + HWREG(i2c + I2C_O_MCR) = 0x10; + HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE; } /** @@ -625,7 +652,8 @@ void i2c_lld_start(I2CDriver *i2cp) */ void i2c_lld_stop(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; + /* If not in stopped state then disables the I2C clock.*/ if (i2cp->state != I2C_STOP) { @@ -635,76 +663,76 @@ void i2c_lld_stop(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 0); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0); nvicDisableVector(TIVA_I2C0_NUMBER); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 1); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1); nvicDisableVector(TIVA_I2C1_NUMBER); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 2); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2); nvicDisableVector(TIVA_I2C2_NUMBER); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 3); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3); nvicDisableVector(TIVA_I2C3_NUMBER); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 4); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4); nvicDisableVector(TIVA_I2C4_NUMBER); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 5); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5); nvicDisableVector(TIVA_I2C5_NUMBER); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 6); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6); nvicDisableVector(TIVA_I2C6_NUMBER); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 7); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7); nvicDisableVector(TIVA_I2C7_NUMBER); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 8); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8); nvicDisableVector(TIVA_I2C8_NUMBER); } #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 9); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9); nvicDisableVector(TIVA_I2C9_NUMBER); } #endif /* TIVA_I2C_USE_I2C9 */ - dp->MCR = 0; - dp->MTPR = 0; + HWREG(i2c + I2C_O_MCR) = 0; + HWREG(i2c + I2C_O_MTPR) = 0; } } @@ -733,7 +761,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -759,7 +787,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -771,10 +799,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, } /* set slave address */ - dp->MSA = addr; + HWREG(i2c + I2C_O_MSA) = addr; /* Starts the operation.*/ - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; /* Waits for the operation completion or a timeout.*/ return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); @@ -808,7 +836,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -833,7 +861,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -848,13 +876,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->addr = addr << 1 | 0; /* set slave address */ - dp->MSA = i2cp->addr; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; /* enable interrupts */ - dp->MIMR = TIVA_MIMR_IM; + HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM; /* put data in register */ - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); /* check if 1 or more bytes */ if (i2cp->txbytes == 1) { @@ -867,7 +895,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_READ_FIRST; } // single byte send - dp->MCS = TIVA_I2C_SIGNLE_SEND; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND; } else { if (i2cp->txbytes == 2) { @@ -879,7 +907,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_WRITE_NEXT; } // multiple bytes start send - dp->MCS = TIVA_I2C_BURST_SEND_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START; } i2cp->txbuf++; diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h index 460d231..4eabda8 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h @@ -31,80 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -440,7 +366,7 @@ struct I2CDriver { /** * @brief Pointer to the I2Cx registers block. */ - I2C_TypeDef *i2c; + uint32_t i2c; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c index 04177b6..cf64bbb 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c @@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; */ static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - ETH->MIIDATA = value; - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; + HWREG(EMAC_O_MIIDATA) = value; + HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; } @@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) */ static uint32_t mii_read(MACDriver *macp, uint32_t reg) { - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; + HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; - return ETH->MIIDATA; + return HWREG(EMAC_O_MIIDATA); } /** @@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp) #endif for (i = 0; i < 31; i++) { macp->phyaddr = i << 11; - ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; + HWREG(EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR; if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { return; @@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p) { /* MAC address configuration, only a single address comparator is used, hash table not used.*/ - ETH->ADDR0H = ((uint32_t)p[5] << 8) | + HWREG(EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) | ((uint32_t)p[4] << 0); - ETH->ADDR0L = ((uint32_t)p[3] << 24) | + HWREG(EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) | ((uint32_t)p[2] << 16) | ((uint32_t)p[1] << 8) | ((uint32_t)p[0] << 0); - ETH->ADDR1H = 0x0000FFFF; - ETH->ADDR1L = 0xFFFFFFFF; - ETH->ADDR2H = 0x0000FFFF; - ETH->ADDR2L = 0xFFFFFFFF; - ETH->ADDR3H = 0x0000FFFF; - ETH->ADDR3L = 0xFFFFFFFF; - ETH->HASHTBLH = 0; - ETH->HASHTBLL = 0; + HWREG(EMAC_O_ADDR1H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR1L) = 0xFFFFFFFF; + HWREG(EMAC_O_ADDR2H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR2L) = 0xFFFFFFFF; + HWREG(EMAC_O_ADDR3H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR3L) = 0xFFFFFFFF; + HWREG(EMAC_O_HASHTBLH) = 0; + HWREG(EMAC_O_HASHTBLL) = 0; } /*===========================================================================*/ @@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER) CH_IRQ_PROLOGUE(); - dmaris = ETH->DMARIS; - ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ + dmaris = HWREG(EMAC_O_DMARIS); + HWREG(EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/ if (dmaris & (1 << 6)) { /* Data Received.*/ @@ -275,26 +275,26 @@ void mac_lld_init(void) } /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Set PHYHOLD bit */ - ETH->PC |= 1; + HWREG(EMAC_O_PC) |= 1; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; /* Enable power to PHY */ - SYSCTL->PCEPHY |= 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_PCEPHY) |= 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; #if BOARD_PHY_RMII - ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); + HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28); #else - ETH->PC = EMAC_PHY_CONFIG; + HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG; #endif /* @@ -310,12 +310,12 @@ void mac_lld_init(void) /* Set done bit after writing EMACPC register */ mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); - while(ETH->DMABUSMOD & 1) + while(HWREG(EMAC_O_DMABUSMOD) & 1) ; /* Reset MAC */ - ETH->DMABUSMOD |= 1; - while (ETH->DMABUSMOD & 1) + HWREG(EMAC_O_DMABUSMOD) |= 1; + while (HWREG(EMAC_O_DMABUSMOD) & 1) ; /* PHY address setup.*/ @@ -344,10 +344,10 @@ void mac_lld_init(void) #endif /* Disable MAC clock */ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* Disable PHY clock */ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; } /** @@ -374,13 +374,13 @@ void mac_lld_start(MACDriver *macp) macp->txptr = (tiva_eth_tx_descriptor_t *)td; /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (!SYSCTL->PREPHY) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (!HWREG(SYSCTL_PREPHY)) ; /* ISR vector enabled.*/ @@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp) #endif /* MAC configuration.*/ - ETH->FRAMEFLTR = 0; - ETH->FLOWCTL = 0; - ETH->VLANTG = 0; + HWREG(EMAC_O_FRAMEFLTR) = 0; + HWREG(EMAC_O_FLOWCTL) = 0; + HWREG(EMAC_O_VLANTG) = 0; /* MAC address setup.*/ if (macp->config->mac_address == NULL) @@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp) Note that the complete setup of the MAC is performed when the link status is detected.*/ #if TIVA_MAC_IP_CHECKSUM_OFFLOAD - ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); + HWREG(EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2); #else - ETH->CFG = (1 << 3) | (1 << 2); + HWREG(EMAC_O_CFG) = (1 << 3) | (1 << 2); #endif /* DMA configuration: Descriptor chains pointers.*/ - ETH->RXDLADDR = (uint32_t)rd; - ETH->TXDLADDR = (uint32_t)td; + HWREG(EMAC_O_RXDLADDR) = (uint32_t)rd; + HWREG(EMAC_O_TXDLADDR) = (uint32_t)td; /* Enabling required interrupt sources.*/ - ETH->DMARIS &= 0xFFFF; - ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); + HWREG(EMAC_O_DMARIS) &= 0xFFFF; + HWREG(EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0); /* DMA general settings.*/ - ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); + HWREG(EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8); /* Transmit FIFO flush.*/ - ETH->DMAOPMODE = (1 << 20); - while (ETH->DMAOPMODE & (1 << 20)) + HWREG(EMAC_O_DMAOPMODE) = (1 << 20); + while (HWREG(EMAC_O_DMAOPMODE) & (1 << 20)) ; /* DMA final configuration and start.*/ - ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | + HWREG(EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) | (1 << 13) | (1 << 1); } @@ -449,16 +449,16 @@ void mac_lld_stop(MACDriver *macp) #endif /* MAC and DMA stopped.*/ - ETH->CFG = 0; - ETH->DMAOPMODE = 0; - ETH->DMAIM = 0; - ETH->DMARIS &= 0xFFFF; + HWREG(EMAC_O_CFG) = 0; + HWREG(EMAC_O_DMAOPMODE) = 0; + HWREG(EMAC_O_DMAIM) = 0; + HWREG(EMAC_O_DMARIS) &= 0xFFFF; /* MAC clocks stopped.*/ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* PHY clock stopped.*/ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; /* ISR vector disabled.*/ nvicDisableVector(TIVA_MAC_NUMBER); @@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) tdp->physdesc->locked = 0; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { - ETH->DMARIS = (1 << 2); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) { + HWREG(EMAC_O_DMARIS) = (1 << 2); + HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) rdp->physdesc->rdes0 = TIVA_RDES0_OWN; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { - ETH->DMARIS = (1 << 7); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) { + HWREG(EMAC_O_DMARIS) = (1 << 7); + HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) { uint32_t maccfg, bmsr, bmcr; - maccfg = ETH->CFG; + maccfg = HWREG(EMAC_O_CFG); /* PHY CR and SR registers read.*/ (void)mii_read(macp, MII_BMSR); @@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) } /* Changes the mode in the MAC.*/ - ETH->CFG = maccfg; + HWREG(EMAC_O_CFG) = maccfg; /* Returns the link status.*/ return macp->link_up = true; diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h index 98036bb..98036bb 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c index ad7c587..964f45b 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c @@ -30,13 +30,6 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -59,6 +52,8 @@ PWMDriver PWMD2; /* Driver local variables and types. */ /*===========================================================================*/ +static uint32_t pwm_generator_offsets[] = { PWM_GEN_0_OFFSET, PWM_GEN_1_OFFSET, PWM_GEN_2_OFFSET, PWM_GEN_3_OFFSET}; + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -75,35 +70,36 @@ PWMDriver PWMD2; static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) { uint32_t isc; + uint32_t pwm = pwmp->pwm; - isc = pwmp->pwm->PWM[i].ISC; - pwmp->pwm->PWM[i].ISC = isc; + isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc; - if (((isc & PWM_INT_CMPAD) != 0) && + if (((isc & PWM_X_ISC_INTCMPAD) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPAU) != 0) && + if (((isc & PWM_X_ISC_INTCMPAU) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPBD) != 0) && + if (((isc & PWM_X_ISC_INTCMPBD) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CMPBU) != 0) && + if (((isc & PWM_X_ISC_INTCMPBU) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } } @@ -311,13 +307,13 @@ void pwm_lld_init(void) #if TIVA_PWM_USE_PWM0 pwmObjectInit(&PWMD1); PWMD1.channels = PWM_CHANNELS; - PWMD1.pwm = PWM0; + PWMD1.pwm = PWM0_BASE; #endif #if TIVA_PWM_USE_PWM1 pwmObjectInit(&PWMD2); PWMD2.channels = PWM_CHANNELS; - PWMD2.pwm = PWM1; + PWMD2.pwm = PWM1_BASE; #endif } @@ -335,14 +331,15 @@ void pwm_lld_start(PWMDriver *pwmp) uint8_t i; uint32_t invert = 0; uint32_t enable = 0; + uint32_t pwm = pwmp->pwm; if (pwmp->state == PWM_STOP) { /* Clock activation.*/ #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 0); + HWREG(SYSCTL_RCGCPWM) |= (1 << 0); - while (!(SYSCTL->PRPWM & (1 << 0))) + while (!(HWREG(SYSCTL_PRPWM) & (1 << 0))) ; nvicEnableVector(TIVA_PWM0FAULT_NUMBER, @@ -356,9 +353,9 @@ void pwm_lld_start(PWMDriver *pwmp) #if TIVA_PWM_USE_PWM1 if (&PWMD2 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 1); + HWREG(SYSCTL_RCGCPWM) |= (1 << 1); - while (!(SYSCTL->PRPWM & (1 << 1))) + while (!(HWREG(SYSCTL_PRPWM) & (1 << 1))) ; nvicEnableVector(TIVA_PWM1FAULT_NUMBER, @@ -372,20 +369,20 @@ void pwm_lld_start(PWMDriver *pwmp) } else { /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; } /* Timer configuration.*/ for (i = 0; i < (PWM_CHANNELS >> 1); i++) { - pwmp->pwm->PWM[i].CTL = 0; - pwmp->pwm->PWM[i].GEN[0] = 0x08C; - pwmp->pwm->PWM[i].GEN[1] = 0x80C; - pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); - pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); - pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CTL) = 0; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENA) = 0x08C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENB) = 0x80C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_LOAD) = (uint16_t)(pwmp->config->frequency - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPA) = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPB) = (uint16_t)(pwmp->period - 1); } /* Output enables and polarities setup.*/ @@ -407,9 +404,9 @@ void pwm_lld_start(PWMDriver *pwmp) } } - pwmp->pwm->INVERT = invert; - pwmp->pwm->ENABLE = enable; - pwmp->pwm->ISC = 0xFFFFFFFF; + HWREG(pwm + PWM_O_INVERT) = invert; + HWREG(pwm + PWM_O_ENABLE) = enable; + HWREG(pwm + PWM_O_ISC) = 0xFFFFFFFF; } /** @@ -421,12 +418,14 @@ void pwm_lld_start(PWMDriver *pwmp) */ void pwm_lld_stop(PWMDriver *pwmp) { + uint32_t pwm = pwmp->pwm; + /* If in ready state then disables the PWM clock.*/ if (pwmp->state == PWM_READY) { - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { @@ -435,7 +434,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM0GEN1_NUMBER); nvicDisableVector(TIVA_PWM0GEN2_NUMBER); nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 0); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 0); } #endif @@ -446,7 +445,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM1GEN1_NUMBER); nvicDisableVector(TIVA_PWM1GEN2_NUMBER); nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 1); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 1); } #endif } @@ -469,9 +468,16 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width) { + uint32_t pwm = pwmp->pwm; + /* Changing channel duty cycle on the fly.*/ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; - pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = width; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = width; + + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -488,8 +494,14 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; - pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); + uint32_t pwm = pwmp->pwm; + + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = 0; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = 0; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -505,18 +517,19 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { uint32_t inten; uint8_t i; + uint32_t pwm = pwmp->pwm; /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ for(i = 0; i < (PWM_CHANNELS >> 1); i++) { - inten = pwmp->pwm->PWM[i].INTEN; + inten = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN); if ((inten & 0x03) == 0) { - pwmp->pwm->PWM[i].INTEN |= 0x03; - pwmp->pwm->PWM[i].ISC = 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN) |= 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = 0x03; } } - pwmp->pwm->INTEN = 0x3f; + HWREG(pwm + PWM_O_INTEN) = 0x3f; } /** @@ -530,11 +543,14 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) */ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { - pwmp->pwm->PWM[0].INTEN &= ~(0x03); - pwmp->pwm->PWM[1].INTEN &= ~(0x03); - pwmp->pwm->PWM[2].INTEN &= ~(0x03); - pwmp->pwm->PWM[3].INTEN &= ~(0x03); - pwmp->pwm->INTEN &= ~(0x3F); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + PWM_O_0_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_1_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_2_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_3_INTEN) = ~(0x03); + + HWREG(pwm + PWM_O_INTEN) &= ~(0x3F); } /** @@ -551,13 +567,14 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) void pwm_lld_enable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; + uint32_t pwm = pwmp->pwm; + uint32_t inten = HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC); /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { - pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); - pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) |= (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC) = (0x03 << (((channel & 1) * 2) + 2)); } } @@ -575,7 +592,9 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, void pwm_lld_disable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) = ~(0x03 << (((channel & 1) * 2) + 2)); } #endif /* HAL_USE_PWM */ diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h index ac64fe1..7ddbd4d 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h @@ -304,7 +304,7 @@ struct PWMDriver { /** * @brief Pointer to the PWMx registers block. */ - PWM_TypeDef *pwm; + uint32_t pwm; }; /*===========================================================================*/ @@ -328,10 +328,10 @@ struct PWMDriver { * @notapi */ #define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) + HWREG((pwmp)->pwm + PWM_O_0_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_1_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_2_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_3_LOAD) = (uint16_t)((period) - 1) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index ded2b99..42efca6 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -77,19 +77,19 @@ static uint16_t dummyrx; */ static void spi_serve_interrupt(SPIDriver *spip) { - SSI_TypeDef *ssi = spip->ssi; - uint32_t mis = ssi->MIS; - uint32_t dmachis = UDMA->CHIS; + uint32_t ssi = spip->ssi; + uint32_t mis = HWREG(ssi + SSI_O_MIS); + uint32_t dmachis = HWREG(UDMA_CHIS); /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { + if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) { TIVA_SPI_SSI_ERROR_HOOK(spip); } - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { + if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) == + (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) { /* Clear DMA Channel interrupts.*/ - UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); + HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); /* Portable SPI ISR code defined in the high level driver, note, it is a macro.*/ @@ -180,7 +180,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI0 spiObjectInit(&SPID1); - SPID1.ssi = SSI0; + SPID1.ssi = SSI0_BASE; SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; @@ -189,7 +189,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI1 spiObjectInit(&SPID2); - SPID2.ssi = SSI1; + SPID2.ssi = SSI1_BASE; SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; @@ -198,7 +198,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI2 spiObjectInit(&SPID3); - SPID3.ssi = SSI2; + SPID3.ssi = SSI2_BASE; SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; @@ -207,7 +207,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI3 spiObjectInit(&SPID4); - SPID4.ssi = SSI3; + SPID4.ssi = SSI3_BASE; SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; @@ -235,8 +235,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 0); - while (!(SYSCTL->PRSSI & (1 << 0))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 0); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 0))) ; nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); @@ -251,8 +251,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 1); - while (!(SYSCTL->PRSSI & (1 << 1))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 1); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 1))) ; nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); @@ -267,8 +267,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 2); - while (!(SYSCTL->PRSSI & (1 << 2))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 2); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 2))) ; nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); @@ -283,40 +283,40 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 3); - while (!(SYSCTL->PRSSI & (1 << 3))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 3); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 3))) ; nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); } #endif - UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); - UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmarxnr / 8) * 4) |= (spip->rxchnmap << (spip->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmatxnr / 8) * 4) |= (spip->txchnmap << (spip->dmatxnr % 8)); } /* Set master operation mode.*/ - spip->ssi->CR1 = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; /* Clock configuration - System Clock.*/ - spip->ssi->CC = 0; + HWREG(spip->ssi + SSI_O_CC) = 0; /* Clear pending interrupts.*/ - spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; + HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC; /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; + HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM; /* Configure the clock prescale divisor.*/ - spip->ssi->CPSR = spip->config->cpsr; + HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr; /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); + HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO; /* Enable SSI.*/ - spip->ssi->CR1 |= TIVA_CR1_SSE; + HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE; /* Enable RX and TX DMA channels.*/ - spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); + HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE); } /** @@ -329,9 +329,9 @@ void spi_lld_start(SPIDriver *spip) void spi_lld_stop(SPIDriver *spip) { if (spip->state != SPI_STOP) { - spip->ssi->CR1 = 0; - spip->ssi->CR0 = 0; - spip->ssi->CPSR = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; + HWREG(spip->ssi + SSI_O_CR0) = 0; + HWREG(spip->ssi + SSI_O_CPSR) = 0; udmaChannelRelease(spip->dmarxnr); udmaChannelRelease(spip->dmatxnr); @@ -399,20 +399,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -420,17 +420,17 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -470,20 +470,20 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -491,17 +491,17 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -539,20 +539,20 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -560,17 +560,17 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -608,20 +608,20 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -629,17 +629,17 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -674,10 +674,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) */ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - spip->ssi->DR = (uint32_t)frame; - while ((spip->ssi->SR & TIVA_SR_RNE) == 0) + HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame; + while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0) ; - return (uint16_t)spip->ssi->DR; + return (uint16_t)HWREG(spip->ssi + SSI_O_DR); } #endif /* HAL_USE_SPI */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 2adc9ed..dd49e84 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -32,89 +32,9 @@ /*===========================================================================*/ /** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ - */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ + * @brief CR0 Serial Clock Rate helper. */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ +#define SSI_CR0_SCR(n) ((n) << 8) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -320,7 +240,7 @@ struct SPIDriver { /** * @brief Pointer to the SSI registers block. */ - SSI_TypeDef *ssi; + uint32_t ssi; /** * @brief Receive DMA channel number. */ diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c index 89d29da..2e3b213 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c @@ -34,58 +34,42 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** - * @brief UART0 serial driver identifier. - */ +/** @brief UART0 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) SerialDriver SD1; #endif -/** - * @brief UART1 serial driver identifier. - */ +/** @brief UART1 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) SerialDriver SD2; #endif -/** - * @brief UART2 serial driver identifier. - */ +/** @brief UART2 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) SerialDriver SD3; #endif -/** - * @brief UART3 serial driver identifier. - */ +/** @brief UART3 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) SerialDriver SD4; #endif -/** - * @brief UART4 serial driver identifier. - */ +/** @brief UART4 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) SerialDriver SD5; #endif -/** - * @brief UART5 serial driver identifier. - */ +/** @brief UART5 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) SerialDriver SD6; #endif -/** - * @brief UART6 serial driver identifier. - */ +/** @brief UART6 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) SerialDriver SD7; #endif -/** - * @brief UART7 serial driver identifier. - */ +/** @brief UART7 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) SerialDriver SD8; #endif @@ -94,14 +78,14 @@ SerialDriver SD8; /* Driver local variables. */ /*===========================================================================*/ -/** - * @brief Driver default configuration. - */ +/** @brief Driver default configuration.*/ static const SerialConfig sd_default_config = { SERIAL_DEFAULT_BITRATE, - TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, - TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E + 0, + UART_LCRH_FEN | UART_LCRH_WLEN_8, + UART_IFLS_TX4_8 | UART_IFLS_RX7_8, + UART_CC_CS_SYSCLK }; /*===========================================================================*/ @@ -111,23 +95,55 @@ static const SerialConfig sd_default_config = /** * @brief UART initialization. * - * @param[in] sdp communication channel associated to the UART + * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration */ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - UART_TypeDef *u = sdp->uart; - uint32_t div; /* baud rate divisor */ - - /* disable the UART before any of the control registers are reprogrammed */ - u->CTL &= ~TIVA_CTL_UARTEN; - div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; - u->IBRD = div / 64; /* integer portion of the baud rate divisor */ - u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ - u->LCRH = config->sc_lcrh; /* set data format */ - u->IFLS = config->sc_ifls; - u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; - u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ + uint32_t u = sdp->uart; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_SYSCLK) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM; } /** @@ -135,9 +151,9 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) * * @param[in] u pointer to an UART I/O block */ -static void uart_deinit(UART_TypeDef *u) +static void uart_deinit(uint32_t u) { - u->CTL &= ~TIVA_CTL_UARTEN; + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; } /** @@ -150,13 +166,13 @@ static void set_error(SerialDriver *sdp, uint16_t err) { eventflags_t sts = 0; - if (err & TIVA_MIS_FEMIS) + if (err & UART_MIS_FEMIS) sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) + if (err & UART_MIS_PEMIS) sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) + if (err & UART_MIS_BEMIS) sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) + if (err & UART_MIS_OEMIS) sts |= SD_OVERRUN_ERROR; osalSysLockFromISR(); chnAddFlagsI(sdp, sts); @@ -174,44 +190,44 @@ static void set_error(SerialDriver *sdp, uint16_t err) */ static void serial_serve_interrupt(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; - uint16_t mis = u->MIS; + uint32_t u = sdp->uart; + uint16_t mis = HWREG(u + UART_O_MIS); - u->ICR = mis; /* clear interrupts */ + HWREG(u + UART_O_ICR) = mis; /* clear interrupts */ - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { + if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) { set_error(sdp, mis); } - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { + if ((mis & UART_MIS_RXMIS) || (mis & UART_MIS_RTMIS)) { osalSysLockFromISR(); if (iqIsEmptyI(&sdp->iqueue)) { chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); } osalSysUnlockFromISR(); - while ((u->FR & TIVA_FR_RXFE) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) { osalSysLockFromISR(); - if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { + if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) { chnAddFlagsI(sdp, SD_OVERRUN_ERROR); } osalSysUnlockFromISR(); } } - if (mis & TIVA_MIS_TXMIS) { - while ((u->FR & TIVA_FR_TXFF) == 0) { + if (mis & UART_MIS_TXMIS) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b; osalSysLockFromISR(); b = oqGetI(&sdp->oqueue); osalSysUnlockFromISR(); if (b < Q_OK) { - u->IM &= ~TIVA_IM_TXIM; + HWREG(u + UART_O_IM) &= ~UART_IM_TXIM; osalSysLockFromISR(); chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); osalSysUnlockFromISR(); break; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } } } @@ -221,17 +237,18 @@ static void serial_serve_interrupt(SerialDriver *sdp) */ static void fifo_load(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; + uint32_t u = sdp->uart; - while ((u->FR & TIVA_FR_TXFF) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b = oqGetI(&sdp->oqueue); if (b < Q_OK) { chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); return; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } - u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ + + HWREG(u + UART_O_IM) |= UART_IM_TXIM; /* transmit interrupt enable */ } /** @@ -452,42 +469,42 @@ void sd_lld_init(void) { #if TIVA_SERIAL_USE_UART0 sdObjectInit(&SD1, NULL, notify1); - SD1.uart = UART0; + SD1.uart = UART0_BASE; #endif #if TIVA_SERIAL_USE_UART1 sdObjectInit(&SD2, NULL, notify2); - SD2.uart = UART1; + SD2.uart = UART1_BASE; #endif #if TIVA_SERIAL_USE_UART2 sdObjectInit(&SD3, NULL, notify3); - SD3.uart = UART2; + SD3.uart = UART2_BASE; #endif #if TIVA_SERIAL_USE_UART3 sdObjectInit(&SD4, NULL, notify4); - SD4.uart = UART3; + SD4.uart = UART3_BASE; #endif #if TIVA_SERIAL_USE_UART4 sdObjectInit(&SD5, NULL, notify5); - SD5.uart = UART4; + SD5.uart = UART4_BASE; #endif #if TIVA_SERIAL_USE_UART5 sdObjectInit(&SD6, NULL, notify6); - SD6.uart = UART5; + SD6.uart = UART5_BASE; #endif #if TIVA_SERIAL_USE_UART6 sdObjectInit(&SD7, NULL, notify7); - SD7.uart = UART6; + SD7.uart = UART6_BASE; #endif #if TIVA_SERIAL_USE_UART7 sdObjectInit(&SD8, NULL, notify8); - SD8.uart = UART7; + SD8.uart = UART7_BASE; #endif } @@ -507,9 +524,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) if (sdp->state == SD_STOP) { #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART |= (1 << 0); + HWREG(SYSCTL_RCGCUART) |= (1 << 0); - while (!(SYSCTL->PRUART & (1 << 0))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) ; nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); @@ -517,9 +534,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGCUART |= (1 << 1); + HWREG(SYSCTL_RCGCUART) |= (1 << 1); - while (!(SYSCTL->PRUART & (1 << 1))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) ; nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); @@ -527,9 +544,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGCUART |= (1 << 2); + HWREG(SYSCTL_RCGCUART) |= (1 << 2); - while (!(SYSCTL->PRUART & (1 << 2))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) ; nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); @@ -537,9 +554,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGCUART |= (1 << 3); + HWREG(SYSCTL_RCGCUART) |= (1 << 3); - while (!(SYSCTL->PRUART & (1 << 3))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) ; nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); @@ -547,9 +564,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGCUART |= (1 << 4); + HWREG(SYSCTL_RCGCUART) |= (1 << 4); - while (!(SYSCTL->PRUART & (1 << 4))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) ; nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); @@ -557,9 +574,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGCUART |= (1 << 5); + HWREG(SYSCTL_RCGCUART) |= (1 << 5); - while (!(SYSCTL->PRUART & (1 << 5))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) ; nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); @@ -567,9 +584,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGCUART |= (1 << 6); + HWREG(SYSCTL_RCGCUART) |= (1 << 6); - while (!(SYSCTL->PRUART & (1 << 6))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) ; nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); @@ -577,9 +594,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGCUART |= (1 << 7); + HWREG(SYSCTL_RCGCUART) |= (1 << 7); - while (!(SYSCTL->PRUART & (1 << 7))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) ; nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); @@ -602,56 +619,56 @@ void sd_lld_stop(SerialDriver *sdp) uart_deinit(sdp->uart); #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); /* disable UART0 module */ nvicDisableVector(TIVA_UART0_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 1); /* disable UART1 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); /* disable UART1 module */ nvicDisableVector(TIVA_UART1_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 2); /* disable UART2 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); /* disable UART2 module */ nvicDisableVector(TIVA_UART2_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 3); /* disable UART3 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); /* disable UART3 module */ nvicDisableVector(TIVA_UART3_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 4); /* disable UART4 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); /* disable UART4 module */ nvicDisableVector(TIVA_UART4_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 5); /* disable UART5 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); /* disable UART5 module */ nvicDisableVector(TIVA_UART5_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 6); /* disable UART6 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); /* disable UART6 module */ nvicDisableVector(TIVA_UART6_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 7); /* disable UART7 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); /* disable UART7 module */ nvicDisableVector(TIVA_UART7_NUMBER); return; } diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h index 203ef6a..d52828c 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h @@ -31,163 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} - */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) - -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -388,22 +231,32 @@ * @brief Tiva Serial Driver configuration structure. * @details An instance of this structure must be passed to @p sdStart() * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. */ typedef struct { /** * @brief Bit rate. */ - uint32_t sc_speed; + uint32_t speed; /* End of the mandatory fields. */ /** - * @brief Initialization value for the LCRH (Line Control) register. + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. */ - uint32_t sc_lcrh; + uint8_t ifls; /** - * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) - * register. + * @brief Initialization value for the CC register. */ - uint32_t sc_ifls; + uint8_t cc; } SerialConfig; /** @@ -423,7 +276,7 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \ /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ - UART_TypeDef *uart; + uint32_t uart; /*===========================================================================*/ /* Driver macros. */ diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c index 38dcef0..ddd01e0 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c @@ -60,14 +60,14 @@ static void serve_interrupt(WDGDriver *wdgp) { uint32_t mis; - mis = wdgp->wdt->MIS; + mis = HWREG(wdgp->wdt + WDT_O_MIS); - if (mis & MIS_WDTMIS) { + if (mis & WDT_MIS_WDTMIS) { /* Invoke callback, if any */ if (wdgp->config->callback) { if (wdgp->config->callback(wdgp)) { /* Clear interrupt */ - wdgp->wdt->ICR = 0; + HWREG(wdgp->wdt + WDT_O_ICR) = 0; wdgTivaSyncWrite(wdgp); } } @@ -113,12 +113,12 @@ void wdg_lld_init(void) { #if TIVA_WDG_USE_WDT0 WDGD1.state = WDG_STOP; - WDGD1.wdt = WDT0; + WDGD1.wdt = WATCHDOG0_BASE; #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 WDGD2.state = WDG_STOP; - WDGD2.wdt = WDT1; + WDGD2.wdt = WATCHDOG1_BASE; #endif /* TIVA_WDG_USE_WDT1 */ /* The shared vector is initialized on driver initialization and never @@ -137,32 +137,32 @@ void wdg_lld_start(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->RCGCWD |= (1 << 0); + HWREG(SYSCTL_RCGCWD) |= (1 << 0); - while (!(SYSCTL->PRWD & (1 << 0))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 0))) ; } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->RCGCWD |= (1 << 1); + HWREG(SYSCTL_RCGCWD) |= (1 << 1); - while (!(SYSCTL->PRWD & (1 << 1))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 1))) ; } #endif /* TIVA_WDG_USE_WDT1 */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); - wdgp->wdt->TEST = wdgp->config->test; + HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_RESEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_INTEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN; wdgTivaSyncWrite(wdgp); } @@ -177,15 +177,15 @@ void wdg_lld_stop(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->SRWD |= (1 << 0); - SYSCTL->SRWD &= ~(1 << 0); + HWREG(SYSCTL_SRWD) |= (1 << 0); + HWREG(SYSCTL_SRWD) &= ~(1 << 0); } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->SRWD |= (1 << 1); - SYSCTL->SRWD &= ~(1 << 1); + HWREG(SYSCTL_SRWD) |= (1 << 1); + HWREG(SYSCTL_SRWD) &= ~(1 << 1); } #endif /* TIVA_WDG_USE_WDT1 */ } @@ -219,7 +219,7 @@ void wdg_lld_reset(WDGDriver *wdgp) #endif /* defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); } @@ -234,7 +234,7 @@ void wdg_lld_reset(WDGDriver *wdgp) void wdgTivaSyncWrite(WDGDriver *wdgp) { if (&WDGD2 == wdgp) { - while (!(wdgp->wdt->CTL & CTL_WRC)) { + while (!(HWREG(wdgp->wdt + WDT_O_CTL) & CTL_WRC)) { ; } } diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h index f88fa26..77badb3 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h @@ -32,23 +32,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -146,7 +129,7 @@ struct WDGDriver /** * @brief Pointer to the WDT registers block. */ - WDT_TypeDef *wdt; + uint32_t wdt; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c index 9f122b2..bb379cb 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.c +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c @@ -75,8 +75,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) /* TODO Do we need to halt the system on a DMA error?*/ - if (UDMA->ERRCLR) { - UDMA->ERRCLR = 1; + if (HWREG(UDMA_ERRCLR)) { + HWREG(UDMA_ERRCLR) = 1; } OSAL_IRQ_EPILOGUE(); @@ -96,18 +96,18 @@ void udmaInit(void) udma_channel_mask = 0; /* Enable UDMA module.*/ - SYSCTL->RCGCDMA = 1; - while (!(SYSCTL->PRDMA & (1 << 0))) + HWREG(SYSCTL_RCGCDMA) = 1; + while (!(HWREG(SYSCTL_PRDMA) & (1 << 0))) ; nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); /* Enable UDMA controller.*/ - UDMA->CFG = 1; + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; /* Set address of control table.*/ - UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; + HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary; } /** diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h index 6479b08..0157277 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.h +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h @@ -22,52 +22,9 @@ /*===========================================================================*/ /** - * @name CHCTL register defines. - * @{ + * @brief CHCTL XFERSIZE helper. */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 #define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -137,43 +94,43 @@ typedef struct __attribute__((packed, aligned(1024))) /*===========================================================================*/ #define dmaChannelEnable(dmach) {\ - UDMA->ENASET = (1 << dmach);\ + HWREG(UDMA_ENASET) = (1 << dmach);\ } #define dmaChannelDisable(dmach) { \ - UDMA->ENACLR = (1 << dmach); \ + HWREG(UDMA_ENACLR) = (1 << dmach); \ } #define dmaChannelPrimary(dmach) {\ - UDMA->ALTCLR = (1 << dmach); \ + HWREG(UDMA_ALTCLR) = (1 << dmach); \ } #define dmaChannelAlternate(dmach) { \ - UDMA->ALTSET = (1 << dmach); \ + HWREG(UDMA_ALTSET) = (1 << dmach); \ } #define dmaChannelSingleBurst(dmach) { \ - UDMA->USEBURSTCLR = (1 << dmach); \ + HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \ } #define dmaChannelBurstOnly(dmach) { \ - UDMA->USEBURSTSET = (1 << dmach); \ + HWREG(UDMA_USEBURSTSET) = (1 << dmach); \ } #define dmaChannelPriorityHigh(dmach) { \ - UDMA->PRIOSET = (1 << dmach); \ + HWREG(UDMA_PRIOSET) = (1 << dmach); \ } #define dmaChannelPriorityDefault(dmach) { \ - UDMA->PRIOCLR = (1 << dmach); \ + HWREG(UDMA_PRIOCLR) = (1 << dmach); \ } #define dmaChannelEnableRequest(dmach) {\ - UDMA->REQMASKCLR = (1 << dmach); \ + HWREG(UDMA_REQMASKCLR) = (1 << dmach); \ } #define dmaChannelDisableRequest(dmach) {\ - UDMA->REQMASKSET = (1 << dmach); \ + HWREG(UDMA_REQMASKSET) = (1 << dmach); \ } /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c index ddcddb3..74a6651 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c @@ -76,60 +76,60 @@ void tiva_clock_init(void) * PLL. */ /* read */ - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); /* modify */ - rcc |= TIVA_RCC_BYPASS; - rcc &= ~TIVA_RCC_USESYSDIV; - rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically * pulls valid PLL configuration data for the appropriate crystal, and * clearing the PWRDN bit powers and enables the PLL and its output. */ /* modify */ - rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS); - rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS)); - rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2); - rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; for(i = 100000; i; i--); /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for * the microcontroller. */ /* modify */ - rcc &= ~TIVA_RCC_SYSDIV_MASK; - rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV; - rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB); - rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ - rcc &= ~TIVA_RCC_BYPASS; - rcc2 &= ~TIVA_RCC2_BYPASS2; + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; rcc |= (TIVA_BYPASS_VALUE << 11); rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; #if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; #endif #if defined(TIVA_UDMA_REQUIRED) diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index ec81806..10936c3 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -45,123 +45,6 @@ * @} */ -/** - * @name RCC register bits definitions - * @{ - */ - -#define TIVA_RCC_MOSCDIS (0x01 << 0) - -#define TIVA_RCC_OSCSRC_MASK (0x03 << 4) -#define TIVA_RCC_OSCSRC_MOSC (0x00 << 4) -#define TIVA_RCC_OSCSRC_PIOSC (0x01 << 4) -#define TIVA_RCC_OSCSRC_PIOSC_4 (0x02 << 4) -#define TIVA_RCC_OSCSRC_LFIOSC (0x03 << 4) - -#define TIVA_RCC_XTAL_MASK (0x1f << 6) -#define TIVA_RCC_XTAL_4000000 (0x06 << 6) -#define TIVA_RCC_XTAL_4096000 (0x07 << 6) -#define TIVA_RCC_XTAL_4915200 (0x08 << 6) -#define TIVA_RCC_XTAL_5000000 (0x09 << 6) -#define TIVA_RCC_XTAL_5120000 (0x0a << 6) -#define TIVA_RCC_XTAL_6000000 (0x0b << 6) -#define TIVA_RCC_XTAL_6144000 (0x0c << 6) -#define TIVA_RCC_XTAL_7372800 (0x0d << 6) -#define TIVA_RCC_XTAL_8000000 (0x0e << 6) -#define TIVA_RCC_XTAL_8192000 (0x0f << 6) -#define TIVA_RCC_XTAL_10000000 (0x10 << 6) -#define TIVA_RCC_XTAL_12000000 (0x11 << 6) -#define TIVA_RCC_XTAL_12288000 (0x12 << 6) -#define TIVA_RCC_XTAL_13560000 (0x13 << 6) -#define TIVA_RCC_XTAL_14318180 (0x14 << 6) -#define TIVA_RCC_XTAL_16000000 (0x15 << 6) -#define TIVA_RCC_XTAL_16384000 (0x16 << 6) -#define TIVA_RCC_XTAL_18000000 (0x17 << 6) -#define TIVA_RCC_XTAL_20000000 (0x18 << 6) -#define TIVA_RCC_XTAL_24000000 (0x19 << 6) -#define TIVA_RCC_XTAL_25000000 (0x1a << 6) - -#define TIVA_RCC_BYPASS (1 << 11) - -#define TIVA_RCC_PWRDN (1 << 13) - -#define TIVA_RCC_PWMDIV_MASK (0x07 << 17) -#define TIVA_RCC_PWMDIV_2 (0x00 << 17) -#define TIVA_RCC_PWMDIV_4 (0x01 << 17) -#define TIVA_RCC_PWMDIV_8 (0x02 << 17) -#define TIVA_RCC_PWMDIV_16 (0x03 << 17) -#define TIVA_RCC_PWMDIV_32 (0x04 << 17) -#define TIVA_RCC_PWMDIV_64 (0x07 << 17) - -#define TIVA_RCC_USEPWMDIV (1 << 20) - -#define TIVA_RCC_USESYSDIV (1 << 22) - -#define TIVA_RCC_SYSDIV_MASK (0x0f << 23) -#define TIVA_RCC_SYSDIV_1 (0x00 << 23) -#define TIVA_RCC_SYSDIV_2 (0x01 << 23) -#define TIVA_RCC_SYSDIV_3 (0x02 << 23) -#define TIVA_RCC_SYSDIV_4 (0x03 << 23) -#define TIVA_RCC_SYSDIV_5 (0x04 << 23) -#define TIVA_RCC_SYSDIV_6 (0x05 << 23) -#define TIVA_RCC_SYSDIV_7 (0x06 << 23) -#define TIVA_RCC_SYSDIV_8 (0x07 << 23) -#define TIVA_RCC_SYSDIV_9 (0x08 << 23) -#define TIVA_RCC_SYSDIV_10 (0x09 << 23) -#define TIVA_RCC_SYSDIV_11 (0x0a << 23) -#define TIVA_RCC_SYSDIV_12 (0x0b << 23) -#define TIVA_RCC_SYSDIV_13 (0x0c << 23) -#define TIVA_RCC_SYSDIV_14 (0x0d << 23) -#define TIVA_RCC_SYSDIV_15 (0x0e << 23) -#define TIVA_RCC_SYSDIV_16 (0x0f << 23) - -#define TIVA_RCC_ACG (1 << 27) - -/** - * @} - */ - -/** - * @name RCC2 register bits definitions - * @{ - */ - -#define TIVA_RCC2_OSCSRC2_MASK (0x07 << 4) -#define TIVA_RCC2_OSCSRC2_MOSC (0x00 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC (0x01 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC_4 (0x02 << 4) -#define TIVA_RCC2_OSCSRC2_LFIOSC (0x03 << 4) -#define TIVA_RCC2_OSCSRC2_32768 (0x07 << 4) - -#define TIVA_RCC2_BYPASS2 (1 << 11) - -#define TIVA_RCC2_PWRDN2 (1 << 13) - -#define TIVA_RCC2_USBPWRDN (1 << 14) - -#define TIVA_RCC2_SYSDIV2LSB (1 << 22) - -#define TIVA_RCC2_SYSDIV2_MASK (0x3f << 23) - -#define TIVA_RCC2_DIV400 (1 << 30) - -#define TIVA_RCC2_USERCC2 (1 << 31) - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) - -/** - * @} - */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -172,7 +55,7 @@ */ #if !defined(TIVA_OSCSRC) -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #endif #if !defined(TIVA_MOSC_ENABLE) @@ -217,56 +100,56 @@ /* * Oscillator-related checks. */ -#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768) +#if !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_32) #error "Invalid value for TIVA_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0abafcc..ae1ea08 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -1,18 +1,58 @@ # List of all the TM4C123x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +ifeq ($(USE_SMART_BUILD),yes) +HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +endif +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD +PLATFORMINC := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h index b380e46..9d41434 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h @@ -42,11 +42,11 @@ #define TIVA_UDMA_ERR_NUMBER 47 /* GPIO units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -63,11 +63,11 @@ #define TIVA_GPIOF_NUMBER 30 #define TIVA_GPIOG_NUMBER 31 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -82,11 +82,11 @@ #define TIVA_GPIOE_NUMBER 4 #define TIVA_GPIOF_NUMBER 30 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -111,8 +111,8 @@ #define TIVA_GPIOK_NUMBER 55 #define TIVA_GPIOL_NUMBER 56 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -157,7 +157,7 @@ #define TIVA_GPIOP6_NUMBER 122 #define TIVA_GPIOP7_NUMBER 123 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -220,23 +220,23 @@ #endif /* GPTM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -291,46 +291,46 @@ #endif /* WDT units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -351,23 +351,23 @@ #endif /* UART units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -388,23 +388,23 @@ #endif /* SPI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_SSI0_HANDLER Vector5C #define TIVA_SSI1_HANDLER VectorC8 #define TIVA_SSI2_HANDLER Vector124 @@ -417,18 +417,18 @@ #endif /* I2C units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -443,11 +443,11 @@ #define TIVA_I2C4_NUMBER 109 #define TIVA_I2C5_NUMBER 110 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -460,28 +460,28 @@ #endif /* CAN units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN0_NUMBER 39 #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN1_HANDLER VectorE0 @@ -490,55 +490,55 @@ #endif /* USB units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) /* No interrupt handler and number.*/ #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_USB0_HANDLER VectorF0 #define TIVA_USB0_NUMBER 44 #endif /* AC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC0_NUMBER 25 #define TIVA_AC1_NUMBER 26 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -549,26 +549,26 @@ #endif /* PWM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -593,25 +593,25 @@ #endif /* QEI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI1_HANLDER VectorD8 diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h index ac7a1d2..88cc376 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h @@ -29,32 +29,32 @@ /* Defined device check. */ /*===========================================================================*/ -#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ - !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ - !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ - !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ - !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ - !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ - !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ - !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ - !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ - !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ - !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ - !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ - !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ - !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ - !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ - !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ - !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ - !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ - !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ - !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ - !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ - !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ - !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ - !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ - !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ - !defined(TM4C123GH5ZXR) +#if !defined(PART_TM4C1230C3PM) && !defined(PART_TM4C1230D5PM) && \ + !defined(PART_TM4C1230E6PM) && !defined(PART_TM4C1230H6PM) && \ + !defined(PART_TM4C1231C3PM) && !defined(PART_TM4C1231D5PM) && \ + !defined(PART_TM4C1231D5PZ) && !defined(PART_TM4C1231E6PM) && \ + !defined(PART_TM4C1231E6PZ) && !defined(PART_TM4C1231H6PGE) && \ + !defined(PART_TM4C1231H6PM) && !defined(PART_TM4C1231H6PZ) && \ + !defined(PART_TM4C1232C3PM) && !defined(PART_TM4C1232D5PM) && \ + !defined(PART_TM4C1232E6PM) && !defined(PART_TM4C1232H6PM) && \ + !defined(PART_TM4C1233C3PM) && !defined(PART_TM4C1233D5PM) && \ + !defined(PART_TM4C1233D5PZ) && !defined(PART_TM4C1233E6PM) && \ + !defined(PART_TM4C1233E6PZ) && !defined(PART_TM4C1233H6PGE) && \ + !defined(PART_TM4C1233H6PM) && !defined(PART_TM4C1233H6PZ) && \ + !defined(PART_TM4C1236D5PM) && !defined(PART_TM4C1236E6PM) && \ + !defined(PART_TM4C1236H6PM) && !defined(PART_TM4C1237D5PM) && \ + !defined(PART_TM4C1237D5PZ) && !defined(PART_TM4C1237E6PM) && \ + !defined(PART_TM4C1237E6PZ) && !defined(PART_TM4C1237H6PGE) && \ + !defined(PART_TM4C1237H6PM) && !defined(PART_TM4C1237H6PZ) && \ + !defined(PART_TM4C123AE6PM) && !defined(PART_TM4C123AH6PM) && \ + !defined(PART_TM4C123BE6PM) && !defined(PART_TM4C123BE6PZ) && \ + !defined(PART_TM4C123BH6PGE) && !defined(PART_TM4C123BH6PM) && \ + !defined(PART_TM4C123BH6PZ) && !defined(PART_TM4C123BH6ZRB) && \ + !defined(PART_TM4C123FE6PM) && !defined(PART_TM4C123FH6PM) && \ + !defined(PART_TM4C123GE6PM) && !defined(PART_TM4C123GE6PZ) && \ + !defined(PART_TM4C123GH6PGE) && !defined(PART_TM4C123GH6PM) && \ + !defined(PART_TM4C123GH6PZ) && !defined(PART_TM4C123GH6ZRB) && \ + !defined(PART_TM4C123GH5ZXR) #error "No valid device defined." #endif @@ -75,11 +75,11 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -100,11 +100,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 56 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -125,11 +125,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 48 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -150,8 +150,8 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 88 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -172,7 +172,7 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 112 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -195,23 +195,23 @@ #endif /* GPTM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -229,67 +229,67 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -301,23 +301,23 @@ #endif /* SPI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_SSI0 TRUE #define TIVA_HAS_SSI1 TRUE #define TIVA_HAS_SSI2 TRUE @@ -325,18 +325,18 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -348,11 +348,11 @@ #define TIVA_HAS_I2C8 FALSE #define TIVA_HAS_I2C9 FALSE #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -366,129 +366,129 @@ #endif /* CAN attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* USB attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) #define TIVA_HAS_USB0 FALSE #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_USB0 TRUE #endif /* AC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 FALSE #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_PWM0 FALSE #define TIVA_HAS_PWM1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 TRUE #endif /* QEI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) #define TIVA_HAS_QEI0 FALSE #define TIVA_HAS_QEI1 FALSE #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 TRUE #endif diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c index 60d6763..e12ab5e 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c @@ -76,8 +76,8 @@ void tiva_clock_init(void) /* * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register. */ - moscctl = SYSCTL->MOSCCTL; - moscctl &= ~MOSCCTL_NOXTAL; + moscctl = HWREG(SYSCTL_MOSCCTL); + moscctl &= ~SYSCTL_MOSCCTL_NOXTAL; /* * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required, @@ -85,18 +85,18 @@ void tiva_clock_init(void) * (RIS), indicating MOSC crystal mode is ready. */ #if TIVA_MOSC_SINGLE_ENDED - SYSCTL->MOSCCTL = moscctl; + HWREG(SYSCTL_MOSCCTL) = moscctl; #else - moscctl &= ~MOSCCTL_PWRDN; - SYSCTL->MOSCCTL = moscctl; + moscctl &= ~SYSCTL_MOSCCTL_PWRDN; + HWREG(SYSCTL_MOSCCTL) = moscctl; - while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)); + while (!(HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS)); #endif /* * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); rsclkcfg |= TIVA_RSCLKCFG_OSCSRC; @@ -109,44 +109,42 @@ void tiva_clock_init(void) * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to * the configure the desired VCO frequency setting. */ - SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1 - SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR; + HWREG(SYSCTL_PLLFREQ1) = (0x04 << 0); // 5 - 1 + HWREG(SYSCTL_PLLFREQ0) = (0x60 << 0) | SYSCTL_PLLFREQ0_PLLPWR; /* * 7. Write the MEMTIM0 register to correspond to the new system clock setting. */ - SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1); + HWREG(SYSCTL_MEMTIM0) = (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1); /* * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point * (or that a timeout period has passed and lock has failed, in which case an error condition exists * and this sequence is abandoned and error processing is initiated). */ - while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK); + while (!HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK); /* * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU * bit. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); - rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); + rsclkcfg |= (SYSCTL_RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20)); - rsclkcfg |= RSCLKCFG_MEMTIMU; + rsclkcfg |= SYSCTL_RSCLKCFG_MEMTIMU; // set new configuration - SYSCTL->RSCLKCFG = rsclkcfg; + HWREG(SYSCTL_RSCLKCFG) = rsclkcfg; #if HAL_USE_PWM #if TIVA_PWM_USE_PWM0 - PWM0->CC = TIVA_PWM_FIELDS; + HWREG(PWM0_CC) = TIVA_PWM_FIELDS; #endif #endif } -/** - * @} - */ +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index e5c667d..3768957 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -38,170 +38,8 @@ * @name Platform identification * @{ */ - #define PLATFORM_NAME "Tiva C Series TM4C129x" - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) - -/** - * @} - */ - -/** - * @name MOSCCTL register bits definitions - * @{ - */ - -#define MOSCCTL_CVAL (1 << 0) -#define MOSCCTL_MOSCIM (1 << 1) -#define MOSCCTL_NOXTAL (1 << 2) -#define MOSCCTL_PWRDN (1 << 3) -#define MOSCCTL_OSCRNG (1 << 4) - -/** - * @} - */ - -/** - * @name RSCLKCFG register bits definitions - * @{ - */ - -#define RSCLKCFG_PSYSDIV_bm (0xfffff << 0) -#define RSCLKCFG_OSYSDIV_bm (0xfffff << 10 - -#define RSCLKCFG_OSCSRC_bm (0xff << 20) -#define RSCLKCFG_OSCSRC_PIOSC (0 << 20) -#define RSCLKCFG_OSCSRC_LFIOSC (0x02 << 20) -#define RSCLKCFG_OSCSRC_MOSC (0x03 << 20) -#define RSCLKCFG_OSCSRC_RTCOSC (0x04 << 20) - -#define RSCLKCFG_PLLSRC_bm (0xff << 24) -#define RSCLKCFG_PLLSRC_PIOSC (0 << 24) -#define RSCLKCFG_PLLSRC_MOSC (0x03 << 24) - -#define RSCLKCFG_USEPLL (1 << 28) - -#define RSCLKCFG_ACG (1 << 29) - -#define RSCLKCFG_NEWFREQ (1 << 30) - -#define RSCLKCFG_MEMTIMU (1 << 31) - -/** - * @} - */ - -/** - * @name PLLFREQ0 register bits definitions - * The PLL frequency can be calculated using the following equation: - * fVCO = (fIN * MDIV) - * where - * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1) - * MDIV = MINT + (MFRAC / 1024) - * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC - * should be programmed to 0x0. - * @{ - */ - -#define PLLFREQ0_MINT_bm (0xfffff << 0) -#define PLLFREQ0_MFRAC_bm (0xfffff << 10) -#define PLLFREQ0_PLLPWR (1 << 23) - -/** - * @} - */ - -/** - * @name PLLFREQ1 register bits definitions - * @{ - */ - -#define PLLFREQ1_N_bm (0x7ff << 0) -#define PLLFREQ1_Q_bm (0x7ff << 8) - -/** - * @} - */ - -/** - * @name MEMTIM0 register bits definitions - * @{ - */ - -#define MEMTIM0_FWS_bm (0xff << 0) -#define MEMTIM0_FWS_0 (0x00 << 0) -#define MEMTIM0_FWS_1 (0x01 << 0) -#define MEMTIM0_FWS_2 (0x02 << 0) -#define MEMTIM0_FWS_3 (0x03 << 0) -#define MEMTIM0_FWS_4 (0x04 << 0) -#define MEMTIM0_FWS_5 (0x05 << 0) -#define MEMTIM0_FWS_6 (0x06 << 0) -#define MEMTIM0_FWS_7 (0x07 << 0) - -#define MEMTIM0_FBCE (1 << 5) - -#define MEMTIM0_FBCHT_bm (0xff << 6) -#define MEMTIM0_FBCHT_0_5 (0x00 << 6) -#define MEMTIM0_FBCHT_1 (0x01 << 6) -#define MEMTIM0_FBCHT_1_5 (0x02 << 6) -#define MEMTIM0_FBCHT_2 (0x03 << 6) -#define MEMTIM0_FBCHT_2_5 (0x04 << 6) -#define MEMTIM0_FBCHT_3 (0x05 << 6) -#define MEMTIM0_FBCHT_3_5 (0x06 << 6) -#define MEMTIM0_FBCHT_4 (0x07 << 6) -#define MEMTIM0_FBCHT_4_5 (0x08 << 6) - -#define MEMTIM0_EWS_bm (0xff << 16) -#define MEMTIM0_EWS_0 (0x00 << 16) -#define MEMTIM0_EWS_1 (0x01 << 16) -#define MEMTIM0_EWS_2 (0x02 << 16) -#define MEMTIM0_EWS_3 (0x03 << 16) -#define MEMTIM0_EWS_4 (0x04 << 16) -#define MEMTIM0_EWS_5 (0x05 << 16) -#define MEMTIM0_EWS_6 (0x06 << 16) -#define MEMTIM0_EWS_7 (0x07 << 16) - -#define MEMTIM0_EBCE (1 << 21) - -#define MEMTIM0_EBCHT_bm (0xff << 22) -#define MEMTIM0_EBCHT_0_5 (0x00 << 22) -#define MEMTIM0_EBCHT_1 (0x01 << 22) -#define MEMTIM0_EBCHT_1_5 (0x02 << 22) -#define MEMTIM0_EBCHT_2 (0x03 << 22) -#define MEMTIM0_EBCHT_2_5 (0x04 << 22) -#define MEMTIM0_EBCHT_3 (0x05 << 22) -#define MEMTIM0_EBCHT_3_5 (0x06 << 22) -#define MEMTIM0_EBCHT_4 (0x07 << 22) -#define MEMTIM0_EBCHT_4_5 (0x08 << 22) - -// XXX: what is this? -#define MEMTIM0_MB1 0x00100010 // MB1 = Must be one - -/** - * @} - */ - -/** - * @name PLLSTAT register bits definitions - * @{ - */ - -#define PLLSTAT_LOCK (1 << 0) - -/** - * @} - */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -212,7 +50,7 @@ #endif #if !defined(TIVA_RSCLKCFG_OSCSRC) -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC +#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC #endif /*===========================================================================*/ @@ -229,55 +67,55 @@ /* * Oscillator-related checks. */ -#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC) +#if !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_PIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_LFIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_MOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_RTC) #error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index b8363f3..18ed48d 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -1,14 +1,63 @@ # List of all the TM4C129x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ +ifeq ($(USE_SMART_BUILD),yes) +HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +endif +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif +ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c +endif +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ +PLATFORMINC := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h index 255bfd6..330d5c6 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h @@ -35,9 +35,9 @@ */ /* GPIO units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -98,10 +98,10 @@ #define TIVA_GPIOQ6_NUMBER 90 #define TIVA_GPIOQ7_NUMBER 91 #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -170,85 +170,85 @@ #endif /* EPI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_EPI0_HANDLER Vector108 #define TIVA_EPI0_NUMBER 50 #endif /* CRC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* CRC has no interrupts.*/ #endif /* AES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_AES_HANDLER Vector1BC #define TIVA_AES_NUMBER 95 #endif /* DES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_DES_HANDLER Vector1C0 #define TIVA_DES_NUMBER 51 #endif /* SHA/MD5 Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_SHA_MD5_HANDLER Vector1B8 #define TIVA_SHA_MD5_NUMBER 94 #endif /* GPT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -285,26 +285,26 @@ #endif /* WDT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -325,13 +325,13 @@ #endif /* UART units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -352,13 +352,13 @@ #endif /* QSSI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QSSI0_HANDLER Vector5C #define TIVA_QSSI1_HANDLER VectorC8 #define TIVA_QSSI2_HANDLER Vector118 @@ -371,13 +371,13 @@ #endif /* I2C units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector134 @@ -402,28 +402,28 @@ #endif /* 1-Wire Master units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_1WIRE_HANDLER Vector1E4 #define TIVA_1WIRE_NUMBER 105 #endif /* CAN units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_CAN0_HANDLER VectorD8 #define TIVA_CAN1_HANDLER VectorDC @@ -432,69 +432,69 @@ #endif /* Ethernet MAC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_MAC_HANDLER VectorE0 #define TIVA_MAC_NUMBER 40 #endif /* Ethernet PHY units.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* no interrupts.*/ #endif /* USB units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_USB0_HANDLER VectorE8 #define TIVA_USB0_NUMBER 42 #endif /* LCD units.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_LCD_HANDLER Vector1C4 #define TIVA_LCD_NUMBER 97 #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) /* no interrupts.*/ #endif /* AC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -505,13 +505,13 @@ #endif /* PWM units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -526,13 +526,13 @@ #endif /* QEI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI0_NUMBER 13 diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h index 5815351..99e4f81 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h @@ -35,9 +35,9 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -57,10 +57,10 @@ #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -82,77 +82,77 @@ #endif /* EPI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_EPI0 TRUE #endif /* CRC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CRC0 TRUE #endif /* AES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_AES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AES TRUE #endif /* DES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_DES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_DES TRUE #endif /* SHA/MD5 Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_SHA_MD5 FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_SHA_MD5 TRUE #endif /* GPT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -170,37 +170,37 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -212,13 +212,13 @@ #endif /* QSSI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QSSI0 TRUE #define TIVA_HAS_QSSI1 TRUE #define TIVA_HAS_QSSI2 TRUE @@ -226,13 +226,13 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -246,113 +246,113 @@ #endif /* 1-Wire Master attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_1WIRE TRUE #endif /* CAN attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* Ethernet MAC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) #define TIVA_HAS_ETHERNET_MAC FALSE #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_MAC TRUE #endif /* Ethernet PHY attributes.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) #define TIVA_HAS_ETHERNET_PHY FALSE #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_PHY TRUE #endif /* USB attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_USB0 TRUE #endif /* LCD attributes.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_LCD TRUE #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) #define TIVA_HAS_LCD FALSE #endif /* AC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 FALSE #endif /* QEI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 FALSE #endif |