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-rw-r--r--os/hal/boards/MICROBIT/board.c91
-rw-r--r--os/hal/boards/MICROBIT/board.h147
-rw-r--r--os/hal/boards/MICROBIT/board.mk5
-rwxr-xr-x[-rw-r--r--]os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c12
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h3
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c16
-rw-r--r--os/hal/src/hal_onewire.c4
-rw-r--r--os/hal/src/usbh/hal_usbh_debug.c22
-rw-r--r--os/hal/src/usbh/hal_usbh_hub.c1
9 files changed, 274 insertions, 27 deletions
diff --git a/os/hal/boards/MICROBIT/board.c b/os/hal/boards/MICROBIT/board.c
new file mode 100644
index 0000000..12f78e2
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.c
@@ -0,0 +1,91 @@
+/*
+ Copyright (C) 2017 Stéphane D'Alu
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/* RAM Banks
+ * (Values are defined in Nordic gcc_startup_nrf51.s)
+ */
+#define NRF_POWER_RAMON_ADDRESS 0x40000524
+#define NRF_POWER_RAMONB_ADDRESS 0x40000554
+#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .pads = {
+ PAL_MODE_OUTPUT_OPENDRAIN, /* P0.0 : SCL P19 */
+ PAL_MODE_UNCONNECTED, /* P0.1 : PAD1 P2 */
+ PAL_MODE_UNCONNECTED, /* P0.2 : PAD2 P1 */
+ PAL_MODE_UNCONNECTED, /* P0.3 : PAD3 P0 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.4 : COL1 P3 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : COL2 P4 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : COL3 P10 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.7 : COL4 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.8 : COL5 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.9 : COL6 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.10: COL7 P9 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.11: COL8 P7 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.12: COL9 P6 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.13: ROW1 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.14: ROW2 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.15: ROW3 */
+ PAL_MODE_UNCONNECTED, /* P0.16 P16 */
+ PAL_MODE_INPUT, /* P0.17: BTN_A P5 */
+ PAL_MODE_UNCONNECTED, /* P0.18 P8 */
+ PAL_MODE_INPUT, /* P0.19: BTN_RST */
+ PAL_MODE_UNCONNECTED, /* P0.20 P12 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: SPI_MOSI P15 */
+ PAL_MODE_INPUT_PULLUP, /* P0.22: SPI_MISO P14 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.23: SPI_SCK P13 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: UART_TX */
+ PAL_MODE_INPUT_PULLUP, /* P0.25: UART_RX */
+ PAL_MODE_INPUT, /* P0.26: BTN_B P11 */
+ PAL_MODE_INPUT, /* P0.27: ACC_INT2 */
+ PAL_MODE_INPUT, /* P0.28: ACC_INT1 */
+ PAL_MODE_INPUT, /* P0.29: MAG_INT1 */
+ PAL_MODE_OUTPUT_OPENDRAIN, /* P0.30: SDA P20 */
+ PAL_MODE_UNCONNECTED, /* P0.31 */
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ * DATA segments initialization.
+ */
+void __early_init(void)
+{
+ /* Make sure ALL RAM banks are powered on */
+ *(uint32_t *)NRF_POWER_RAMON_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+ *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+}
+
+/**
+ * @brief Late initialization code.
+ * @note This initialization is performed after BSS and DATA segments
+ * initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/os/hal/boards/MICROBIT/board.h b/os/hal/boards/MICROBIT/board.h
new file mode 100644
index 0000000..7798634
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.h
@@ -0,0 +1,147 @@
+/*
+ Copyright (C) 2016 Stephane D'Alu
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * See: https://www.microbit.co.uk/device/pins
+ * https://lancaster-university.github.io/microbit-docs/ubit/display/
+ */
+
+/* Board identifier. */
+#define BOARD_MICROBIT
+#define BOARD_NAME "micro:bit"
+
+/* Board oscillators-related settings. */
+#define NRF51_XTAL_VALUE 16000000
+#define NRF51_LFCLK_SOURCE 0 /* RC oscillator */
+
+/*
+ * IO pins assignments.
+ */
+#define IOPORT1_P0 3U
+#define IOPORT1_P1 2U
+#define IOPORT1_P2 1U
+#define IOPORT1_P3 4U
+#define IOPORT1_P4 5U
+#define IOPORT1_P5 17U
+#define IOPORT1_P6 12U
+#define IOPORT1_P7 11U
+#define IOPORT1_P8 18U
+#define IOPORT1_P9 10U
+#define IOPORT1_P10 6U
+#define IOPORT1_P11 26U
+#define IOPORT1_P12 20U
+#define IOPORT1_P13 23U
+#define IOPORT1_P14 22U
+#define IOPORT1_P15 21U
+#define IOPORT1_P16 16U
+#define IOPORT1_P19 0U
+#define IOPORT1_P20 30U
+#define IOPORT1_BTN_A 17U
+#define IOPORT1_BTN_B 26U
+#define IOPORT1_BTN_RST 19U
+#define IOPORT1_LED_COL_1 4U
+#define IOPORT1_LED_COL_2 5U
+#define IOPORT1_LED_COL_3 6U
+#define IOPORT1_LED_COL_4 7U
+#define IOPORT1_LED_COL_5 8U
+#define IOPORT1_LED_COL_6 9U
+#define IOPORT1_LED_COL_7 10U
+#define IOPORT1_LED_COL_8 11U
+#define IOPORT1_LED_COL_9 12U
+#define IOPORT1_LED_ROW_1 13U
+#define IOPORT1_LED_ROW_2 14U
+#define IOPORT1_LED_ROW_3 15U
+#define IOPORT1_PAD_1 1U
+#define IOPORT1_PAD_2 2U
+#define IOPORT1_PAD_3 3U
+#define IOPORT1_SPI_MOSI 21U
+#define IOPORT1_SPI_MISO 22U
+#define IOPORT1_SPI_SCK 23U
+#define IOPORT1_I2C_SCL 0U
+#define IOPORT1_I2C_SDA 30U
+#define IOPORT1_UART_TX 24U
+#define IOPORT1_UART_RX 25U
+#define IOPORT1_ACC_INT1 28U
+#define IOPORT1_ACC_INT2 27U
+#define IOPORT1_MAG_INT1 29U
+
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_P0 PAL_LINE(IOPORT1, IOPORT1_P0)
+#define LINE_P1 PAL_LINE(IOPORT1, IOPORT1_P1)
+#define LINE_P2 PAL_LINE(IOPORT1, IOPORT1_P2)
+#define LINE_P3 PAL_LINE(IOPORT1, IOPORT1_P3)
+#define LINE_P4 PAL_LINE(IOPORT1, IOPORT1_P4)
+#define LINE_P5 PAL_LINE(IOPORT1, IOPORT1_P5)
+#define LINE_P6 PAL_LINE(IOPORT1, IOPORT1_P6)
+#define LINE_P7 PAL_LINE(IOPORT1, IOPORT1_P7)
+#define LINE_P8 PAL_LINE(IOPORT1, IOPORT1_P8)
+#define LINE_P9 PAL_LINE(IOPORT1, IOPORT1_P9)
+#define LINE_P10 PAL_LINE(IOPORT1, IOPORT1_P10)
+#define LINE_P11 PAL_LINE(IOPORT1, IOPORT1_P11)
+#define LINE_P12 PAL_LINE(IOPORT1, IOPORT1_P12)
+#define LINE_P13 PAL_LINE(IOPORT1, IOPORT1_P13)
+#define LINE_P14 PAL_LINE(IOPORT1, IOPORT1_P14)
+#define LINE_P15 PAL_LINE(IOPORT1, IOPORT1_P15)
+#define LINE_P16 PAL_LINE(IOPORT1, IOPORT1_P16)
+#define LINE_P19 PAL_LINE(IOPORT1, IOPORT1_P19)
+#define LINE_P20 PAL_LINE(IOPORT1, IOPORT1_P20)
+#define LINE_BTN_A PAL_LINE(IOPORT1, IOPORT1_BTN_A)
+#define LINE_BTN_B PAL_LINE(IOPORT1, IOPORT1_BTN_B)
+#define LINE_BTN_RST PAL_LINE(IOPORT1, IOPORT1_BTN_RST)
+#define LINE_LED_COL_1 PAL_LINE(IOPORT1, IOPORT1_LED_COL_1)
+#define LINE_LED_COL_2 PAL_LINE(IOPORT1, IOPORT1_LED_COL_2)
+#define LINE_LED_COL_3 PAL_LINE(IOPORT1, IOPORT1_LED_COL_3)
+#define LINE_LED_COL_4 PAL_LINE(IOPORT1, IOPORT1_LED_COL_4)
+#define LINE_LED_COL_5 PAL_LINE(IOPORT1, IOPORT1_LED_COL_5)
+#define LINE_LED_COL_6 PAL_LINE(IOPORT1, IOPORT1_LED_COL_6)
+#define LINE_LED_COL_7 PAL_LINE(IOPORT1, IOPORT1_LED_COL_7)
+#define LINE_LED_COL_8 PAL_LINE(IOPORT1, IOPORT1_LED_COL_8)
+#define LINE_LED_COL_9 PAL_LINE(IOPORT1, IOPORT1_LED_COL_9)
+#define LINE_LED_ROW_1 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1)
+#define LINE_LED_ROW_2 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2)
+#define LINE_LED_ROW_3 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3)
+#define LINE_PAD_1 PAL_LINE(IOPORT1, IOPORT1_PAD_1)
+#define LINE_PAD_2 PAL_LINE(IOPORT1, IOPORT1_PAD_2)
+#define LINE_PAD_3 PAL_LINE(IOPORT1, IOPORT1_PAD_3)
+#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_ACC_INT1 PAL_LINE(IOPORT1, IOPORT1_ACC_INT1)
+#define LINE_ACC_INT2 PAL_LINE(IOPORT1, IOPORT1_ACC_INT2)
+#define LINE_MAG_INT1 PAL_LINE(IOPORT1, IOPORT1_MAG_INT1)
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/MICROBIT/board.mk b/os/hal/boards/MICROBIT/board.mk
new file mode 100644
index 0000000..3595b1a
--- /dev/null
+++ b/os/hal/boards/MICROBIT/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
index f8178f1..a2cf026 100644..100755
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
@@ -185,15 +185,15 @@ void crc_lld_start(CRCDriver *crcp) {
crcp->crc->CR |= CRC_CR_REV_OUT;
}
#else
- osalDbgAssert(crcp->config->initial_val != default_config.initial_val,
+ osalDbgAssert(crcp->config->initial_val == default_config.initial_val,
"hardware doesn't support programmable initial value");
- osalDbgAssert(crcp->config->poly_size != default_config.poly_size,
+ osalDbgAssert(crcp->config->poly_size == default_config.poly_size,
"hardware doesn't support programmable polynomial size");
- osalDbgAssert(crcp->config->poly != default_config.poly,
+ osalDbgAssert(crcp->config->poly == default_config.poly,
"hardware doesn't support programmable polynomial");
- osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data,
+ osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data,
"hardware doesn't support reflect of input data");
- osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder,
+ osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder,
"hardware doesn't support reflect of output remainder");
#endif
@@ -299,7 +299,7 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
n--;
}
#else
- osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses");
+ osalDbgAssert(n == 0, "STM32 CRC Unit only supports WORD accesses");
#endif
#endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index f0d4c65..f4837f5 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -230,6 +230,9 @@ typedef struct {
defined(STM32F7))
#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
#endif
+#if (defined(STM32F7))
+#define FSMC_BCR_WFDIS ((uint32_t)1 << 21)
+#endif
/*===========================================================================*/
/* Driver pre-compile time settings. */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index ffc4992..6138481 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -194,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) {
#endif
}
/* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0;
qeip->tim->PSC = 0;
qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
+ qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else {
/* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
}
if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@@ -230,7 +230,7 @@ void qei_lld_start(QEIDriver *qeip) {
void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
@@ -275,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) {
*/
void qei_lld_enable(QEIDriver *qeip) {
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
}
/**
@@ -287,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) {
*/
void qei_lld_disable(QEIDriver *qeip) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
}
#endif /* HAL_USE_QEI */
diff --git a/os/hal/src/hal_onewire.c b/os/hal/src/hal_onewire.c
index 4e80807..06e63e6 100644
--- a/os/hal/src/hal_onewire.c
+++ b/os/hal/src/hal_onewire.c
@@ -679,7 +679,7 @@ bool onewireReset(onewireDriver *owp) {
}
/**
- * @brief Read some bites from slave device.
+ * @brief Read some bytes from slave device.
*
* @param[in] owp pointer to the @p onewireDriver object
* @param[out] rxbuf pointer to the buffer for read data
@@ -727,7 +727,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) {
}
/**
- * @brief Read some bites from slave device.
+ * @brief Write some bytes to slave device.
*
* @param[in] owp pointer to the @p onewireDriver object
* @param[in] txbuf pointer to the buffer with data to be written
diff --git a/os/hal/src/usbh/hal_usbh_debug.c b/os/hal/src/usbh/hal_usbh_debug.c
index 9f17189..51ca166 100644
--- a/os/hal/src/usbh/hal_usbh_debug.c
+++ b/os/hal/src/usbh/hal_usbh_debug.c
@@ -111,7 +111,7 @@ static char *ftoa(char *p, double num, unsigned long precision, bool dot) {
static inline void _put(char c) {
input_queue_t *iqp = &USBH_DEBUG_USBHD.iq;
- if (chIQIsFullI(iqp))
+ if (iqIsFullI(iqp))
return;
iqp->q_counter++;
@@ -407,8 +407,8 @@ void usbDbgReset(void) {
const char *msg = "\r\n\r\n==== DEBUG OUTPUT RESET ====\r\n";
syssts_t sts = chSysGetStatusAndLockX();
- chIQResetI(&USBH_DEBUG_USBHD.iq);
- chOQResetI(&USBH_DEBUG_SD.oqueue);
+ iqResetI(&USBH_DEBUG_USBHD.iq);
+ oqResetI(&USBH_DEBUG_SD.oqueue);
while (*msg) {
*USBH_DEBUG_SD.oqueue.q_wrptr++ = *msg++;
USBH_DEBUG_SD.oqueue.q_counter--;
@@ -478,7 +478,7 @@ static void usb_debug_thread(void *p) {
chRegSetThreadName("USBH_DBG");
while (true) {
- msg_t c = chIQGet(&host->iq);
+ msg_t c = iqGet(&host->iq);
if (c < 0) goto reset;
if (state == 0) {
@@ -491,16 +491,16 @@ static void usb_debug_thread(void *p) {
uint32_t hfnum;
hfir = c;
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
hfir |= c << 8;
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
hfnum = c;
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
hfnum |= c << 8;
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
hfnum |= c << 16;
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
hfnum |= c << 24;
uint32_t f = hfnum & 0xffff;
@@ -508,7 +508,7 @@ static void usb_debug_thread(void *p) {
chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d ", f, p);
while (true) {
- c = chIQGet(&host->iq); if (c < 0) goto reset;
+ c = iqGet(&host->iq); if (c < 0) goto reset;
if (!c) {
sdPut(&USBH_DEBUG_SD, '\r');
sdPut(&USBH_DEBUG_SD, '\n');
@@ -528,7 +528,7 @@ reset:
void usbDbgInit(USBHDriver *host) {
if (host != &USBH_DEBUG_USBHD)
return;
- chIQObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0);
+ iqObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0);
chThdCreateStatic(USBH_DEBUG_USBHD.waDebug, sizeof(USBH_DEBUG_USBHD.waDebug), NORMALPRIO, usb_debug_thread, &USBH_DEBUG_USBHD);
}
#endif
diff --git a/os/hal/src/usbh/hal_usbh_hub.c b/os/hal/src/usbh/hal_usbh_hub.c
index 7fdcef1..56257b2 100644
--- a/os/hal/src/usbh/hal_usbh_hub.c
+++ b/os/hal/src/usbh/hal_usbh_hub.c
@@ -15,6 +15,7 @@
limitations under the License.
*/
+#include <string.h>
#include "hal.h"
#include "hal_usbh.h"
#include "usbh/internal.h"
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 19:02:47 +0000