4 files changed, 9 insertions, 13 deletions
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c
index 75643d6..977eba0 100644
--- a/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c
+++ b/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c
@@ -150,7 +150,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->thread != NULL) {
       tp = dma2dp->thread;
       dma2dp->thread = NULL;
-      tp->p_u.rdymsg = MSG_OK;
+      tp->u.rdymsg = MSG_OK;
       chSchReadyI(tp);
     }
   #endif  /* DMA2D_USE_WAIT */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
index 32fe468..b37c026 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
@@ -291,10 +291,12 @@ void nand_lld_start(NANDDriver *nandp) {
                           (void *)nandp);
     osalDbgAssert(!b, "stream already allocated");
     nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
-                        STM32_DMA_CR_PSIZE_BYTE     | STM32_DMA_CR_MSIZE_BYTE |
-                        STM32_DMA_CR_DMEIE          | STM32_DMA_CR_TEIE |
-                        STM32_DMA_CR_TCIE;
+                     STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
+                     STM32_DMA_CR_PSIZE_BYTE |
+                     STM32_DMA_CR_MSIZE_BYTE |
+                     STM32_DMA_CR_DMEIE |
+                     STM32_DMA_CR_TEIE |
+                     STM32_DMA_CR_TCIE;
     /* dmaStreamSetFIFO(nandp->dma,
                     STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */
     nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN;
@@ -392,7 +394,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
   nand_lld_write_addr(nandp, addr, addrlen);
 
   /* Now start DMA transfer to NAND buffer and put thread in sleep state.
-     Tread will we woken up from ready ISR. */
+     Tread will be woken up from ready ISR. */
   nandp->state = NAND_DMA_TX;
   osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0,
           "State machine broken. ECCEN must be previously disabled.");
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
index 23e8e51..c891fcc 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
@@ -124,12 +124,6 @@
 #error "External interrupt controller must be enabled to use this feature"
 #endif
 
-#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) &&             \
-    !STM32_DMA_IS_VALID_ID(STM32_NAND_DMA_STREAM,                           \
-                           STM32_FSMC_DMA_MSK)
-#error "invalid DMA stream associated to NAND"
-#endif
-
 #if !defined(STM32_DMA_REQUIRED)
 #define STM32_DMA_REQUIRED
 #endif
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c
index 72c9d06..7037a7c 100644
--- a/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c
+++ b/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c
@@ -173,7 +173,7 @@ OSAL_IRQ_HANDLER(STM32_LTDC_EV_HANDLER) {
     if (ltdcp->thread != NULL) {
       tp = ltdcp->thread;
       ltdcp->thread = NULL;
-      tp->p_u.rdymsg = MSG_OK;
+      tp->u.rdymsg = MSG_OK;
       chSchReadyI(tp);
     }
 #endif  /* LTDC_USE_WAIT */