diff options
Diffstat (limited to 'os')
37 files changed, 3880 insertions, 5615 deletions
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c index 1e10241..e6eeed8 100644 --- a/os/hal/ports/KINETIS/K20x/hal_lld.c +++ b/os/hal/ports/KINETIS/K20x/hal_lld.c @@ -39,7 +39,7 @@ #ifdef __CC_ARM
__attribute__ ((section(".ARM.__at_0x400")))
#else
-__attribute__ ((used, section(".cfmconfig")))
+__attribute__ ((used,section(".cfmconfig")))
#endif
const uint8_t _cfm[0x10] = {
0xFF, /* NV_BACKKEY3: KEY=0xFF */
@@ -84,7 +84,7 @@ void hal_lld_init(void) { }
/**
- * @brief MK20D5 clock initialization.
+ * @brief K20x clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
@@ -93,16 +93,9 @@ void hal_lld_init(void) { *
* @special
*/
-void mk20d50_clock_init(void) {
+void k20x_clock_init(void) {
#if !KINETIS_NO_INIT
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
- uint32_t ratio, frdiv;
- uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
- int ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
- int i;
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
-
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
@@ -115,14 +108,24 @@ void mk20d50_clock_init(void) { SIM_SCGC5_PORTE;
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
/* Configure FEI mode */
MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
(KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI */
+ /* Set clock dividers */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
@@ -132,8 +135,13 @@ void mk20d50_clock_init(void) { * Start in FEI mode
*/
- /* Disable capacitors for crystal */
- OSC->CR = 0;
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* TODO: need to add more flexible calculation, specially regarding
* divisors which may not be available depending on the XTAL
@@ -141,13 +149,13 @@ void mk20d50_clock_init(void) { */
/* Enable OSC, low power mode */
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
- if (KINETIS_XTAL_FREQUENCY > 8000000)
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
MCG->C2 |= MCG_C2_RANGE0(2);
else
MCG->C2 |= MCG_C2_RANGE0(1);
frdiv = 7;
- ratio = KINETIS_XTAL_FREQUENCY / 31250;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
for (i = 0; i < ratio_quantity; ++i) {
if (ratio == ratios[i]) {
frdiv = i;
@@ -170,22 +178,42 @@ void mk20d50_clock_init(void) { /*
* Now in FBE mode
*/
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /*
+ * Config PLL input for 2 MHz
+ * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+ */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
- /* Config PLL input for 2 MHz */
- MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY / 2000000) - 1);
-
- /* Config PLL for 96 MHz output */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /*
+ * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+ */
+ for(i = 24; i < 56; i++)
+ {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+ {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
- /* Wait for PLL to start using crystal as its input */
- while (!(MCG->S & MCG_S_PLLST));
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
- /* Wait for PLL to lock */
- while (!(MCG->S & MCG_S_LOCK0));
+ /* Wait for PLL to start using crystal as its input, and to lock */
+ while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
/*
* Now in PBE mode
*/
+ /* Set the PLL dividers for the different clocks */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
@@ -196,7 +224,9 @@ void mk20d50_clock_init(void) { /*
* Now in PEE mode
*/
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
#endif /* !KINETIS_NO_INIT */
}
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.h b/os/hal/ports/KINETIS/K20x/hal_lld.h index 3544797..31364cf 100644 --- a/os/hal/ports/KINETIS/K20x/hal_lld.h +++ b/os/hal/ports/KINETIS/K20x/hal_lld.h @@ -15,8 +15,8 @@ */
/**
- * @file KL2x/hal_lld.h
- * @brief Kinetis KL2x HAL subsystem low level driver header.
+ * @file K20x/hal_lld.h
+ * @brief Kinetis K20x HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
@@ -25,7 +25,6 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-#include "mk20d5.h"
#include "kinetis_registry.h"
/*===========================================================================*/
@@ -45,16 +44,6 @@ /** @} */
/**
- * @brief Maximum system and core clock (f_SYS) frequency.
- */
-#define KINETIS_SYSCLK_MAX 48000000
-
-/**
- * @brief Maximum bus clock (f_BUS) frequency.
- */
-#define KINETIS_BUSCLK_MAX 24000000
-
-/**
* @name Internal clock sources
* @{
*/
@@ -94,24 +83,56 @@ #endif
/**
- * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
- * @note The allowed range is 1...16.
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system clocks (OUTDIV1).
+ * @note The allowed range is 1..16
* @note The default value is calculated for a 48 MHz system clock
* from a 96 MHz PLL output.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV1 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for bus clock (OUTDIV2).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz bus clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV2 2
+ #endif
#endif
/**
- * @brief Additional clock divider bus/flash clocks (OUTDIV4).
- * @note The allowed range is 1...8.
- * @note This divider is on top of the OUTDIV1 divider.
- * @note The default value is calculated for 24 MHz bus/flash clocks
- * from a 96 MHz PLL output and 48 MHz core/system clock.
+ * @brief Clock divider for flash clock (OUTDIV4).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 24 MHz flash clock
+ * from a 96 MHz PLL output
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV4 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 4
+ #endif
#endif
/**
@@ -140,32 +161,21 @@ * @brief MCU system/core clock frequency.
*/
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
#endif
/**
- * @brief MCU bus/flash clock frequency.
+ * @brief MCU bus clock frequency.
*/
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
#endif
/**
- * @brief UART0 clock frequency.
- * @note The default value is based on 96 MHz PLL/2 source.
- * If you use a different source, such as the FLL,
- * you must set this properly.
+ * @brief MCU flash clock frequency.
*/
-#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
-#endif
-
-/**
- * @brief UART0 clock source.
- * @note The default value is to use PLL/2 or FLL source.
- */
-#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_SRC 1
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif
/** @} */
@@ -175,29 +185,52 @@ /*===========================================================================*/
#if !defined(KINETIS_SYSCLK_FREQUENCY)
-#error KINETIS_SYSCLK_FREQUENCY must be defined
+ #error KINETIS_SYSCLK_FREQUENCY must be defined
#endif
#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
-#error KINETIS_SYSCLK_FREQUENCY out of range
+ #error KINETIS_SYSCLK_FREQUENCY out of range
#endif
#if !defined(KINETIS_BUSCLK_FREQUENCY)
-#error KINETIS_BUSCLK_FREQUENCY must be defined
+ #error KINETIS_BUSCLK_FREQUENCY must be defined
#endif
#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
-#error KINETIS_BUSCLK_FREQUENCY out of range
+ #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+ #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+ #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
- KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
-#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+ KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
- KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
-#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
#endif
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
@@ -259,7 +292,7 @@ typedef uint32_t halrtcnt_t; extern "C" {
#endif
void hal_lld_init(void);
- void mk20d50_clock_init(void);
+ void k20x_clock_init(void);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/KINETIS/K20x/kinetis_registry.h b/os/hal/ports/KINETIS/K20x/kinetis_registry.h index 024a424..4c70e84 100644 --- a/os/hal/ports/KINETIS/K20x/kinetis_registry.h +++ b/os/hal/ports/KINETIS/K20x/kinetis_registry.h @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +16,8 @@ */
/**
- * @file KL2x/kinetis_registry.h
- * @brief KL2x capabilities registry.
+ * @file K20x/kinetis_registry.h
+ * @brief K20x capabilities registry.
*
* @addtogroup HAL
* @{
@@ -25,31 +26,230 @@ #ifndef _KINETIS_REGISTRY_H_
#define _KINETIS_REGISTRY_H_
+#if !defined(K20x) || defined(__DOXYGEN__)
+#define K20x
+#endif
+
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
- * @name KL2x capabilities
+ * @name K20x capabilities
* @{
*/
-/* EXT attributes.*/
+/*===========================================================================*/
+/* K20x5 */
+/*===========================================================================*/
+#if defined(K20x5) || defined(__DOXYGEN__)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector98
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+/* EXT attributes.*/
#define KINETIS_PORTA_IRQ_VECTOR VectorE0
#define KINETIS_PORTB_IRQ_VECTOR VectorE4
#define KINETIS_PORTC_IRQ_VECTOR VectorE8
#define KINETIS_PORTD_IRQ_VECTOR VectorEC
#define KINETIS_PORTE_IRQ_VECTOR VectorF0
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+#define KINETIS_HAS_I2C1 FALSE
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector80
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector90
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR Vector84
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector8C
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector94
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SPI1 FALSE
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR VectorA4
+#define KINETIS_FTM1_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_FTM2 FALSE
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR VectorB8
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR VectorBC
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR VectorC0
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR VectorC4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorCC
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorDC
+
+/*===========================================================================*/
+/* K20x7 */
+/*===========================================================================*/
+#elif defined(K20x7)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 72000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/**
+ * @name K20x7 attributes
+ * @{
+ */
/* ADC attributes.*/
#define KINETIS_HAS_ADC0 TRUE
-#define KINETIS_ADC0_IRQ_VECTOR Vector98
+#define KINETIS_ADC0_IRQ_VECTOR Vector124
+#define KINETIS_HAS_ADC1 TRUE
+#define KINETIS_ADC1_IRQ_VECTOR Vector128
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR Vector184
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR Vector19C
+#define KINETIS_PORTB_IRQ_VECTOR Vector1A0
+#define KINETIS_PORTC_IRQ_VECTOR Vector1A4
+#define KINETIS_PORTD_IRQ_VECTOR Vector1A8
+#define KINETIS_PORTE_IRQ_VECTOR Vector1AC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
/* I2C attributes.*/
-#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR VectorA0
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR VectorA4
-/* USB attributes */
-#define KINETIS_USB_IRQ_VECTOR VectorCC
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR VectorF4
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR VectorFC
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector104
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorF8
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector100
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector108
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR VectorAC
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR Vector138
+#define KINETIS_FTM1_IRQ_VECTOR Vector13C
+#define KINETIS_HAS_FTM2 TRUE
+#define KINETIS_FTM2_IRQ_VECTOR Vector140
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR Vector150
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR Vector154
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR Vector158
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR Vector15C
+#define KINETIS_HAS_PIT FALSE
+#define KINETIS_PIT_CHANNELS 4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR Vector164
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR Vector194
+
+#endif /* K20xY */
/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/mk20d5.h b/os/hal/ports/KINETIS/K20x/mk20d5.h deleted file mode 100644 index aa70723..0000000 --- a/os/hal/ports/KINETIS/K20x/mk20d5.h +++ /dev/null @@ -1,2394 +0,0 @@ -/* - * Copyright (C) 2014 Fabio Utzig, http://fabioutzig.com - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef _MK20D5_H_ -#define _MK20D5_H_ - -/* - * ============================================================== - * ---------- Interrupt Number Definition ----------------------- - * ============================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ****************/ - InitialSP_IRQn = -15, - InitialPC_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - -/****** K20x Specific Interrupt Numbers ***********************/ - DMA0_IRQn = 0, - DMA1_IRQn = 1, - DMA2_IRQn = 2, - DMA3_IRQn = 3, - DMAError_IRQn = 4, - DMA_IRQn = 5, - FlashMemComplete_IRQn = 6, - FlashMemReadCollision_IRQn = 7, - LowVoltageWarning_IRQn = 8, - LLWU_IRQn = 9, - WDOG_IRQn = 10, - I2C0_IRQn = 11, - SPI0_IRQn = 12, - I2S0_IRQn = 13, - I2S1_IRQn = 14, - UART0LON_IRQn = 15, - UART0Status_IRQn = 16, - UART0Error_IRQn = 17, - UART1Status_IRQn = 18, - UART1Error_IRQn = 19, - UART2Status_IRQn = 20, - UART2Error_IRQn = 21, - ADC0_IRQn = 22, - CMP0_IRQn = 23, - CMP1_IRQn = 24, - FTM0_IRQn = 25, - FTM1_IRQn = 26, - CMT_IRQn = 27, - RTCAlarm_IRQn = 28, - RTCSeconds_IRQn = 29, - PITChannel0_IRQn = 30, - PITChannel1_IRQn = 31, - PITChannel2_IRQn = 32, - PITChannel3_IRQn = 33, - PDB_IRQn = 34, - USB_OTG_IRQn = 35, - USBChargerDetect_IRQn = 36, - TSI_IRQn = 37, - MCG_IRQn = 38, - LowPowerTimer_IRQn = 39, - PINA_IRQn = 40, - PINB_IRQn = 41, - PINC_IRQn = 42, - PIND_IRQn = 43, - PINE_IRQn = 44, - SoftInitInt_IRQn = 45, -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/** - * @brief K20x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __MPU_PRESENT 0 -#define __FPU_PRESENT 0 -#define __NVIC_PRIO_BITS 4 -#define __Vendor_SysTickConfig 0 - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ - -typedef struct -{ - __IO uint32_t SOPT1; - __IO uint32_t SOPT1CFG; - uint32_t RESERVED0[1023]; - __IO uint32_t SOPT2; - uint32_t RESERVED1[1]; - __IO uint32_t SOPT4; - __IO uint32_t SOPT5; - uint32_t RESERVED2[1]; - __IO uint32_t SOPT7; - uint32_t RESERVED3[2]; - __I uint32_t SDID; - uint32_t RESERVED4[3]; - __IO uint32_t SCGC4; - __IO uint32_t SCGC5; - __IO uint32_t SCGC6; - __IO uint32_t SCGC7; - __IO uint32_t CLKDIV1; - __IO uint32_t CLKDIV2; - __I uint32_t FCFG1; - __I uint32_t FCFG2; - __I uint32_t UIDH; - __I uint32_t UIDMH; - __I uint32_t UIDML; - __I uint32_t UIDL; -} SIM_TypeDef; - -typedef struct -{ - __IO uint8_t PE1; - __IO uint8_t PE2; - __IO uint8_t PE3; - __IO uint8_t PE4; - __IO uint8_t ME; - __IO uint8_t F1; - __IO uint8_t F2; - __I uint8_t F3; - __IO uint8_t FILT1; - __IO uint8_t FILT2; -} LLWU_TypeDef; - -typedef struct -{ - __IO uint32_t PCR[32]; - __O uint32_t GPCLR; - __O uint32_t GPCHR; - uint32_t RESERVED0[6]; - __IO uint32_t ISFR; -} PORT_TypeDef; - -typedef struct -{ - __IO uint8_t C1; - __IO uint8_t C2; - __IO uint8_t C3; - __IO uint8_t C4; - __IO uint8_t C5; - __IO uint8_t C6; - __I uint8_t S; - uint8_t RESERVED0[1]; - __IO uint8_t SC; - uint8_t RESERVED1[1]; - __IO uint8_t ATCVH; - __IO uint8_t ATCVL; - __IO uint8_t C7; - __IO uint8_t C8; -} MCG_TypeDef; - -typedef struct -{ - __IO uint8_t CR; -} OSC_TypeDef; - -typedef struct { - uint32_t SADDR; /* TCD Source Address */ - uint16_t SOFF; /* TCD Signed Source Address Offset */ - uint16_t ATTR; /* TCD Transfer Attributes */ - union { - uint32_t NBYTES_MLNO; /* TCD Minor Byte Count (Minor Loop Disabled) */ - uint32_t NBYTES_MLOFFNO; /* TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ - uint32_t NBYTES_MLOFFYES; /* TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ - }; - uint32_t SLAST; /* TCD Last Source Address Adjustment */ - uint32_t DADDR; /* TCD Destination Address */ - uint16_t DOFF; /* TCD Signed Destination Address Offset */ - union { - uint16_t CITER_ELINKNO; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - uint16_t CITER_ELINKYES; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; - uint32_t DLASTSGA; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ - uint16_t CSR; /* TCD Control and Status */ - union { - uint16_t BITER_ELINKNO; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - uint16_t BITER_ELINKYES; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; -} DMA_TCD_TypeDef; - -/** DMA - Peripheral register structure */ -typedef struct { - __IO uint32_t CR; /* Control Register */ - __IO uint32_t ES; /* Error Status Register */ - __IO uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /* Enable Request Register */ - __IO uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /* Enable Error Interrupt Register */ - __IO uint8_t CEEI; /* Clear Enable Error Interrupt Register */ - __IO uint8_t SEEI; /* Set Enable Error Interrupt Register */ - __IO uint8_t CERQ; /* Clear Enable Request Register */ - __IO uint8_t SERQ; /* Set Enable Request Register */ - __IO uint8_t CDNE; /* Clear DONE Status Bit Register */ - __IO uint8_t SSRT; /* Set START Bit Register */ - __IO uint8_t CERR; /* Clear Error Register */ - __IO uint8_t CINT; /* Clear Interrupt Request Register */ - __IO uint8_t RESERVED_2[4]; - __IO uint32_t INT; /* Interrupt Request Register */ - __IO uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /* Error Register */ - __IO uint8_t RESERVED_4[4]; - __IO uint32_t HRS; /* Hardware Request Status Register */ - __IO uint8_t RESERVED_5[200]; - __IO uint8_t DCHPRI3; /* Channel 3 Priority Register */ - __IO uint8_t DCHPRI2; /* Channel 2 Priority Register */ - __IO uint8_t DCHPRI1; /* Channel 1 Priority Register */ - __IO uint8_t DCHPRI0; /* Channel 0 Priority Register */ - __IO uint8_t RESERVED_6[3836]; - DMA_TCD_TypeDef TCD[4]; -} DMA_TypeDef; - -typedef struct -{ - __IO uint8_t CHCFG[4]; -} DMAMUX_TypeDef; - -/** PIT - Peripheral register structure */ -typedef struct { - __IO uint32_t MCR; /* PIT Module Control Register */ - uint8_t RESERVED0[252]; - struct PIT_CHANNEL { - __IO uint32_t LDVAL; /* Timer Load Value Register */ - __IO uint32_t CVAL; /* Current Timer Value Register */ - __IO uint32_t TCTRL; /* Timer Control Register */ - __IO uint32_t TFLG; /* Timer Flag Register */ - } CHANNEL[4]; -} PIT_TypeDef; - -typedef struct -{ - __IO uint32_t SC; /* Status and Control */ - __IO uint32_t CNT; /* Counter */ - __IO uint32_t MOD; /* Modulo */ - struct FTM_Channel { - __IO uint32_t CnSC; /* Channel Status and Control */ - __IO uint32_t CnV; /* Channel Value */ - } CHANNEL[8]; - __IO uint32_t CNTIN; /* Counter Initial Value */ - __IO uint32_t STATUS; /* Capture and Compare Status */ - __IO uint32_t MODE; /* Features Mode Selection */ - __IO uint32_t SYNC; /* Synchronization */ - __IO uint32_t OUTINIT; /* Initial State for Channels Output */ - __IO uint32_t OUTMASK; /* Output Mask */ - __IO uint32_t COMBINE; /* Function for Linked Channels */ - __IO uint32_t DEADTIME; /* Deadtime Insertion Control */ - __IO uint32_t EXTTRIG; /* FTM External Trigger */ - __IO uint32_t POL; /* Channels Polarity */ - __IO uint32_t FMS; /* Fault Mode Status */ - __IO uint32_t FILTER; /* Input Capture Filter Control */ - __IO uint32_t FLTCTRL; /* Fault Control */ - __IO uint32_t QDCTRL; /* Quadrature Decode Control and Status */ - __IO uint32_t CONF; /* Configuration */ - __IO uint32_t FTLPOL; /* FTM Fault Input Polarity */ - __IO uint32_t SYNCONF; /* Synchronization Configuration */ - __IO uint32_t INVCTRL; /* FTM Inverting Control */ - __IO uint32_t SWOCTRL; /* FTM Software Output Control */ - __IO uint32_t PWMLOAD; /* FTM PWM Load */ -} FTM_TypeDef; - -typedef struct -{ - __IO uint32_t SC1A; // offset: 0x00 - __IO uint32_t SC1B; // offset: 0x04 - __IO uint32_t CFG1; // offset: 0x08 - __IO uint32_t CFG2; // offset: 0x0C - __I uint32_t RA; // offset: 0x10 - __I uint32_t RB; // offset: 0x14 - __IO uint32_t CV1; // offset: 0x18 - __IO uint32_t CV2; // offset: 0x1C - __IO uint32_t SC2; // offset: 0x20 - __IO uint32_t SC3; // offset: 0x24 - __IO uint32_t OFS; // offset: 0x28 - __IO uint32_t PG; // offset: 0x2C - __IO uint32_t MG; // offset: 0x30 - __IO uint32_t CLPD; // offset: 0x34 - __IO uint32_t CLPS; // offset: 0x38 - __IO uint32_t CLP4; // offset: 0x3C - __IO uint32_t CLP3; // offset: 0x40 - __IO uint32_t CLP2; // offset: 0x44 - __IO uint32_t CLP1; // offset: 0x48 - __IO uint32_t CLP0; // offset: 0x4C - uint32_t RESERVED0[1]; // offset: 0x50 - __IO uint32_t CLMD; // offset: 0x54 - __IO uint32_t CLMS; // offset: 0x58 - __IO uint32_t CLM4; // offset: 0x5C - __IO uint32_t CLM3; // offset: 0x60 - __IO uint32_t CLM2; // offset: 0x64 - __IO uint32_t CLM1; // offset: 0x68 - __IO uint32_t CLM0; // offset: 0x6C -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t PSR; - __IO uint32_t CMR; - __I uint32_t CNR; -} LPTMR_TypeDef; - -typedef struct -{ - __IO uint32_t GENCS; - __IO uint32_t DATA; - __IO uint32_t TSHD; -} TSI_TypeDef; - -typedef struct -{ - __IO uint32_t PDOR; - __IO uint32_t PSOR; - __IO uint32_t PCOR; - __IO uint32_t PTOR; - __IO uint32_t PDIR; - __IO uint32_t PDDR; -} GPIO_TypeDef; - -/** SPI - Peripheral register structure */ -typedef struct { - __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ - uint32_t RESERVED0[1]; - __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ - __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ - }; - uint32_t RESERVED1[6]; - __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ - __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ - union { /* offset: 0x34 */ - __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ - __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ - }; - __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ - __I uint32_t TXFR[4]; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ - uint32_t RESERVED2[12]; - __I uint32_t RXFR[4]; /**< DSPI Receive FIFO Registers, offset: 0x7C */ -} SPI_TypeDef; - -typedef struct -{ - __IO uint8_t A1; - __IO uint8_t F; - __IO uint8_t C1; - __IO uint8_t S; - __IO uint8_t D; - __IO uint8_t C2; - __IO uint8_t FLT; - __IO uint8_t RA; - __IO uint8_t SMB; - __IO uint8_t A2; - __IO uint8_t SLTH; - __IO uint8_t SLTL; -} I2C_TypeDef; - -typedef struct -{ - __IO uint8_t BDH; - __IO uint8_t BDL; - __IO uint8_t C1; - __IO uint8_t C2; - __I uint8_t S1; - __IO uint8_t S2; - __IO uint8_t C3; - __IO uint8_t D; - __IO uint8_t MA1; - __IO uint8_t MA2; - __IO uint8_t C4; - __IO uint8_t C5; - __I uint8_t ED; - __IO uint8_t MODEM; - __IO uint8_t IR; - uint8_t RESERVED0[1]; - __IO uint8_t PFIFO; - __IO uint8_t CFIFO; - __IO uint8_t SFIFO; - __IO uint8_t TWFIFO; - __I uint8_t TCFIFO; - __IO uint8_t RWFIFO; - __I uint8_t RCFIFO; - uint8_t RESERVED1[1]; - __IO uint8_t C7816; - __IO uint8_t IE7816; - __IO uint8_t IS7816; - union { - __IO uint8_t WP7816T0; - __IO uint8_t WP7816T1; - }; - __IO uint8_t WN7816; - __IO uint8_t WF7816; - __IO uint8_t ET7816; - __IO uint8_t TL7816; - uint8_t RESERVED2[2]; - __IO uint8_t C6; - __IO uint8_t PCTH; - __IO uint8_t PCTL; - __IO uint8_t B1T; - __IO uint8_t SDTH; - __IO uint8_t SDTL; - __IO uint8_t PRE; - __IO uint8_t TPL; - __IO uint8_t IE; - __IO uint8_t WB; - __IO uint8_t S3; - __IO uint8_t S4; - __I uint8_t RPL; - __I uint8_t RPREL; - __IO uint8_t CPW; - __IO uint8_t RIDT; - __IO uint8_t TIDT; -} UART_TypeDef; - -typedef struct -{ - __IO uint8_t LVDSC1; - __IO uint8_t LVDSC2; - __IO uint8_t REGSC; -} PMC_TypeDef; - -typedef struct -{ - __IO uint16_t STCTRLH; - __IO uint16_t STCTRLL; - __IO uint16_t TOVALH; - __IO uint16_t TOVALL; - __IO uint16_t WINH; - __IO uint16_t WINL; - __IO uint16_t REFRESH; - __IO uint16_t UNLOCK; - __IO uint16_t TMROUTH; - __IO uint16_t TMROUTL; - __IO uint16_t RSTCNT; - __IO uint16_t PRESC; -} WDOG_TypeDef; - -typedef struct { - __I uint8_t PERID; // 0x00 - uint8_t RESERVED0[3]; - __I uint8_t IDCOMP; // 0x04 - uint8_t RESERVED1[3]; - __I uint8_t REV; // 0x08 - uint8_t RESERVED2[3]; - __I uint8_t ADDINFO; // 0x0C - uint8_t RESERVED3[3]; - __IO uint8_t OTGISTAT; // 0x10 - uint8_t RESERVED4[3]; - __IO uint8_t OTGICR; // 0x14 - uint8_t RESERVED5[3]; - __IO uint8_t OTGSTAT; // 0x18 - uint8_t RESERVED6[3]; - __IO uint8_t OTGCTL; // 0x1C - uint8_t RESERVED7[99]; - __IO uint8_t ISTAT; // 0x80 - uint8_t RESERVED8[3]; - __IO uint8_t INTEN; // 0x84 - uint8_t RESERVED9[3]; - __IO uint8_t ERRSTAT; // 0x88 - uint8_t RESERVED10[3]; - __IO uint8_t ERREN; // 0x8C - uint8_t RESERVED11[3]; - __I uint8_t STAT; // 0x90 - uint8_t RESERVED12[3]; - __IO uint8_t CTL; // 0x94 - uint8_t RESERVED13[3]; - __IO uint8_t ADDR; // 0x98 - uint8_t RESERVED14[3]; - __IO uint8_t BDTPAGE1; // 0x9C - uint8_t RESERVED15[3]; - __IO uint8_t FRMNUML; // 0xA0 - uint8_t RESERVED16[3]; - __IO uint8_t FRMNUMH; // 0xA4 - uint8_t RESERVED17[3]; - __IO uint8_t TOKEN; // 0xA8 - uint8_t RESERVED18[3]; - __IO uint8_t SOFTHLD; // 0xAC - uint8_t RESERVED19[3]; - __IO uint8_t BDTPAGE2; // 0xB0 - uint8_t RESERVED20[3]; - __IO uint8_t BDTPAGE3; // 0xB4 - uint8_t RESERVED21[11]; - struct { - __IO uint8_t V; // 0xC0 - uint8_t RESERVED[3]; - } ENDPT[16]; - __IO uint8_t USBCTRL; // 0x100 - uint8_t RESERVED22[3]; - __I uint8_t OBSERVE; // 0x104 - uint8_t RESERVED23[3]; - __IO uint8_t CONTROL; // 0x108 - uint8_t RESERVED24[3]; - __IO uint8_t USBTRC0; // 0x10C - uint8_t RESERVED25[7]; - __IO uint8_t USBFRMADJUST; // 0x114 -} USBOTG_TypeDef; - -/****************************************************************/ -/* Peripheral memory map */ -/****************************************************************/ -#define DMA_BASE ((uint32_t)0x40008000) -#define DMAMUX_BASE ((uint32_t)0x40021000) -#define SPI0_BASE ((uint32_t)0x4002C000) -#define PIT_BASE ((uint32_t)0x40037000) -#define FTM0_BASE ((uint32_t)0x40038000) -#define FTM1_BASE ((uint32_t)0x40039000) -#define ADC0_BASE ((uint32_t)0x4003B000) -#define LPTMR0_BASE ((uint32_t)0x40040000) -#define TSI0_BASE ((uint32_t)0x40045000) -#define SIM_BASE ((uint32_t)0x40047000) -#define PORTA_BASE ((uint32_t)0x40049000) -#define PORTB_BASE ((uint32_t)0x4004A000) -#define PORTC_BASE ((uint32_t)0x4004B000) -#define PORTD_BASE ((uint32_t)0x4004C000) -#define PORTE_BASE ((uint32_t)0x4004D000) -#define WDOG_BASE ((uint32_t)0x40052000) -#define MCG_BASE ((uint32_t)0x40064000) -#define OSC0_BASE ((uint32_t)0x40065000) -#define I2C0_BASE ((uint32_t)0x40066000) -#define UART0_BASE ((uint32_t)0x4006A000) -#define UART1_BASE ((uint32_t)0x4006B000) -#define UART2_BASE ((uint32_t)0x4006C000) -#define USBOTG_BASE ((uint32_t)0x40072000) -#define LLWU_BASE ((uint32_t)0x4007C000) -#define PMC_BASE ((uint32_t)0x4007D000) -#define GPIOA_BASE ((uint32_t)0x400FF000) -#define GPIOB_BASE ((uint32_t)0x400FF040) -#define GPIOC_BASE ((uint32_t)0x400FF080) -#define GPIOD_BASE ((uint32_t)0x400FF0C0) -#define GPIOE_BASE ((uint32_t)0x400FF100) - -/****************************************************************/ -/* Peripheral declaration */ -/****************************************************************/ -#define DMA ((DMA_TypeDef *) DMA_BASE) -#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) -#define PIT ((PIT_TypeDef *) PIT_BASE) -#define FTM0 ((FTM_TypeDef *) FTM0_BASE) -#define FTM1 ((FTM_TypeDef *) FTM1_BASE) -#define ADC0 ((ADC_TypeDef *) ADC0_BASE) -#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) -#define TSI0 ((TSI_TypeDef *) TSI0_BASE) -#define SIM ((SIM_TypeDef *) SIM_BASE) -#define LLWU ((LLWU_TypeDef *) LLWU_BASE) -#define PMC ((PMC_TypeDef *) PMC_BASE) -#define PORTA ((PORT_TypeDef *) PORTA_BASE) -#define PORTB ((PORT_TypeDef *) PORTB_BASE) -#define PORTC ((PORT_TypeDef *) PORTC_BASE) -#define PORTD ((PORT_TypeDef *) PORTD_BASE) -#define PORTE ((PORT_TypeDef *) PORTE_BASE) -#define WDOG ((WDOG_TypeDef *) WDOG_BASE) -#define USBOTG ((USBOTG_TypeDef *) USBOTG_BASE) -#define MCG ((MCG_TypeDef *) MCG_BASE) -#define OSC ((OSC_TypeDef *) OSC0_BASE) -#define SPI0 ((SPI_TypeDef *) SPI0_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) - -/****************************************************************/ -/* Peripheral Registers Bits Definition */ -/****************************************************************/ - -/****************************************************************/ -/* */ -/* System Integration Module (SIM) */ -/* */ -/****************************************************************/ -/********* Bits definition for SIM_SOPT1 register *************/ -#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ -#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ -#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ -#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ -#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ -#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) -#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) - -/******* Bits definition for SIM_SOPT1CFG register ************/ -#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ -#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ -#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ - -/******* Bits definition for SIM_SOPT2 register ************/ -#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ -#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ -#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) -#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) -#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 -#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) -#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) -#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ - -/******* Bits definition for SIM_SCGC4 register ************/ -#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ -#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ -#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ -#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ -#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ -#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ -#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ -#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ -#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ - -/******* Bits definition for SIM_SCGC5 register ************/ -#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ -#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ -#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ -#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ -#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ -#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ -#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ -#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ -#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ -#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ -#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ -#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ -#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ -#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ -#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ -#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ -#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ -#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ - -/****** Bits definition for SIM_CLKDIV1 register ***********/ -#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 -#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) -#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) -#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 -#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) -#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) -#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 -#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) -#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) - -/****** Bits definition for SIM_CLKDIV2 register ***********/ -#define SIM_CLKDIV2_USBDIV_SHIFT 1 -#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) -#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) -#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) - -/****************************************************************/ -/* */ -/* Low-Leakage Wakeup Unit (LLWU) */ -/* */ -/****************************************************************/ -/********** Bits definition for LLWU_PE1 register *************/ -#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ -#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ -#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ -#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ -#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ -#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ -#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ -#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ -#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ -#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ -#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ -#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ - -/********** Bits definition for LLWU_PE2 register *************/ -#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ -#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ -#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ -#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ -#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ -#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ -#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ -#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ -#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ -#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ -#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ -#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ - -/********** Bits definition for LLWU_PE3 register *************/ -#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ -#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ -#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ -#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ -#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ -#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ -#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ -#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ -#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ -#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ -#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ -#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ - -/********** Bits definition for LLWU_PE4 register *************/ -#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ -#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ -#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ -#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ -#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ -#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ -#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ -#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ -#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ -#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ -#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ -#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ - -/********** Bits definition for LLWU_ME register *************/ -#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ -#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ -#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ -#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ -#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ -#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ -#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ -#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ - -/********** Bits definition for LLWU_F1 register *************/ -#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ -#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ -#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ -#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ -#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ -#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ -#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ -#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ - -/********** Bits definition for LLWU_F2 register *************/ -#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ -#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ -#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ -#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ -#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ -#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ -#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ -#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ - -/********** Bits definition for LLWU_F3 register *************/ -#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ -#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ -#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ -#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ -#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ -#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ -#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ -#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ - -/********** Bits definition for LLWU_FILT1 register *************/ -#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ - -/********** Bits definition for LLWU_FILT2 register *************/ -#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ - -/****************************************************************/ -/* */ -/* Port Control and interrupts (PORT) */ -/* */ -/****************************************************************/ -/******** Bits definition for PORTx_PCRn register *************/ -#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ -#define PORTx_PCRn_IRQC_SHIFT 16 -#define PORTx_PCRn_IRQC_MASK ((uint32_t)((uint32_t)0xF << PORTx_PCRn_IRQC_SHIFT)) -#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) -#define PORTx_PCRn_LK ((uint32_t)0x00008000) /*!< Lock Register */ -#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ -#define PORTx_PCRn_MUX_MASK ((uint32_t)((uint32_t)0x7 << PORTx_PCRn_MUX_SHIFT)) /*!< Pin Mux Control (mask) */ -#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ -#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ -#define PORTx_PCRn_ODE ((uint32_t)0x00000020) /*!< Open Drain Enable */ -#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ -#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ -#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ -#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ - -/****************************************************************/ -/* */ -/* Oscillator (OSC) */ -/* */ -/****************************************************************/ -/*********** Bits definition for OSC_CR register **************/ -#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ -#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ -#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ -#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ -#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ -#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ - -/****************************************************************/ -/* */ -/* Direct Memory Access (DMA) */ -/* */ -/****************************************************************/ -/* ---------------------------------------------------------------------------- - -- DMA - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros - * @{ - */ - - -/* DMA - Register accessors */ -#define DMA_CR_REG(base) ((base)->CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK 0x4000u -#define DMA_ES_CPE_SHIFT 14 -#define DMA_ES_ECX_MASK 0x10000u -#define DMA_ES_ECX_SHIFT 16 -#define DMA_ES_VLD_MASK 0x80000000u -#define DMA_ES_VLD_SHIFT 31 -/* ERQ Bit Fields */ -#define DMA_ERQ_ERQ0_MASK 0x1u -#define DMA_ERQ_ERQ0_SHIFT 0 -#define DMA_ERQ_ERQ1_MASK 0x2u -#define DMA_ERQ_ERQ1_SHIFT 1 -#define DMA_ERQ_ERQ2_MASK 0x4u -#define DMA_ERQ_ERQ2_SHIFT 2 -#define DMA_ERQ_ERQ3_MASK 0x8u -#define DMA_ERQ_ERQ3_SHIFT 3 -/* EEI Bit Fields */ -#define DMA_EEI_EEI0_MASK 0x1u -#define DMA_EEI_EEI0_SHIFT 0 -#define DMA_EEI_EEI1_MASK 0x2u -#define DMA_EEI_EEI1_SHIFT 1 -#define DMA_EEI_EEI2_MASK 0x4u -#define DMA_EEI_EEI2_SHIFT 2 -#define DMA_EEI_EEI3_MASK 0x8u -#define DMA_EEI_EEI3_SHIFT 3 -/* CEEI Bit Fields */ -#define DMA_CEEI_CEEI_MASK 0xFu -#define DMA_CEEI_CEEI_SHIFT 0 -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK 0x40u -#define DMA_CEEI_CAEE_SHIFT 6 -#define DMA_CEEI_NOP_MASK 0x80u -#define DMA_CEEI_NOP_SHIFT 7 -/* SEEI Bit Fields */ -#define DMA_SEEI_SEEI_MASK 0xFu -#define DMA_SEEI_SEEI_SHIFT 0 -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK 0x40u -#define DMA_SEEI_SAEE_SHIFT 6 -#define DMA_SEEI_NOP_MASK 0x80u -#define DMA_SEEI_NOP_SHIFT 7 -/* CERQ Bit Fields */ -#define DMA_CERQ_CERQ_MASK 0xFu -#define DMA_CERQ_CERQ_SHIFT 0 -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK 0x40u -#define DMA_CERQ_CAER_SHIFT 6 -#define DMA_CERQ_NOP_MASK 0x80u -#define DMA_CERQ_NOP_SHIFT 7 -/* SERQ Bit Fields */ -#define DMA_SERQ_SERQ_MASK 0xFu -#define DMA_SERQ_SERQ_SHIFT 0 -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK 0x40u -#define DMA_SERQ_SAER_SHIFT 6 -#define DMA_SERQ_NOP_MASK 0x80u -#define DMA_SERQ_NOP_SHIFT 7 -/* CDNE Bit Fields */ -#define DMA_CDNE_CDNE_MASK 0xFu -#define DMA_CDNE_CDNE_SHIFT 0 -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK 0x40u -#define DMA_CDNE_CADN_SHIFT 6 -#define DMA_CDNE_NOP_MASK 0x80u -#define DMA_CDNE_NOP_SHIFT 7 -/* SSRT Bit Fields */ -#define DMA_SSRT_SSRT_MASK 0xFu -#define DMA_SSRT_SSRT_SHIFT 0 -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK 0x40u -#define DMA_SSRT_SAST_SHIFT 6 -#define DMA_SSRT_NOP_MASK 0x80u -#define DMA_SSRT_NOP_SHIFT 7 -/* CERR Bit Fields */ -#define DMA_CERR_CERR_MASK 0xFu -#define DMA_CERR_CERR_SHIFT 0 -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK 0x40u -#define DMA_CERR_CAEI_SHIFT 6 -#define DMA_CERR_NOP_MASK 0x80u -#define DMA_CERR_NOP_SHIFT 7 -/* CINT Bit Fields */ -#define DMA_CINT_CINT_MASK 0xFu -#define DMA_CINT_CINT_SHIFT 0 -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK 0x40u -#define DMA_CINT_CAIR_SHIFT 6 -#define DMA_CINT_NOP_MASK 0x80u -#define DMA_CINT_NOP_SHIFT 7 -/* INT Bit Fields */ -#define DMA_INT_INT0_MASK 0x1u -#define DMA_INT_INT0_SHIFT 0 -#define DMA_INT_INT1_MASK 0x2u -#define DMA_INT_INT1_SHIFT 1 -#define DMA_INT_INT2_MASK 0x4u -#define DMA_INT_INT2_SHIFT 2 -#define DMA_INT_INT3_MASK 0x8u -#define DMA_INT_INT3_SHIFT 3 -/* ERR Bit Fields */ -#define DMA_ERR_ERR0_MASK 0x1u -#define DMA_ERR_ERR0_SHIFT 0 -#define DMA_ERR_ERR1_MASK 0x2u -#define DMA_ERR_ERR1_SHIFT 1 -#define DMA_ERR_ERR2_MASK 0x4u -#define DMA_ERR_ERR2_SHIFT 2 -#define DMA_ERR_ERR3_MASK 0x8u -#define DMA_ERR_ERR3_SHIFT 3 -/* HRS Bit Fields */ -#define DMA_HRS_HRS0_MASK 0x1u -#define DMA_HRS_HRS0_SHIFT 0 -#define DMA_HRS_HRS1_MASK 0x2u -#define DMA_HRS_HRS1_SHIFT 1 -#define DMA_HRS_HRS2_MASK 0x4u -#define DMA_HRS_HRS2_SHIFT 2 -#define DMA_HRS_HRS3_MASK 0x8u -#define DMA_HRS_HRS3_SHIFT 3 -/* DCHPRI3 Bit Fields */ -#define DMA_DCHPRI3_CHPRI_MASK 0xFu -#define DMA_DCHPRI3_CHPRI_SHIFT 0 -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK 0x40u -#define DMA_DCHPRI3_DPA_SHIFT 6 -#define DMA_DCHPRI3_ECP_MASK 0x80u -#define DMA_DCHPRI3_ECP_SHIFT 7 -/* DCHPRI2 Bit Fields */ -#define DMA_DCHPRI2_CHPRI_MASK 0xFu -#define DMA_DCHPRI2_CHPRI_SHIFT 0 -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK 0x40u -#define DMA_DCHPRI2_DPA_SHIFT 6 -#define DMA_DCHPRI2_ECP_MASK 0x80u -#define DMA_DCHPRI2_ECP_SHIFT 7 -/* DCHPRI1 Bit Fields */ -#define DMA_DCHPRI1_CHPRI_MASK 0xFu -#define DMA_DCHPRI1_CHPRI_SHIFT 0 -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK 0x40u -#define DMA_DCHPRI1_DPA_SHIFT 6 -#define DMA_DCHPRI1_ECP_MASK 0x80u -#define DMA_DCHPRI1_ECP_SHIFT 7 -/* DCHPRI0 Bit Fields */ -#define DMA_DCHPRI0_CHPRI_MASK 0xFu -#define DMA_DCHPRI0_CHPRI_SHIFT 0 -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK 0x40u -#define DMA_DCHPRI0_DPA_SHIFT 6 -#define DMA_DCHPRI0_ECP_MASK 0x80u -#define DMA_DCHPRI0_ECP_SHIFT 7 -/* SADDR Bit Fields */ -#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu -#define DMA_SADDR_SADDR_SHIFT 0 -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) -/* SOFF Bit Fields */ -#define DMA_SOFF_SOFF_MASK 0xFFFFu -#define DMA_SOFF_SOFF_SHIFT 0 -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) -/* ATTR Bit Fields */ -#define DMA_ATTR_DSIZE_MASK 0x7u -#define DMA_ATTR_DSIZE_SHIFT 0 -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK 0xF8u -#define DMA_ATTR_DMOD_SHIFT 3 -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK 0x700u -#define DMA_ATTR_SSIZE_SHIFT 8 -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK 0xF800u -#define DMA_ATTR_SMOD_SHIFT 11 -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) -/* NBYTES_MLNO Bit Fields */ -#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu -#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) -/* NBYTES_MLOFFNO Bit Fields */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 -/* NBYTES_MLOFFYES Bit Fields */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 -/* SLAST Bit Fields */ -#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu -#define DMA_SLAST_SLAST_SHIFT 0 -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) -/* DADDR Bit Fields */ -#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu -#define DMA_DADDR_DADDR_SHIFT 0 -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) -/* DOFF Bit Fields */ -#define DMA_DOFF_DOFF_MASK 0xFFFFu -#define DMA_DOFF_DOFF_SHIFT 0 -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) -/* CITER_ELINKNO Bit Fields */ -#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu -#define DMA_CITER_ELINKNO_CITER_SHIFT 0 -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u -#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 -/* CITER_ELINKYES Bit Fields */ -#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu -#define DMA_CITER_ELINKYES_CITER_SHIFT 0 -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u -#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u -#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 -/* DLAST_SGA Bit Fields */ -#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu -#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) -/* CSR Bit Fields */ -#define DMA_CSR_START_MASK 0x1u -#define DMA_CSR_START_SHIFT 0 -#define DMA_CSR_INTMAJOR_MASK 0x2u -#define DMA_CSR_INTMAJOR_SHIFT 1 -#define DMA_CSR_INTHALF_MASK 0x4u -#define DMA_CSR_INTHALF_SHIFT 2 -#define DMA_CSR_DREQ_MASK 0x8u -#define DMA_CSR_DREQ_SHIFT 3 -#define DMA_CSR_ESG_MASK 0x10u -#define DMA_CSR_ESG_SHIFT 4 -#define DMA_CSR_MAJORELINK_MASK 0x20u -#define DMA_CSR_MAJORELINK_SHIFT 5 -#define DMA_CSR_ACTIVE_MASK 0x40u -#define DMA_CSR_ACTIVE_SHIFT 6 -#define DMA_CSR_DONE_MASK 0x80u -#define DMA_CSR_DONE_SHIFT 7 -#define DMA_CSR_MAJORLINKCH_MASK 0xF00u -#define DMA_CSR_MAJORLINKCH_SHIFT 8 -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK 0xC000u -#define DMA_CSR_BWC_SHIFT 14 -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) -/* BITER_ELINKNO Bit Fields */ -#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu -#define DMA_BITER_ELINKNO_BITER_SHIFT 0 -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u -#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 -/* BITER_ELINKYES Bit Fields */ -#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu -#define DMA_BITER_ELINKYES_BITER_SHIFT 0 -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u -#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u -#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA base pointer */ -#define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u) -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA_BASE_PTR } - -/* ---------------------------------------------------------------------------- - -- DMA - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros - * @{ - */ - - -/* DMA - Register instance definitions */ -/* DMA */ -#define DMA_CR DMA_CR_REG(DMA_BASE_PTR) -#define DMA_ES DMA_ES_REG(DMA_BASE_PTR) -#define DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR) -#define DMA_EEI DMA_EEI_REG(DMA_BASE_PTR) -#define DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR) -#define DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR) -#define DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR) -#define DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR) -#define DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR) -#define DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR) -#define DMA_CERR DMA_CERR_REG(DMA_BASE_PTR) -#define DMA_CINT DMA_CINT_REG(DMA_BASE_PTR) -#define DMA_INT DMA_INT_REG(DMA_BASE_PTR) -#define DMA_ERR DMA_ERR_REG(DMA_BASE_PTR) -#define DMA_HRS DMA_HRS_REG(DMA_BASE_PTR) -#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR) -#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR) -#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR) -#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR) -#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0) -#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0) -#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1) -#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1) -#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2) -#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2) -#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3) -#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3) - -/* DMA - Register array accessors */ -#define DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index) -#define DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index) -#define DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index) -#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index) -#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index) -#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index) -#define DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index) -#define DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index) -#define DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index) -#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index) -#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index) -#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index) -#define DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index) -#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index) -#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index) - -/****************************************************************/ -/* */ -/* Direct Memory Access Multiplexer (DMAMUX) */ -/* */ -/****************************************************************/ -/******** Bits definition for DMAMUX_CHCFGn register **********/ -#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ -#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ -#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ -#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ -#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ - -/****************************************************************/ -/* */ -/* FlexTimer Module (FTM) */ -/* */ -/****************************************************************/ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) -#define FTM_SC_CLKS_MASK 0x18u -#define FTM_SC_CLKS_SHIFT 3 -#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) -#define FTM_SC_CPWMS 0x20u -#define FTM_SC_TOIE 0x40u -#define FTM_SC_TOF 0x80u -/* CNT Bit Fields */ -#define FTM_CNT_COUNT_MASK 0xFFFFu -#define FTM_CNT_COUNT_SHIFT 0 -#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) -/* MOD Bit Fields */ -#define FTM_MOD_MOD_MASK 0xFFFFu -#define FTM_MOD_MOD_SHIFT 0 -#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) -/* CnSC Bit Fields */ -#define FTM_CnSC_DMA 0x1u -#define FTM_CnSC_ELSA 0x4u -#define FTM_CnSC_ELSB 0x8u -#define FTM_CnSC_MSA 0x10u -#define FTM_CnSC_MSB 0x20u -#define FTM_CnSC_CHIE 0x40u -#define FTM_CnSC_CHF 0x80u -/* CnV Bit Fields */ -#define FTM_CnV_VAL_MASK 0xFFFFu -#define FTM_CnV_VAL_SHIFT 0 -#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) -/* CNTIN Bit Fields */ -#define FTM_CNTIN_INIT_MASK 0xFFFFu -#define FTM_CNTIN_INIT_SHIFT 0 -#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) -/* STATUS Bit Fields */ -#define FTM_STATUS_CH0F_MASK 0x1u -#define FTM_STATUS_CH0F_SHIFT 0 -#define FTM_STATUS_CH1F_MASK 0x2u -#define FTM_STATUS_CH1F_SHIFT 1 -#define FTM_STATUS_CH2F_MASK 0x4u -#define FTM_STATUS_CH2F_SHIFT 2 -#define FTM_STATUS_CH3F_MASK 0x8u -#define FTM_STATUS_CH3F_SHIFT 3 -#define FTM_STATUS_CH4F_MASK 0x10u -#define FTM_STATUS_CH4F_SHIFT 4 -#define FTM_STATUS_CH5F_MASK 0x20u -#define FTM_STATUS_CH5F_SHIFT 5 -#define FTM_STATUS_CH6F_MASK 0x40u -#define FTM_STATUS_CH6F_SHIFT 6 -#define FTM_STATUS_CH7F_MASK 0x80u -#define FTM_STATUS_CH7F_SHIFT 7 -/* MODE Bit Fields */ -#define FTM_MODE_FTMEN_MASK 0x1u -#define FTM_MODE_FTMEN_SHIFT 0 -#define FTM_MODE_INIT_MASK 0x2u -#define FTM_MODE_INIT_SHIFT 1 -#define FTM_MODE_WPDIS_MASK 0x4u -#define FTM_MODE_WPDIS_SHIFT 2 -#define FTM_MODE_PWMSYNC_MASK 0x8u -#define FTM_MODE_PWMSYNC_SHIFT 3 -#define FTM_MODE_CAPTEST_MASK 0x10u -#define FTM_MODE_CAPTEST_SHIFT 4 -#define FTM_MODE_FAULTM_MASK 0x60u -#define FTM_MODE_FAULTM_SHIFT 5 -#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) -#define FTM_MODE_FAULTIE_MASK 0x80u -#define FTM_MODE_FAULTIE_SHIFT 7 -/* SYNC Bit Fields */ -#define FTM_SYNC_CNTMIN_MASK 0x1u -#define FTM_SYNC_CNTMIN_SHIFT 0 -#define FTM_SYNC_CNTMAX_MASK 0x2u -#define FTM_SYNC_CNTMAX_SHIFT 1 -#define FTM_SYNC_REINIT_MASK 0x4u -#define FTM_SYNC_REINIT_SHIFT 2 -#define FTM_SYNC_SYNCHOM_MASK 0x8u -#define FTM_SYNC_SYNCHOM_SHIFT 3 -#define FTM_SYNC_TRIG0_MASK 0x10u -#define FTM_SYNC_TRIG0_SHIFT 4 -#define FTM_SYNC_TRIG1_MASK 0x20u -#define FTM_SYNC_TRIG1_SHIFT 5 -#define FTM_SYNC_TRIG2_MASK 0x40u -#define FTM_SYNC_TRIG2_SHIFT 6 -#define FTM_SYNC_SWSYNC_MASK 0x80u -#define FTM_SYNC_SWSYNC_SHIFT 7 -/* OUTINIT Bit Fields */ -#define FTM_OUTINIT_CH0OI_MASK 0x1u -#define FTM_OUTINIT_CH0OI_SHIFT 0 -#define FTM_OUTINIT_CH1OI_MASK 0x2u -#define FTM_OUTINIT_CH1OI_SHIFT 1 -#define FTM_OUTINIT_CH2OI_MASK 0x4u -#define FTM_OUTINIT_CH2OI_SHIFT 2 -#define FTM_OUTINIT_CH3OI_MASK 0x8u -#define FTM_OUTINIT_CH3OI_SHIFT 3 -#define FTM_OUTINIT_CH4OI_MASK 0x10u -#define FTM_OUTINIT_CH4OI_SHIFT 4 -#define FTM_OUTINIT_CH5OI_MASK 0x20u -#define FTM_OUTINIT_CH5OI_SHIFT 5 -#define FTM_OUTINIT_CH6OI_MASK 0x40u -#define FTM_OUTINIT_CH6OI_SHIFT 6 -#define FTM_OUTINIT_CH7OI_MASK 0x80u -#define FTM_OUTINIT_CH7OI_SHIFT 7 -/* OUTMASK Bit Fields */ -#define FTM_OUTMASK_CH0OM_MASK 0x1u -#define FTM_OUTMASK_CH0OM_SHIFT 0 -#define FTM_OUTMASK_CH1OM_MASK 0x2u -#define FTM_OUTMASK_CH1OM_SHIFT 1 -#define FTM_OUTMASK_CH2OM_MASK 0x4u -#define FTM_OUTMASK_CH2OM_SHIFT 2 -#define FTM_OUTMASK_CH3OM_MASK 0x8u -#define FTM_OUTMASK_CH3OM_SHIFT 3 -#define FTM_OUTMASK_CH4OM_MASK 0x10u -#define FTM_OUTMASK_CH4OM_SHIFT 4 -#define FTM_OUTMASK_CH5OM_MASK 0x20u -#define FTM_OUTMASK_CH5OM_SHIFT 5 -#define FTM_OUTMASK_CH6OM_MASK 0x40u -#define FTM_OUTMASK_CH6OM_SHIFT 6 -#define FTM_OUTMASK_CH7OM_MASK 0x80u -#define FTM_OUTMASK_CH7OM_SHIFT 7 -/* COMBINE Bit Fields */ -#define FTM_COMBINE_COMBINE0_MASK 0x1u -#define FTM_COMBINE_COMBINE0_SHIFT 0 -#define FTM_COMBINE_COMP0_MASK 0x2u -#define FTM_COMBINE_COMP0_SHIFT 1 -#define FTM_COMBINE_DECAPEN0_MASK 0x4u -#define FTM_COMBINE_DECAPEN0_SHIFT 2 -#define FTM_COMBINE_DECAP0_MASK 0x8u -#define FTM_COMBINE_DECAP0_SHIFT 3 -#define FTM_COMBINE_DTEN0_MASK 0x10u -#define FTM_COMBINE_DTEN0_SHIFT 4 -#define FTM_COMBINE_SYNCEN0_MASK 0x20u -#define FTM_COMBINE_SYNCEN0_SHIFT 5 -#define FTM_COMBINE_FAULTEN0_MASK 0x40u -#define FTM_COMBINE_FAULTEN0_SHIFT 6 -#define FTM_COMBINE_COMBINE1_MASK 0x100u -#define FTM_COMBINE_COMBINE1_SHIFT 8 -#define FTM_COMBINE_COMP1_MASK 0x200u -#define FTM_COMBINE_COMP1_SHIFT 9 -#define FTM_COMBINE_DECAPEN1_MASK 0x400u -#define FTM_COMBINE_DECAPEN1_SHIFT 10 -#define FTM_COMBINE_DECAP1_MASK 0x800u -#define FTM_COMBINE_DECAP1_SHIFT 11 -#define FTM_COMBINE_DTEN1_MASK 0x1000u -#define FTM_COMBINE_DTEN1_SHIFT 12 -#define FTM_COMBINE_SYNCEN1_MASK 0x2000u -#define FTM_COMBINE_SYNCEN1_SHIFT 13 -#define FTM_COMBINE_FAULTEN1_MASK 0x4000u -#define FTM_COMBINE_FAULTEN1_SHIFT 14 -#define FTM_COMBINE_COMBINE2_MASK 0x10000u -#define FTM_COMBINE_COMBINE2_SHIFT 16 -#define FTM_COMBINE_COMP2_MASK 0x20000u -#define FTM_COMBINE_COMP2_SHIFT 17 -#define FTM_COMBINE_DECAPEN2_MASK 0x40000u -#define FTM_COMBINE_DECAPEN2_SHIFT 18 -#define FTM_COMBINE_DECAP2_MASK 0x80000u -#define FTM_COMBINE_DECAP2_SHIFT 19 -#define FTM_COMBINE_DTEN2_MASK 0x100000u -#define FTM_COMBINE_DTEN2_SHIFT 20 -#define FTM_COMBINE_SYNCEN2_MASK 0x200000u -#define FTM_COMBINE_SYNCEN2_SHIFT 21 -#define FTM_COMBINE_FAULTEN2_MASK 0x400000u -#define FTM_COMBINE_FAULTEN2_SHIFT 22 -#define FTM_COMBINE_COMBINE3_MASK 0x1000000u -#define FTM_COMBINE_COMBINE3_SHIFT 24 -#define FTM_COMBINE_COMP3_MASK 0x2000000u -#define FTM_COMBINE_COMP3_SHIFT 25 -#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u -#define FTM_COMBINE_DECAPEN3_SHIFT 26 -#define FTM_COMBINE_DECAP3_MASK 0x8000000u -#define FTM_COMBINE_DECAP3_SHIFT 27 -#define FTM_COMBINE_DTEN3_MASK 0x10000000u -#define FTM_COMBINE_DTEN3_SHIFT 28 -#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u -#define FTM_COMBINE_SYNCEN3_SHIFT 29 -#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u -#define FTM_COMBINE_FAULTEN3_SHIFT 30 -/* DEADTIME Bit Fields */ -#define FTM_DEADTIME_DTVAL_MASK 0x3Fu -#define FTM_DEADTIME_DTVAL_SHIFT 0 -#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) -#define FTM_DEADTIME_DTPS_MASK 0xC0u -#define FTM_DEADTIME_DTPS_SHIFT 6 -#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) -/* EXTTRIG Bit Fields */ -#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u -#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 -#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u -#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 -#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u -#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 -#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u -#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 -#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u -#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 -#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u -#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 -#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u -#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 -#define FTM_EXTTRIG_TRIGF_MASK 0x80u -#define FTM_EXTTRIG_TRIGF_SHIFT 7 -/* POL Bit Fields */ -#define FTM_POL_POL0_MASK 0x1u -#define FTM_POL_POL0_SHIFT 0 -#define FTM_POL_POL1_MASK 0x2u -#define FTM_POL_POL1_SHIFT 1 -#define FTM_POL_POL2_MASK 0x4u -#define FTM_POL_POL2_SHIFT 2 -#define FTM_POL_POL3_MASK 0x8u -#define FTM_POL_POL3_SHIFT 3 -#define FTM_POL_POL4_MASK 0x10u -#define FTM_POL_POL4_SHIFT 4 -#define FTM_POL_POL5_MASK 0x20u -#define FTM_POL_POL5_SHIFT 5 -#define FTM_POL_POL6_MASK 0x40u -#define FTM_POL_POL6_SHIFT 6 -#define FTM_POL_POL7_MASK 0x80u -#define FTM_POL_POL7_SHIFT 7 -/* FMS Bit Fields */ -#define FTM_FMS_FAULTF0_MASK 0x1u -#define FTM_FMS_FAULTF0_SHIFT 0 -#define FTM_FMS_FAULTF1_MASK 0x2u -#define FTM_FMS_FAULTF1_SHIFT 1 -#define FTM_FMS_FAULTF2_MASK 0x4u -#define FTM_FMS_FAULTF2_SHIFT 2 -#define FTM_FMS_FAULTF3_MASK 0x8u -#define FTM_FMS_FAULTF3_SHIFT 3 -#define FTM_FMS_FAULTIN_MASK 0x20u -#define FTM_FMS_FAULTIN_SHIFT 5 -#define FTM_FMS_WPEN_MASK 0x40u -#define FTM_FMS_WPEN_SHIFT 6 -#define FTM_FMS_FAULTF_MASK 0x80u -#define FTM_FMS_FAULTF_SHIFT 7 -/* FILTER Bit Fields */ -#define FTM_FILTER_CH0FVAL_MASK 0xFu -#define FTM_FILTER_CH0FVAL_SHIFT 0 -#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) -#define FTM_FILTER_CH1FVAL_MASK 0xF0u -#define FTM_FILTER_CH1FVAL_SHIFT 4 -#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) -#define FTM_FILTER_CH2FVAL_MASK 0xF00u -#define FTM_FILTER_CH2FVAL_SHIFT 8 -#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) -#define FTM_FILTER_CH3FVAL_MASK 0xF000u -#define FTM_FILTER_CH3FVAL_SHIFT 12 -#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) -/* FLTCTRL Bit Fields */ -#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u -#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 -#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u -#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 -#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u -#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 -#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u -#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 -#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u -#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 -#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u -#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 -#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u -#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 -#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u -#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 -#define FTM_FLTCTRL_FFVAL_MASK 0xF00u -#define FTM_FLTCTRL_FFVAL_SHIFT 8 -#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) -/* QDCTRL Bit Fields */ -#define FTM_QDCTRL_QUADEN_MASK 0x1u -#define FTM_QDCTRL_QUADEN_SHIFT 0 -#define FTM_QDCTRL_TOFDIR_MASK 0x2u -#define FTM_QDCTRL_TOFDIR_SHIFT 1 -#define FTM_QDCTRL_QUADIR_MASK 0x4u -#define FTM_QDCTRL_QUADIR_SHIFT 2 -#define FTM_QDCTRL_QUADMODE_MASK 0x8u -#define FTM_QDCTRL_QUADMODE_SHIFT 3 -#define FTM_QDCTRL_PHBPOL_MASK 0x10u -#define FTM_QDCTRL_PHBPOL_SHIFT 4 -#define FTM_QDCTRL_PHAPOL_MASK 0x20u -#define FTM_QDCTRL_PHAPOL_SHIFT 5 -#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u -#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 -#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u -#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 -/* CONF Bit Fields */ -#define FTM_CONF_NUMTOF_MASK 0x1Fu -#define FTM_CONF_NUMTOF_SHIFT 0 -#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) -#define FTM_CONF_BDMMODE_MASK 0xC0u -#define FTM_CONF_BDMMODE_SHIFT 6 -#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) -#define FTM_CONF_GTBEEN_MASK 0x200u -#define FTM_CONF_GTBEEN_SHIFT 9 -#define FTM_CONF_GTBEOUT_MASK 0x400u -#define FTM_CONF_GTBEOUT_SHIFT 10 -/* FLTPOL Bit Fields */ -#define FTM_FLTPOL_FLT0POL_MASK 0x1u -#define FTM_FLTPOL_FLT0POL_SHIFT 0 -#define FTM_FLTPOL_FLT1POL_MASK 0x2u -#define FTM_FLTPOL_FLT1POL_SHIFT 1 -#define FTM_FLTPOL_FLT2POL_MASK 0x4u -#define FTM_FLTPOL_FLT2POL_SHIFT 2 -#define FTM_FLTPOL_FLT3POL_MASK 0x8u -#define FTM_FLTPOL_FLT3POL_SHIFT 3 -/* SYNCONF Bit Fields */ -#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u -#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 -#define FTM_SYNCONF_CNTINC_MASK 0x4u -#define FTM_SYNCONF_CNTINC_SHIFT 2 -#define FTM_SYNCONF_INVC_MASK 0x10u -#define FTM_SYNCONF_INVC_SHIFT 4 -#define FTM_SYNCONF_SWOC_MASK 0x20u -#define FTM_SYNCONF_SWOC_SHIFT 5 -#define FTM_SYNCONF_SYNCMODE_MASK 0x80u -#define FTM_SYNCONF_SYNCMODE_SHIFT 7 -#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u -#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 -#define FTM_SYNCONF_SWWRBUF_MASK 0x200u -#define FTM_SYNCONF_SWWRBUF_SHIFT 9 -#define FTM_SYNCONF_SWOM_MASK 0x400u -#define FTM_SYNCONF_SWOM_SHIFT 10 -#define FTM_SYNCONF_SWINVC_MASK 0x800u -#define FTM_SYNCONF_SWINVC_SHIFT 11 -#define FTM_SYNCONF_SWSOC_MASK 0x1000u -#define FTM_SYNCONF_SWSOC_SHIFT 12 -#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u -#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 -#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u -#define FTM_SYNCONF_HWWRBUF_SHIFT 17 -#define FTM_SYNCONF_HWOM_MASK 0x40000u -#define FTM_SYNCONF_HWOM_SHIFT 18 -#define FTM_SYNCONF_HWINVC_MASK 0x80000u -#define FTM_SYNCONF_HWINVC_SHIFT 19 -#define FTM_SYNCONF_HWSOC_MASK 0x100000u -#define FTM_SYNCONF_HWSOC_SHIFT 20 -/* INVCTRL Bit Fields */ -#define FTM_INVCTRL_INV0EN_MASK 0x1u -#define FTM_INVCTRL_INV0EN_SHIFT 0 -#define FTM_INVCTRL_INV1EN_MASK 0x2u -#define FTM_INVCTRL_INV1EN_SHIFT 1 -#define FTM_INVCTRL_INV2EN_MASK 0x4u -#define FTM_INVCTRL_INV2EN_SHIFT 2 -#define FTM_INVCTRL_INV3EN_MASK 0x8u -#define FTM_INVCTRL_INV3EN_SHIFT 3 -/* SWOCTRL Bit Fields */ -#define FTM_SWOCTRL_CH0OC_MASK 0x1u -#define FTM_SWOCTRL_CH0OC_SHIFT 0 -#define FTM_SWOCTRL_CH1OC_MASK 0x2u -#define FTM_SWOCTRL_CH1OC_SHIFT 1 -#define FTM_SWOCTRL_CH2OC_MASK 0x4u -#define FTM_SWOCTRL_CH2OC_SHIFT 2 -#define FTM_SWOCTRL_CH3OC_MASK 0x8u -#define FTM_SWOCTRL_CH3OC_SHIFT 3 -#define FTM_SWOCTRL_CH4OC_MASK 0x10u -#define FTM_SWOCTRL_CH4OC_SHIFT 4 -#define FTM_SWOCTRL_CH5OC_MASK 0x20u -#define FTM_SWOCTRL_CH5OC_SHIFT 5 -#define FTM_SWOCTRL_CH6OC_MASK 0x40u -#define FTM_SWOCTRL_CH6OC_SHIFT 6 -#define FTM_SWOCTRL_CH7OC_MASK 0x80u -#define FTM_SWOCTRL_CH7OC_SHIFT 7 -#define FTM_SWOCTRL_CH0OCV_MASK 0x100u -#define FTM_SWOCTRL_CH0OCV_SHIFT 8 -#define FTM_SWOCTRL_CH1OCV_MASK 0x200u -#define FTM_SWOCTRL_CH1OCV_SHIFT 9 -#define FTM_SWOCTRL_CH2OCV_MASK 0x400u -#define FTM_SWOCTRL_CH2OCV_SHIFT 10 -#define FTM_SWOCTRL_CH3OCV_MASK 0x800u -#define FTM_SWOCTRL_CH3OCV_SHIFT 11 -#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u -#define FTM_SWOCTRL_CH4OCV_SHIFT 12 -#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u -#define FTM_SWOCTRL_CH5OCV_SHIFT 13 -#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u -#define FTM_SWOCTRL_CH6OCV_SHIFT 14 -#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u -#define FTM_SWOCTRL_CH7OCV_SHIFT 15 -/* PWMLOAD Bit Fields */ -#define FTM_PWMLOAD_CH0SEL_MASK 0x1u -#define FTM_PWMLOAD_CH0SEL_SHIFT 0 -#define FTM_PWMLOAD_CH1SEL_MASK 0x2u -#define FTM_PWMLOAD_CH1SEL_SHIFT 1 -#define FTM_PWMLOAD_CH2SEL_MASK 0x4u -#define FTM_PWMLOAD_CH2SEL_SHIFT 2 -#define FTM_PWMLOAD_CH3SEL_MASK 0x8u -#define FTM_PWMLOAD_CH3SEL_SHIFT 3 -#define FTM_PWMLOAD_CH4SEL_MASK 0x10u -#define FTM_PWMLOAD_CH4SEL_SHIFT 4 -#define FTM_PWMLOAD_CH5SEL_MASK 0x20u -#define FTM_PWMLOAD_CH5SEL_SHIFT 5 -#define FTM_PWMLOAD_CH6SEL_MASK 0x40u -#define FTM_PWMLOAD_CH6SEL_SHIFT 6 -#define FTM_PWMLOAD_CH7SEL_MASK 0x80u -#define FTM_PWMLOAD_CH7SEL_SHIFT 7 -#define FTM_PWMLOAD_LDOK_MASK 0x200u -#define FTM_PWMLOAD_LDOK_SHIFT 9 - -/****************************************************************/ -/* */ -/* Periodic Interrupt Timer (PIT) */ -/* */ -/****************************************************************/ -/* MCR Bit Fields */ -#define PIT_MCR_FRZ 0x1u -#define PIT_MCR_MDIS 0x2u -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) -/* CVAL Bit Fields */ -#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu -#define PIT_CVAL_TVL_SHIFT 0 -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) -/* TCTRL Bit Fields */ -#define PIT_TCTRL_TEN 0x1u -#define PIT_TCTRL_TIE 0x2u -/* TFLG Bit Fields */ -#define PIT_TFLG_TIF 0x1u - -/****************************************************************/ -/* */ -/* Analog-to-Digital Converter (ADC) */ -/* */ -/****************************************************************/ -/*********** Bits definition for ADCx_SC1n register ***********/ -#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ -#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ -#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ -#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ -#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ -#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ - -/*********** Bits definition for ADCx_CFG1 register ***********/ -#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ -#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ -#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ -#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ -#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ -#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ -#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ -#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ -#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ -#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ -#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ - -/*********** Bits definition for ADCx_CFG2 register ***********/ -#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ -#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ -#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ -#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ -#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ -#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ - -/*********** Bits definition for ADCx_SC2 register ***********/ -#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ -#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ -#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ -#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ -#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ -#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ -#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ -#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ -#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ - -/*********** Bits definition for ADCx_SC3 register ***********/ -#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ -#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ -#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ -#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ -#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ -#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ -#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ - -/****************************************************************/ -/* */ -/* Low-Power Timer (LPTMR) */ -/* */ -/****************************************************************/ -/********** Bits definition for LPTMRx_CSR register ***********/ -#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ -#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ -#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ -#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ -#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ -#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ -#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ -#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ -#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ - -/********** Bits definition for LPTMRx_PSR register ***********/ -#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ -#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ -#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ -#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ -#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ -#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ -#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ - -/********** Bits definition for LPTMRx_CMR register ***********/ -#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ -#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ -#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ - -/********** Bits definition for LPTMRx_CNR register ***********/ -#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ -#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ -#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ - -/****************************************************************/ -/* */ -/* Touch Sensing Input (TSI) */ -/* */ -/****************************************************************/ -/********** Bits definition for TSIx_GENCS register ***********/ -#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ -#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ -#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ -#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ -#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ -#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ -#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ -#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ -#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ -#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ -#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ -#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ -#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ -#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ -#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ -#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ -#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ -#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ -#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ -#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ -#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ -#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ -#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ -#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ -#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ -#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ -#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ - -/********** Bits definition for TSIx_DATA register ************/ -#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ -#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ -#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ -#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ -#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ -#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ -#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ -#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ - -/********** Bits definition for TSIx_TSHD register ************/ -#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ -#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ -#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ -#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ -#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ -#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ - -/****************************************************************/ -/* */ -/* Multipurpose Clock Generator (MCG) */ -/* */ -/****************************************************************/ -/*********** Bits definition for MCG_C1 register **************/ -#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ -#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ -#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ -#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ -#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ -#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ -#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ -#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ -#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ -#define MCG_C1_IREFS ((uint8_t)0x04) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ -#define MCG_C1_IRCLKEN ((uint8_t)0x02) /*!< Internal Reference Clock Enable */ -#define MCG_C1_IREFSTEN ((uint8_t)0x01) /*!< Internal Reference Stop Enable */ - -/*********** Bits definition for MCG_C2 register **************/ -#define MCG_C2_LOCRE0 ((uint8_t)0x80) /*!< Loss of Clock Reset Enable */ -#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ -#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x3 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ -#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ -#define MCG_C2_HGO0 ((uint8_t)0x08) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ -#define MCG_C2_EREFS0 ((uint8_t)0x04) /*!< External Reference Select (0=clock; 1=oscillator) */ -#define MCG_C2_LP ((uint8_t)0x02) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ -#define MCG_C2_IRCS ((uint8_t)0x01) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ - -/*********** Bits definition for MCG_C4 register **************/ -#define MCG_C4_DMX32 ((uint8_t)0x80) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ -#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ -#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ -#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ -#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ -#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0xF << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ -#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ -#define MCG_C4_SCFTRIM ((uint8_t)0x01) /*!< Slow Internal Reference Clock Fine Trim */ - -/*********** Bits definition for MCG_C5 register **************/ -#define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) /*!< PLL Clock Enable */ -#define MCG_C5_PLLSTEN0 ((uint8_t)0x20) /*!< PLL Stop Enable */ -#define MCG_C5_PRDIV0_MASK ((uint8_t)0x1F) /*!< PLL External Reference Divider (mask) */ -#define MCG_C5_PRDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ - -/*********** Bits definition for MCG_C6 register **************/ -#define MCG_C6_LOLIE0 ((uint8_t)0x80) /*!< Loss of Lock Interrupt Enable */ -#define MCG_C6_PLLS ((uint8_t)0x40) /*!< PLL Select */ -#define MCG_C6_CME0 ((uint8_t)0x20) /*!< Clock Monitor Enable */ -#define MCG_C6_VDIV0_MASK ((uint8_t)0x1F) /*!< VCO 0 Divider (mask) */ -#define MCG_C6_VDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ - -/************ Bits definition for MCG_S register **************/ -#define MCG_S_LOLS ((uint8_t)0x80) /*!< Loss of Lock Status */ -#define MCG_S_LOCK0 ((uint8_t)0x40) /*!< Lock Status */ -#define MCG_S_PLLST ((uint8_t)0x20) /*!< PLL Select Status */ -#define MCG_S_IREFST ((uint8_t)0x10) /*!< Internal Reference Status */ -#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ -#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x3 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ -#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ -#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ -#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ -#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ -#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ -#define MCG_S_OSCINIT0 ((uint8_t)0x02) /*!< OSC Initialization */ -#define MCG_S_IRCST ((uint8_t)0x01) /*!< Internal Reference Clock Status */ - -/************ Bits definition for MCG_SC register **************/ -#define MCG_SC_ATME ((uint8_t)0x80) /*!< Automatic Trim Machine Enable */ -#define MCG_SC_ATMS ((uint8_t)0x40) /*!< Automatic Trim Machine Select */ -#define MCG_SC_ATMF ((uint8_t)0x20) /*!< Automatic Trim Machine Fail Flag */ -#define MCG_SC_FLTPRSRV ((uint8_t)0x10) /*!< FLL Filter Preserve Enable */ -#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ -#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ -#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ -#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ -#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ -#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ -#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ -#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ -#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ -#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ -#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ -#define MCG_SC_LOCS0 ((uint8_t)0x01) /*!< OSC0 Loss of Clock Status */ - -/************ Bits definition for MCG_C7 register **************/ -#define MCG_C7_OSCSEL ((uint8_t)0x01) /*!< MCG OSC Clock Select */ - -/************ Bits definition for MCG_C8 register **************/ -#define MCG_C8_LOCRE1 ((uint8_t)0x80) /*!< PLL Loss of Clock Reset Enable */ -#define MCG_C8_LOLRE ((uint8_t)0x40) /*!< PLL Loss of Lock Reset Enable */ -#define MCG_C8_CME1 ((uint8_t)0x20) /*!< PLL Clock Monitor Enable */ -#define MCG_C8_LOCS1 ((uint8_t)0x01) /*!< RTC Loss of Clock Status */ - -/****************************************************************/ -/* */ -/* Serial Peripheral Interface (SPI) */ -/* */ -/****************************************************************/ - -/*********** Bits definition for SPIx_MCR register *************/ -#define SPIx_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select -#define SPIx_MCR_CONT_SCKE ((uint32_t)0x40000000) // Continuous SCK Enable -#define SPIx_MCR_DCONF(n) (((n) & 3) << 28) // DSPI Configuration -#define SPIx_MCR_FRZ ((uint32_t)0x08000000) // Freeze -#define SPIx_MCR_MTFE ((uint32_t)0x04000000) // Modified Timing Format Enable -#define SPIx_MCR_ROOE ((uint32_t)0x01000000) // Receive FIFO Overflow Overwrite Enable -#define SPIx_MCR_PCSIS(n) (((n) & 0x1F) << 16) // Peripheral Chip Select x Inactive State -#define SPIx_MCR_DOZE ((uint32_t)0x00008000) // Doze Enable -#define SPIx_MCR_MDIS ((uint32_t)0x00004000) // Module Disable -#define SPIx_MCR_DIS_TXF ((uint32_t)0x00002000) // Disable Transmit FIFO -#define SPIx_MCR_DIS_RXF ((uint32_t)0x00001000) // Disable Receive FIFO -#define SPIx_MCR_CLR_TXF ((uint32_t)0x00000800) // Clear the TX FIFO and counter -#define SPIx_MCR_CLR_RXF ((uint32_t)0x00000400) // Clear the RX FIFO and counter -#define SPIx_MCR_SMPL_PT(n) (((n) & 3) << 8) // Sample Point -#define SPIx_MCR_HALT ((uint32_t)0x00000001) // Halt - -/*********** Bits definition for SPIx_TCR register *************/ -#define SPIx_TCR_TCNT(n) (((n) & 0xffff) << 16) // DSPI Transfer Count Register - -/*********** Bits definition for SPIx_CTARn register *************/ -#define SPIx_CTARn_DBR ((uint32_t)0x80000000) // Double Baud Rate -#define SPIx_CTARn_FMSZ_SHIFT 27 // Frame Size Shift -#define SPIx_CTARn_FMSZ_MASK 0xF // Frame Size Mask -#define SPIx_CTARn_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) -#define SPIx_CTARn_CPOL ((uint32_t)0x04000000) // Clock Polarity -#define SPIx_CTARn_CPHA ((uint32_t)0x02000000) // Clock Phase -#define SPIx_CTARn_LSBFE ((uint32_t)0x01000000) // LSB First -#define SPIx_CTARn_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler -#define SPIx_CTARn_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler -#define SPIx_CTARn_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler -#define SPIx_CTARn_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler -#define SPIx_CTARn_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler -#define SPIx_CTARn_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler -#define SPIx_CTARn_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler -#define SPIx_CTARn_BR(n) (((n) & 15) << 0) // Baud Rate Scaler - - -/*********** Bits definition for SPIx_CTARn_SLAVE register *************/ -#define SPIx_CTARn_SLAVE_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) -#define SPIx_CTARn_SLAVE_CPOL ((uint32_t)0x04000000) // Clock Polarity -#define SPIx_CTARn_SLAVE_CPHA ((uint32_t)0x02000000) // Clock Phase - -/*********** Bits definition for SPIx_SR register *************/ -#define SPIx_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag -#define SPIx_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status -#define SPIx_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag -#define SPIx_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag -#define SPIx_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag -#define SPIx_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag -#define SPIx_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag -#define SPIx_SR_TXCTR (((n) & 15) << 12) // TX FIFO Counter -#define SPIx_SR_TXNXPTR (((n) & 15) << 8) // Transmit Next Pointer -#define SPIx_SR_RXCTR (((n) & 15) << 4) // RX FIFO Counter -#define SPIx_SR_POPNXTPTR ((n) & 15) // POP Next Pointer - -/*********** Bits definition for SPIx_SR register *************/ -#define SPIx_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable -#define SPIx_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable -#define SPIx_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable -#define SPIx_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable -#define SPIx_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select -#define SPIx_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable -#define SPIx_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable -#define SPIx_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select - -/*********** Bits definition for SPIx_PUSHR register *************/ -#define SPIx_PUSHR_CONT ((uint32_t)0x80000000) // Continuous Peripheral Chip Select Enable -#define SPIx_PUSHR_CTAS(n) (((n) & 7) << 28) // Clock and Transfer Attributes Select -#define SPIx_PUSHR_EOQ ((uint32_t)0x08000000) // End Of Queue -#define SPIx_PUSHR_CTCNT ((uint32_t)0x04000000) // Clear Transfer Counter -#define SPIx_PUSHR_PCS(n) (((n) & 31) << 16) // Peripheral Chip Select -#define SPIx_PUSHR_TXDATA(n) ((n) & 0xffff) // Transmit Data - -/*********** Bits definition for SPIx_PUSHR_SLAVE register *************/ -#define SPIx_PUSHR_SLAVE_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data in slave mode - -/*********** Bits definition for SPIx_POPR register *************/ -#define SPIx_POPR_RXDATA(n) (((n) & 0xffff) << 16) // Received Data - -/*********** Bits definition for SPIx_TXFRn register *************/ -#define SPIx_TXFRn_TXCMD_TXDATA (((n) & 0xffff) << 16) // Transmit Command (in master mode) -#define SPIx_TXFRn_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data - -/*********** Bits definition for SPIx_RXFRn register *************/ -#define SPIx_RXFRn_RXDATA(n) (((n) & 0xffff) << 0) // Receive Data - -/****************************************************************/ -/* */ -/* Inter-Integrated Circuit (I2C) */ -/* */ -/****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ - -#define I2Cx_A1_AD_SHIT 1 - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ - -#define I2Cx_F_MULT_SHIFT 5 - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S register **************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ - -/*********** Bits definition for I2Cx_FLT register ************/ -#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ -#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ -#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ -#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ - -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ - -#define I2Cx_RA_RAD_SHIFT 1 - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ - -#define I2Cx_A2_SAD_SHIFT 1 - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ - -/****************************************************************/ -/* */ -/* Universal Asynchronous Receiver/Transmitter (UART) */ -/* */ -/****************************************************************/ -/********* Bits definition for UARTx_BDH register *************/ -#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ -#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RxD Input Active Edge Interrupt Enable */ -#define UARTx_BDH_SBR_MASK ((uint8_t)0x1F) -#define UARTx_BDH_SBR(x) ((uint8_t)((uint8_t)(x) & UARTx_BDH_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ - -/********* Bits definition for UARTx_BDL register *************/ -#define UARTx_BDL_SBR_MASK ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ - -/********* Bits definition for UARTx_C1 register **************/ -#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ -#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ -#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ -#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ -#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ -#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ -#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ -#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ -#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ - -/********* Bits definition for UARTx_C2 register **************/ -#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ -#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ -#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ -#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ -#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ -#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ -#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ -#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ - -/********* Bits definition for UARTx_S1 register **************/ -#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ -#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ -#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ -#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ -#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ -#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ -#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ -#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ - -/********* Bits definition for UARTx_S2 register **************/ -#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ -#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ -#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ -#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ -#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ -#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ -#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ -#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ - -/********* Bits definition for UARTx_C3 register **************/ -#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ -#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ -#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ -#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ -#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ -#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ -#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ -#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ - -/********* Bits definition for UARTx_D register ***************/ -#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ -#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ -#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ -#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ -#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ -#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ -#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ -#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ - -/********* Bits definition for UARTx_MA1 register *************/ -#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ - -/********* Bits definition for UARTx_MA2 register *************/ -#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ - -/********* Bits definition for UARTx_C4 register **************/ -#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ -#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ -#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ -#define UARTx_C4_BRFA_MASK ((uint8_t)0x1F) -#define UARTx_C4_BRFA(x) ((uint8_t)((uint8_t)(x) & UARTx_C4_BRFA_MASK)) /*!< Baud Rate Fine Adjust */ - -/********* Bits definition for UARTx_C5 register **************/ -#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ -#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ -#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ -#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ - -/******* Bits definition for UARTx_CFIFO register ************/ -#define UARTx_CFIFO_TXFLUSH ((uint8_t)0x80) /*!< Transmit FIFO/Buffer Flush */ -#define UARTx_CFIFO_RXFLUSH ((uint8_t)0x40) /*!< Receive FIFO/Buffer Flush */ -#define UARTx_CFIFO_RXOFE ((uint8_t)0x04) /*!< Receive FIFO Overflow Interrupt Enable */ -#define UARTx_CFIFO_TXOFE ((uint8_t)0x02) /*!< Transmit FIFO Overflow Interrupt Enable */ -#define UARTx_CFIFO_RXUFE ((uint8_t)0x01) /*!< Receive FIFO Underflow Interrupt Enable */ - -/******* Bits definition for UARTx_PFIFO register ************/ -#define UARTx_PFIFO_TXFE ((uint8_t)0x80) /*!< Transmit FIFO Enable */ -#define UARTx_PFIFO_TXFIFOSIZE_SHIFT 4 -#define UARTx_PFIFO_TXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_TXFIFOSIZE_SHIFT)) -#define UARTx_PFIFO_TXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_TXFIFOSIZE_SHIFT) & UARTx_PFIFO_TXFIFOSIZE_MASK)) /*!< Transmit FIFO Buffer depth */ -#define UARTx_PFIFO_RXFE ((uint8_t)0x08) /*!< Receive FIFOh */ -#define UARTx_PFIFO_RXFIFOSIZE_SHIFT 0 -#define UARTx_PFIFO_RXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_RXFIFOSIZE_SHIFT)) -#define UARTx_PFIFO_RXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_RXFIFOSIZE_SHIFT) & UARTx_PFIFO_RXFIFOSIZE_MASK)) /*!< Receive FIFO Buffer depth */ - -/****************************************************************/ -/* */ -/* Power Management Controller (PMC) */ -/* */ -/****************************************************************/ -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ -#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ -#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ -#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ -#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ -#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ -#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ -#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ -#define PMC_LVDSC2_LVWV_SHIFT 0 -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) -/********* Bits definition for PMC_REGSC register *************/ -#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ -#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ -#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ -#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ - -/****************************************************************/ -/* */ -/* Watchdog */ -/* */ -/****************************************************************/ -/******** Bits definition for WDOG_STCTRLH register ***********/ -#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) -#define WDOG_STCTRLH_BYTESEL_1_0 ((uint16_t)0x3000) -#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800) -#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400) -#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080) -#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040) -#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020) -#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010) -#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008) -#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004) -#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002) -#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001) - -/******** Bits definition for WDOG_STCTRLL register ***********/ -#define WDOG_STCTRLL_INTFLG ((uint16_t)0x8000) - -/********* Bits definition for WDOG_PRESC register ************/ -#define WDOG_PRESC_PRESCVAL ((uint16_t)0x0700) - -/****************************************************************/ -/* */ -/* USB OTG */ -/* */ -/****************************************************************/ -/******** Bits definition for USBx_ISTAT register *************/ -#define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ -#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ -#define USBx_ISTAT_RESUME ((uint8_t)0x20) /*!< Signal remote wakeup on the bus */ -#define USBx_ISTAT_SLEEP ((uint8_t)0x10) /*!< Detected bus idle for 3ms */ -#define USBx_ISTAT_TOKDNE ((uint8_t)0x08) /*!< Completed processing of current token */ -#define USBx_ISTAT_SOFTOK ((uint8_t)0x04) /*!< Received start of frame */ -#define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ -#define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ - -/******** Bits definition for USBx_ERRSTAT register ***********/ -#define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ -#define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ -#define USBx_ERRSTAT_BTOERR ((uint8_t)0x10) /*!< BUS turnaround timeout error */ -#define USBx_ERRSTAT_DFN8 ((uint8_t)0x08) /*!< Received data not 8-bit sized */ -#define USBx_ERRSTAT_CRC16 ((uint8_t)0x04) /*!< Packet with CRC16 error */ -#define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ -#define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ - -/******** Bits definition for USBx_CTL register *****************/ -#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ -#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ -#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */ -#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ -#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ -#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ -#define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ -#define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ - -/******** Bits definition for USBx_INTEN register ***************/ -#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ -#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ -#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ -#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ -#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ -#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ -#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ -#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ - -/******** Bits definition for USBx_ENDPTn register **************/ -#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) -#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) -#define USBx_ENDPTn_EPCTLDIS ((uint8_t)0x10) /*!< Disables control transfers */ -#define USBx_ENDPTn_EPRXEN ((uint8_t)0x08) /*!< Enable RX transfers */ -#define USBx_ENDPTn_EPTXEN ((uint8_t)0x04) /*!< Enable TX transfers */ -#define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ -#define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ - -/******** Bits definition for USBx_CTRL register ****************/ -#define USBx_CTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ -#define USBx_CTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ - -/******** Bits definition for USBx_USBTRC0 register *************/ -#define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ -#define USBx_USBTRC0_USBRESMEN ((uint8_t)0x20) /*!< Asynchronous resume interrupt enable */ -#define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ -#define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ - -/******** Bits definition for USBx_CONTROL register *************/ -#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ - -#endif diff --git a/os/hal/ports/KINETIS/K20x/platform.mk b/os/hal/ports/KINETIS/K20x/platform.mk index 20502c2..baa90a2 100644 --- a/os/hal/ports/KINETIS/K20x/platform.mk +++ b/os/hal/ports/KINETIS/K20x/platform.mk @@ -1,14 +1,16 @@ # List of all platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/st_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/pwm_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/KINETIS/K20x/pwm_lld.c b/os/hal/ports/KINETIS/K20x/pwm_lld.c new file mode 100644 index 0000000..f5a8d96 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pwm_lld.c @@ -0,0 +1,390 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer FTM0 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer FTM1 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer FTM2 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->ftm->SC;
+ pwmp->ftm->SC = sr&(~FTM_SC_TOF);
+
+ if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
+ ((sr & FTM_SC_TOIE) != 0) &&
+ (pwmp->config->callback != NULL)) {
+ pwmp->config->callback(pwmp);
+ }
+
+ uint8_t n=0;
+ for(n=0;n<pwmp->channels;n++) {
+ sr = pwmp->ftm->CHANNEL[n].CnSC;
+ pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
+ if (((sr & FTM_CnSC_CHF) != 0) &&
+ ((sr & FTM_CnSC_CHIE) != 0) &&
+ (pwmp->config->channels[n].callback != NULL)) {
+ pwmp->config->channels[n].callback(pwmp);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0
+/**
+ * @brief FTM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM0 */
+
+#if KINETIS_PWM_USE_FTM1
+/**
+ * @brief FTM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM1 */
+
+#if KINETIS_PWM_USE_FTM2
+/**
+ * @brief FTM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_FTM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_FTM0_CHANNELS;
+ PWMD1.ftm = FTM0;
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_FTM1_CHANNELS;
+ PWMD2.ftm = FTM1;
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_FTM2_CHANNELS;
+ PWMD3.ftm = FTM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint16_t psc;
+ uint8_t i=0;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM0;
+ nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM1;
+ nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 |= SIM_SCGC3_FTM2;
+ nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
+ }
+#endif
+ }
+ pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
+ pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
+ |FTM_SYNC_SWSYNC_MASK;
+ pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
+ | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
+ pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
+
+ pwmp->ftm->CNTIN = 0x0000;
+ //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
+ pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ //~ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ //~ /* Prescaler register value determination.
+ //~ Prescaler register value conveniently corresponds to bit position,
+ //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (unsigned)(1 << i)) {
+ break;
+ }
+ }
+
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWMS up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
+ /* Configure period */
+ pwmp->ftm->MOD = pwmp->period-1;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
+ nvicDisableVector(FTM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
+ nvicDisableVector(FTM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
+ nvicDisableVector(FTM2_IRQn);
+ }
+#endif
+ /* Disable FTM counter.*/
+ pwmp->ftm->SC = 0;
+ pwmp->ftm->MOD = 0;
+ }
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= FTM_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= FTM_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
+ mode |= FTM_CnSC_CHIE;
+
+ pwmp->ftm->CHANNEL[channel].CnSC = mode;
+ pwmp->ftm->CHANNEL[channel].CnV = width;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->ftm->CHANNEL[channel].CnSC = 0;
+ pwmp->ftm->CHANNEL[channel].CnV = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC |= FTM_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC &= ~FTM_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/pwm_lld.h b/os/hal/ports/KINETIS/K20x/pwm_lld.h new file mode 100644 index 0000000..176e8a8 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pwm_lld.h @@ -0,0 +1,270 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x7/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_FTM0)
+ #define KINETIS_PWM_USE_FTM0 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM1)
+ #define KINETIS_PWM_USE_FTM1 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM2)
+ #define KINETIS_PWM_USE_FTM2 FALSE
+#endif
+
+/**
+ * @brief FTM0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM0_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM1_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM2_PRIORITY 12
+#endif
+
+/** @} */
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
+#error "PWM driver activated but no FTM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the FTM registers block.
+ */
+ FTM_TypeDef *ftm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ do { \
+ (pwmp)->ftm->MOD = ((period) - 1); \
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+ } while(0)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.c b/os/hal/ports/KINETIS/K20x/serial_lld.c deleted file mode 100644 index 0092747..0000000 --- a/os/hal/ports/KINETIS/K20x/serial_lld.c +++ /dev/null @@ -1,327 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/serial_lld.c
- * @brief Kinetis K20x Serial Driver subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "mk20d5.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SD1 driver identifier.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- 38400
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] u pointer to an UART I/O block
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- UART_TypeDef *u = sdp->uart;
- uint8_t s1 = u->S1;
-
- if (s1 & UARTx_S1_RDRF) {
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if (s1 & UARTx_S1_TDRE) {
- msg_t b;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- u->C2 &= ~UARTx_C2_TIE;
- } else {
- u->D = b;
- }
- }
-}
-
-/**
- * @brief Attempts a TX preload
- */
-static void preload(SerialDriver *sdp) {
- UART_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b = oqGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- return;
- }
- u->D = b;
- u->C2 |= UARTx_C2_TIE;
- }
-}
-
-/**
- * @brief Driver output notification.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD1);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
-}
-#endif
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(UART_TypeDef *uart, const SerialConfig *config)
-{
- uint32_t divisor = (KINETIS_SYSCLK_FREQUENCY * 2 + 1) / config->sc_speed;
-
- /* Disable UART while configuring */
- uart->C2 &= ~(UARTx_C2_RE | UARTx_C2_TE);
- uart->C1 = 0;
-
- uart->BDH = UARTx_BDH_SBR(divisor >> 13) | (uart->BDH & ~UARTx_BDH_SBR_MASK);
- uart->BDL = divisor >> 5;
- uart->C4 = UARTx_C4_BRFA(divisor) | (uart->C4 & ~UARTx_C4_BRFA_MASK);
-
- uart->C2 |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
- uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/* TODO:
- * UART0_Error is Vector84
- * UART1_Error is Vector8C
- * UART2_Error is Vector94
- */
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector80) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector88) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector90) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if KINETIS_SERIAL_USE_UART0
- /* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
- SD1.uart = UART0;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- /* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
- SD2.uart = UART1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart = UART2;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- SIM->SCGC4 |= SIM_SCGC4_UART0;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- SIM->SCGC4 |= SIM_SCGC4_UART1;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- SIM->SCGC4 |= SIM_SCGC4_UART2;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART2 */
-
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- /* TODO: Resets the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- nvicDisableVector(UART0Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART0;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- nvicDisableVector(UART1Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART1;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- nvicDisableVector(UART2Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART2;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.h b/os/hal/ports/KINETIS/K20x/serial_lld.h deleted file mode 100644 index 736cfe3..0000000 --- a/os/hal/ports/KINETIS/K20x/serial_lld.h +++ /dev/null @@ -1,163 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/serial_lld.h
- * @brief Kinetis K20x Serial Driver subsystem low level driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART0 FALSE
-#endif
-/**
- * @brief SD2 driver enable switch.
- * @details If set to @p TRUE the support for SD2 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART1 FALSE
-#endif
-/**
- * @brief SD3 driver enable switch.
- * @details If set to @p TRUE the support for SD3 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART2 FALSE
-#endif
-
-/**
- * @brief UART0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART0_PRIORITY 12
-#endif
-
-/**
- * @brief UART1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART1_PRIORITY 12
-#endif
-
-/**
- * @brief UART2 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART2_PRIORITY 12
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t sc_speed;
- /* End of the mandatory fields.*/
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- input_queue_t iqueue; \
- /* Output queue.*/ \
- output_queue_t oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the UART registers block.*/ \
- UART_TypeDef *uart;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.c b/os/hal/ports/KINETIS/K20x/spi_lld.c index 132580f..29ab4e8 100644 --- a/os/hal/ports/KINETIS/K20x/spi_lld.c +++ b/os/hal/ports/KINETIS/K20x/spi_lld.c @@ -30,10 +30,6 @@ /* Driver local definitions. */
/*===========================================================================*/
-#if !defined(KINETIS_SPI_USE_SPI0)
-#define KINETIS_SPI_USE_SPI0 TRUE
-#endif
-
#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
#endif
@@ -54,8 +50,35 @@ #define KINETIS_SPI0_TX_DMA_CHANNEL 1
#endif
+#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
+#define KINETIS_SPI1_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
+#define KINETIS_SPI1_TX_DMA_CHANNEL 1
+#endif
+
+#if KINETIS_SPI_USE_SPI0
#define DMAMUX_SPI_RX_SOURCE 16
#define DMAMUX_SPI_TX_SOURCE 17
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+#define DMAMUX_SPI_RX_SOURCE 18
+#define DMAMUX_SPI_TX_SOURCE 19
+#endif
/*===========================================================================*/
/* Driver exported variables. */
@@ -66,6 +89,11 @@ SPIDriver SPID1;
#endif
+/** @brief SPI1 driver identifier.*/
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -137,7 +165,9 @@ static void spi_stop_xfer(SPIDriver *spip) /* Driver interrupt handlers. */
/*===========================================================================*/
-OSAL_IRQ_HANDLER(Vector40) {
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
/* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
@@ -150,6 +180,25 @@ OSAL_IRQ_HANDLER(Vector40) { OSAL_IRQ_EPILOGUE();
}
+#endif
+
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID2);
+
+ _spi_isr_code(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -163,6 +212,9 @@ void spi_lld_init(void) { #if KINETIS_SPI_USE_SPI0
spiObjectInit(&SPID1);
#endif
+#if KINETIS_SPI_USE_SPI1
+ spiObjectInit(&SPID2);
+#endif
}
/**
@@ -193,6 +245,22 @@ void spi_lld_start(SPIDriver *spip) { }
#endif
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI1;
+
+ SPID2.spi = SPI1;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
@@ -201,6 +269,7 @@ void spi_lld_start(SPIDriver *spip) { /* Clear DMA error flags */
DMA->ERR = 0x0F;
+#if KINETIS_SPI_USE_SPI0
/* Rx, select SPI Rx FIFO */
DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
@@ -239,6 +308,48 @@ void spi_lld_start(SPIDriver *spip) { DMA_ATTR_DSIZE(dma_size);
DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
}
}
@@ -264,10 +375,20 @@ void spi_lld_stop(SPIDriver *spip) { /* SPI halt.*/
spip->spi->MCR |= SPIx_MCR_HALT;
}
-#endif
/* Disable the clock for SPI0 */
SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI1 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
+#endif
}
}
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.h b/os/hal/ports/KINETIS/K20x/spi_lld.h index 23c6812..a1f2a99 100644 --- a/os/hal/ports/KINETIS/K20x/spi_lld.h +++ b/os/hal/ports/KINETIS/K20x/spi_lld.h @@ -55,17 +55,39 @@ #define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
#endif
+/**
+ * @brief SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief SPI1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
-#define KINETIS_HAS_SPI0 TRUE
-
#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
#error "SPI0 not present in the selected device"
#endif
-#if !KINETIS_SPI_USE_SPI0
+#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
+#error "Only one SPI peripheral can be enabled"
+#endif
+
+#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
#error "SPI driver activated but no SPI peripheral assigned"
#endif
@@ -74,6 +96,11 @@ #error "Invalid IRQ priority assigned to SPI0"
#endif
+#if KINETIS_SPI_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -205,6 +232,10 @@ struct SPIDriver { extern SPIDriver SPID1;
#endif
+#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.c b/os/hal/ports/KINETIS/K20x/st_lld.c deleted file mode 100644 index 1f8cb63..0000000 --- a/os/hal/ports/KINETIS/K20x/st_lld.c +++ /dev/null @@ -1,98 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/KL2x/st_lld.c
- * @brief ST Driver subsystem low level driver code.
- *
- * @addtogroup ST
- * @{
- */
-
-#include "hal.h"
-
-#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
-/**
- * @brief System Timer vector.
- * @details This interrupt is used for system tick in periodic mode.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(SysTick_Handler) {
-
- OSAL_IRQ_PROLOGUE();
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ST driver initialization.
- *
- * @notapi
- */
-void st_lld_init(void) {
-#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
- /* Periodic systick mode, the Cortex-Mx internal systick timer is used
- in this mode.*/
- SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* IRQ enabled.*/
- nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-}
-
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.c b/os/hal/ports/KINETIS/KL2x/hal_lld.c index dce1588..77addf0 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_lld.c +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.c @@ -40,7 +40,7 @@ #ifdef __CC_ARM
__attribute__ ((section(".ARM.__at_0x400")))
#else
-__attribute__ ((used, section(".cfmconfig")))
+__attribute__ ((used,section(".cfmconfig")))
#endif
const uint8_t _cfm[0x10] = {
0xFF, /* NV_BACKKEY3: KEY=0xFF */
@@ -55,9 +55,20 @@ const uint8_t _cfm[0x10] = { 0xFF, /* NV_FPROT2: PROT=0xFF */
0xFF, /* NV_FPROT1: PROT=0xFF */
0xFF, /* NV_FPROT0: PROT=0xFF */
+#if defined(KINETIS_NV_FSEC_BYTE)
+ #warning Please triple check your FSEC setting: KEYEN!=b10, MEEN==b10, SEC!=b10 leads to an unmodifiable chip.
+ KINETIS_NV_FSEC_BYTE,
+#else /* KINETIS_NV_FSEC_BYTE */
0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+#endif /* KINETIS_NV_FSEC_BYTE */
+#if defined(KINETIS_NV_FOPT_BYTE)
+ KINETIS_NV_FOPT_BYTE,
+#else /* KINETIS_NV_FOPT_BYTE */
0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ /* on KL27: bit7-6:BOOTSRC_SEL=0b11 (11=from ROM; 00=from FLASH)
+ bit1:BOOTPIN_OPT=1 (NMI pin not sampled at boot) */
+#endif /* KINETIS_NV_FOPT_BYTE */
0xFF,
0xFF
};
@@ -91,6 +102,7 @@ void hal_lld_init(void) { */
void kl2x_clock_init(void) {
#if !KINETIS_NO_INIT
+
/* Disable COP watchdog */
SIM->COPC = 0;
@@ -107,16 +119,118 @@ void kl2x_clock_init(void) { /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
+#if KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_LIRC8M
+ /* Out of reset, the MCU is in LIRC8M mode. */
+ /* Except when coming out of the ROM bootloader, then
+ * the MCU is in HIRC mode; so better set it explicitly here. */
+
+ /* Switching to LIRC8M mode, page 414 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_C2[IRCS] to select LIRC 8M. */
+ MCG->C2 |= MCG_C2_IRCS;
+
+ /* (2) Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional). */
+ MCG->C1 |= MCG_C1_IRCLKEN;
+
+ /* (2) Write 01b to MCG_C1[CLKS] to select LIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_LIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm LIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_LIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_HIRC
+ /* Switching to HIRC mode, page 413 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_MC[HIRCEN] to enable HIRC (optional). */
+ MCG->MC |= MCG_MC_HIRCEN;
+
+ /* (2) Write 00b to MCG_C1[CLKS] to select HIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_HIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm HIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_EXT
+ /* Assuming we have an external crystal, frequency
+ * specified with KINETIS_XTAL_FREQUENCY.
+ *
+ * Note: Except with 32768 kHz crystal (low-freq mode),
+ * external load capacitors and a feedback resistor
+ * are *required*. Additionally, a series resistor is
+ * required in the high-gain mode, and forbidden in
+ * the low-power mode.
+ * In this case, the internal caps can be configured
+ * via KINETIS_BOARD_OSCILLATOR_SETTING.
+ * (Page 420 of the KL27 manual.) */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* Switching to EXT mode, page 413 of the KL27 manual. */
+
+ /* (1) Configure MCG_C2[EREFS0] for external clock source selection. */
+ #if KINETIS_XTAL_FREQUENCY == 32768 /* low range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(0);
+ #elif (KINETIS_XTAL_FREQUENCY >= 1000000 && \
+ KINETIS_XTAL_FREQUENCY <= 8000000) /* high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(1);
+ #elif (KINETIS_XTAL_FREQUENCY > 8000000 && \
+ KINETIS_XTAL_FREQUENCY <= 32000000) /* very high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(2);
+ #else /* KINETIS_XTAL_FREQUENCY == */
+ #error KINETIS_XTAL_FREQUENCY not in allowed range
+ #endif /* KINETIS_XTAL_FREQUENCY == */
+
+ #if defined(KINETIS_XTAL_HIGH_GAIN) && KINETIS_XTAL_HIGH_GAIN
+ MCG->C2 |= MCG_C2_HGO0;
+ #endif /* KINETIS_XTAL_HIGH_GAIN */
+
+ /* Oscillator requested. */
+ MCG->C2 |= MCG_C2_EREFS0;
+
+ /* (2) Write 10b to MCG_C1[CLKS] to select external clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_EXT;
+
+ /* (3) Check MCG_S[CLKST] to confirm external clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT )
+ ;
+
+#else /* KINETIS_MCGLITE_MODE */
+#error Unimplemented KINETIS_MCGLITE_MODE
+#endif /* KINETIS_MCGLITE_MODE */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
+
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
/* This is the default mode at reset. */
/* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
* OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 24 MHz */
- SIM_CLKDIV1_OUTDIV4(0); /* OUTDIV4 = divide-by-1 => 24 MHz */
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
+ /* TODO: check this, for generality */
/*
* FLL Enabled External (FEE) MCG Mode
* 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
@@ -138,14 +252,20 @@ void kl2x_clock_init(void) { * OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(KINETIS_MCG_FLL_OUTDIV1 - 1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_MCG_FLL_OUTDIV4 - 1);
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FEE mode: */
@@ -183,35 +303,40 @@ void kl2x_clock_init(void) { seems to omit it. */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
/*
* PLL Enabled External (PEE) MCG Mode
- * 48 MHz core, 24 MHz bus - using 8 MHz crystal with PLL.
+ * Uses external crystal (KINETIS_XTAL_FREQUENCY) with PLL.
* f_MCGOUTCLK = (OSCCLK / PLL_R) * M
- * = 8 MHz / 2 * 24 = 96 MHz
+ * OSCCLK = KINETIS_XTAL_FREQUENCY
* PLL_R is the reference divider selected by C5[PRDIV0]
+ * (OSCCLK/PLL_R must be between 2 and 4 MHz)
* M is the multiplier selected by C6[VDIV0]
*
+ * Running from PLL, so assuming PLLCLK = MCGOUTCLK.
+ *
* Then the core/system and bus/flash clocks are divided:
* f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
* f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
*/
- /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
- * OUTDIV1 (divider for core/system and bus/flash clock)
- * OUTDIV4 (additional divider for bus/flash clock) */
- SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 48 MHz */
- SIM_CLKDIV1_OUTDIV4(1); /* OUTDIV4 = divide-by-2 => 24 MHz */
-
- SIM->SOPT2 =
- SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
- SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
-
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+ /* Start in FEI mode */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FBE mode: */
@@ -220,15 +345,27 @@ void kl2x_clock_init(void) { resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
Use high-gain mode by setting C2[HGO0] instead if external
feedback resistor Rf is installed. */
- MCG->C2 =
- MCG_C2_RANGE0(2) | /* very high frequency range */
- MCG_C2_EREFS0; /* external reference (using a crystal) */
+ MCG->C2 = MCG_C2_EREFS0; /* external reference (using a crystal) */
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 |= MCG_C2_RANGE0(2);
+ else
+ MCG->C2 |= MCG_C2_RANGE0(1);
/* (2) Write to C1 to select the clock mode. */
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
- MCG_C1_CLKS_ERCLK | /* Use ERCLK for system clock, MCGCLKOUT. */
- MCG_C1_FRDIV(3); /* Divide ERCLK / 256 for FLL reference. */
- /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz.
- 8 MHz / 256 = 31.25 kHz. */
+ MCG_C1_CLKS_ERCLK | /* Use Ext Ref Clock for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(frdiv); /* Divide ERCLK / 256 for FLL reference. */
+ /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz. */
+
MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
@@ -254,11 +391,25 @@ void kl2x_clock_init(void) { /* (2) Then configure C5[PRDIV0] to generate the
correct PLL reference frequency. */
- MCG->C5 = MCG_C5_PRDIV0(1); /* PLL External Reference Divide by 2 */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */
+ /* PLL External Reference Divide by ... */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
/* (3) Then from FBE transition to PBE mode. */
/* (3)(b) C6[PLLS]=1 to select PLL. */
- /* (3)(b) C6[VDIV0]=5'b0000 (x24) 2 MHz * 24 = 48 MHz. */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /* (3)(b) C6[VDIV0]= PLLIN MHz * i = PLLCLK MHz. */
+ /* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match */
+ for(i = 24; i < 56; i++) {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY)) {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
/* (3)(d) Loop until S[PLLST], indicating PLL
is the PLLS clock source. */
while ((MCG->S & MCG_S_PLLST) == 0)
@@ -270,14 +421,26 @@ void kl2x_clock_init(void) { /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
+ /* Set the PLL dividers for the different clocks */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock)
+ * - these are computed in .h */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
+
/* (4) Transition from PBE mode to PEE mode. */
/* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
// Switch to PEE mode
// Select PLL output (CLKS=0)
- // FLL external reference divider (FRDIV=3)
+ // FLL external reference divider (FRDIV) already set
// External reference clock for FLL (IREFS=0)
- MCG->C1 = MCG_C1_CLKS(0) |
- MCG_C1_FRDIV(3);
+ MCG->C1 = MCG_C1_CLKS(0);
/* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
; /* wait until clock switched to PLL output */
@@ -288,6 +451,8 @@ void kl2x_clock_init(void) { #error Unimplemented KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+#endif /* KINETIS_HAS_MCG_LITE */
+
#endif /* !KINETIS_NO_INIT */
}
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.h b/os/hal/ports/KINETIS/KL2x/hal_lld.h index f93d920..a10c21c 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_lld.h +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.h @@ -25,7 +25,7 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-#include "kl25z.h"
+#include "kl2xz.h"
#include "kinetis_registry.h"
/*===========================================================================*/
@@ -44,15 +44,30 @@ #define PLATFORM_NAME "Kinetis"
/** @} */
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
/**
- * @brief Maximum system and core clock (f_SYS) frequency.
+ * @name Internal clock sources
+ * @{
*/
-#define KINETIS_SYSCLK_MAX 48000000
+#define KINETIS_HIRC 48000000 /**< High-frequency internal reference clock (USB recovery). */
+#define KINETIS_LIRC_8 8000000 /**< Low-frequency internal reference clock (faster). */
+#define KINETIS_LIRC_2 2000000 /**< Low-frequency internal reference clock (slower). */
+/** @} */
/**
- * @brief Maximum bus clock (f_BUS) frequency.
+ * @name MCG modes of operation
+ * @{
*/
-#define KINETIS_BUSCLK_MAX 24000000
+#define KINETIS_MCGLITE_MODE_LIRC8M 1 /**< Low frequency internal reference mode (8MHz). */
+#define KINETIS_MCGLITE_MODE_LIRC2M 2 /**< Low frequency internal reference mode (2MHz). */
+#define KINETIS_MCGLITE_MODE_HIRC 3 /**< High frequency internal reference mode (with optional USB recovery). */
+#define KINETIS_MCGLITE_MODE_EXT 4 /**< External reference mode. */
+/** @} */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
/**
* @name Internal clock sources
@@ -62,6 +77,10 @@ #define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
/** @} */
+/**
+ * @name MCG modes of operation
+ * @{
+ */
#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
@@ -70,6 +89,9 @@ #define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+/** @} */
+
+#endif /* KINETIS_HAS_MCG_LITE */
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -93,14 +115,29 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#endif
+#if !defined(KINETIS_MCGLITE_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
/**
* @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
* @note The allowed range is 1...16.
* @note The default value is calculated for a 48 MHz system clock
* from a 96 MHz PLL output.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV1 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
#endif
/**
@@ -110,8 +147,12 @@ * @note The default value is calculated for 24 MHz bus/flash clocks
* from a 96 MHz PLL output and 48 MHz core/system clock.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV4 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 ((KINETIS_PLLCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV1)/KINETIS_BUSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 2
+ #endif
#endif
/**
@@ -140,14 +181,14 @@ * @brief MCU system/core clock frequency.
*/
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
#endif
/**
* @brief MCU bus/flash clock frequency.
*/
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif
/**
@@ -190,14 +231,20 @@ #error KINETIS_BUSCLK_FREQUENCY out of range
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
- KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
-#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
- KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
-#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
#endif
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_registry.h b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h index dcf3576..92ea0cc 100644 --- a/os/hal/ports/KINETIS/KL2x/kinetis_registry.h +++ b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,6 +26,10 @@ #ifndef _KINETIS_REGISTRY_H_
#define _KINETIS_REGISTRY_H_
+#if !defined(KL2x) || defined(__DOXYGEN__)
+#define KL2x
+#endif
+
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
@@ -34,16 +39,217 @@ * @{
*/
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+/*===========================================================================*/
+/* Common features */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
/* ADC attributes.*/
#define KINETIS_HAS_ADC0 TRUE
#define KINETIS_ADC0_IRQ_VECTOR Vector7C
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ FALSE
+
+/* GPT attributes.*/
+#define KINETIS_PIT_IRQ_VECTOR Vector98
+#define KINETIS_HAS_PIT_COMMON_IRQ TRUE
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_HAS_PIT2 FALSE
+#define KINETIS_HAS_PIT3 FALSE
/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
#define KINETIS_I2C0_IRQ_VECTOR Vector60
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR Vector64
+
+/* Serial attributes */
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector74
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector78
+#define KINETIS_HAS_SERIAL_ERROR_IRQ FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector68
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR Vector6C
+
+/* TPM attributes.*/
+#define KINETIS_HAS_TPM0 TRUE
+#define KINETIS_TPM0_CHANNELS 6
+#define KINETIS_TPM0_IRQ_VECTOR Vector84
+#define KINETIS_HAS_TPM1 TRUE
+#define KINETIS_TPM1_CHANNELS 2
+#define KINETIS_TPM1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_TPM2 TRUE
+#define KINETIS_TPM2_CHANNELS 2
+#define KINETIS_TPM2_IRQ_VECTOR Vector8C
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorA0
+
+/* FTFA attributes.*/
+#define KINETIS_FTFA_IRQ_VECTOR Vector54
+
+/* LPTMR attributes */
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorB0
+
+/*===========================================================================*/
+/* KL25 */
+/*===========================================================================*/
+#if defined(KL25) || defined(__DOXYGEN__)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL26 */
+/*===========================================================================*/
+#elif defined(KL26) /* defined(KL25) */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL27 */
+/*===========================================================================*/
+#elif defined(KL27Zxxx) || defined(KL27Zxx) /* defined(KL26) */
+
+#if !defined(KL27)
+#define KL27
+#endif
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE TRUE
+
+/* Note: on this device, SERIAL2 IRQ is alternatively FlexIO IRQ. */
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL0_IS_LPUART TRUE
+#define KINETIS_SERIAL1_IS_LPUART TRUE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG FALSE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/*===========================================================================*/
+/* KL27Zxxx (MKL27Z128* and MKL27Z256*) specific */
+/*===========================================================================*/
+#if defined(KL27Zxxx)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/*===========================================================================*/
+/* KL27Zxx (MKL27Z32* and MKL27Z264*) specific */
+/*===========================================================================*/
+#elif defined(KL27Zxx) /* defined(KL27Zxxx) */
+
+/* Has CRC module */
+/* Does not have USB voltage regulator */
+/* Does have KEEP_ALIVE USB feature */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTB to PORTE */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ TRUE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+#endif /* defined(KL27Zxx) */
+
+#else /* ! (KL25 || KL26 || KL27) */
+#error MCU type not described in kinetis_registry
+#endif /* KL2Y */
/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h b/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h deleted file mode 100644 index 99ffc9c..0000000 --- a/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h +++ /dev/null @@ -1,120 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/kinetis_tpm.h
- * @brief Kinetis TPM registers layout header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _KINETIS_TPM_H_
-#define _KINETIS_TPM_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name TPM_SC register
- * @{
- */
-#define TPM_SC_CMOD_DISABLE (0 << 3)
-#define TPM_SC_CMOD_LPTPM_CLK (1 << 3)
-#define TPM_SC_CMOD_LPTPM_EXTCLK (2 << 3)
-#define TPM_SC_CPWMS (1 << 5)
-#define TPM_SC_TOIE (1 << 6)
-#define TPM_SC_TOF (1 << 7)
-#define TPM_SC_DMA (1 << 8)
-/** @} */
-
-/**
- * @name TPM_MOD register
- * @{
- */
-#define TPM_MOD_MASK (0xFFFF)
-/** @} */
-
-/**
- * @name TPM_CnSC register
- * @{
- */
-#define TPM_CnSC_DMA (1 << 0)
-#define TPM_CnSC_ELSA (1 << 2)
-#define TPM_CnSC_ELSB (1 << 3)
-#define TPM_CnSC_MSA (1 << 4)
-#define TPM_CnSC_MSB (1 << 5)
-#define TPM_CnSC_CHIE (1 << 6)
-#define TPM_CnSC_CHF (1 << 7)
-/** @} */
-
-/**
- * @name TPM_CnV register
- * @{
- */
-#define TPM_CnV_VAL_MASK (0xFFFF)
-/** @} */
-
-/**
- * @name TPM_STATUS register
- * @{
- */
-#define TPM_STATUS_CH0F (1 << 0)
-#define TPM_STATUS_CH1F (1 << 1)
-#define TPM_STATUS_CH2F (1 << 2)
-#define TPM_STATUS_CH3F (1 << 3)
-#define TPM_STATUS_CH4F (1 << 4)
-#define TPM_STATUS_CH5F (1 << 5)
-#define TPM_STATUS_TOF (1 << 8)
-/** @} */
-
-/**
- * @name TPM_CONF register
- * @{
- */
-#define TPM_CONF_DOZEEN (1 << 5)
-#define TPM_CONF_DBGMODE_CONT (3 << 6)
-#define TPM_CONF_DBGMODE_PAUSE (0 << 6)
-#define TPM_CONF_GTBEEN (1 << 9)
-#define TPM_CONF_CSOT (1 << 16)
-#define TPM_CONF_CSOO (1 << 17)
-#define TPM_CONF_CROT (1 << 18)
-#define TPM_CONF_TRGSEL(n) ((n) << 24)
-/** @{ */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-#endif /* _KINETIS_TPM_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kl25z.h b/os/hal/ports/KINETIS/KL2x/kl25z.h deleted file mode 100644 index 4e9547f..0000000 --- a/os/hal/ports/KINETIS/KL2x/kl25z.h +++ /dev/null @@ -1,1190 +0,0 @@ -/* - * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef _KL25Z_H_ -#define _KL25Z_H_ - -/* - * ============================================================== - * ---------- Interrupt Number Definition ----------------------- - * ============================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ****************/ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - SVCall_IRQn = -5, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - -/****** KL2x Specific Interrupt Numbers ***********************/ - DMA0_IRQn = 0, - DMA1_IRQn = 1, - DMA2_IRQn = 2, - DMA3_IRQn = 3, - Reserved0_IRQn = 4, - FTFA_IRQn = 5, - PMC_IRQn = 6, - LLWU_IRQn = 7, - I2C0_IRQn = 8, - I2C1_IRQn = 9, - SPI0_IRQn = 10, - SPI1_IRQn = 11, - UART0_IRQn = 12, - UART1_IRQn = 13, - UART2_IRQn = 14, - ADC0_IRQn = 15, - CMP0_IRQn = 16, - TPM0_IRQn = 17, - TPM1_IRQn = 18, - TPM2_IRQn = 19, - RTC0_IRQn = 20, - RTC1_IRQn = 21, - PIT_IRQn = 22, - Reserved1_IRQn = 23, - USB_OTG_IRQn = 24, - DAC0_IRQn = 25, - TSI0_IRQn = 26, - MCG_IRQn = 27, - LPTMR0_IRQn = 28, - Reserved2_IRQn = 29, - PINA_IRQn = 30, - PIND_IRQn = 31, -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/** - * @brief KL2x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __MPU_PRESENT 0 -#define __VTOR_PRESENT 1 -#define __NVIC_PRIO_BITS 2 -#define __Vendor_SysTickConfig 0 - -#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ - -typedef struct -{ - __IO uint32_t SOPT1; - __IO uint32_t SOPT1CFG; - uint32_t RESERVED0[1023]; - __IO uint32_t SOPT2; - __I uint32_t RESERVED1[1]; - __IO uint32_t SOPT4; - __IO uint32_t SOPT5; - uint32_t RESERVED2[1]; - __IO uint32_t SOPT7; - uint32_t RESERVED3[2]; - __IO uint32_t SDID; - uint32_t RESERVED4[3]; - __IO uint32_t SCGC4; - __IO uint32_t SCGC5; - __IO uint32_t SCGC6; - __IO uint32_t SCGC7; - __IO uint32_t CLKDIV1; - uint32_t RESERVED5[1]; - __IO uint32_t FCFG1; - __IO uint32_t FCFG2; - uint32_t RESERVED6[1]; - __IO uint32_t UIDMH; - __IO uint32_t UIDML; - __IO uint32_t UIDL; - uint32_t RESERVED7[39]; - __IO uint32_t COPC; - __IO uint32_t SRVCOP; -} SIM_TypeDef; - -typedef struct -{ - __IO uint8_t PE1; - __IO uint8_t PE2; - __IO uint8_t PE3; - __IO uint8_t PE4; - __IO uint8_t ME; - __IO uint8_t F1; - __IO uint8_t F2; - __I uint8_t F3; - __IO uint8_t FILT1; - __IO uint8_t FILT2; -} LLWU_TypeDef; - -typedef struct -{ - __IO uint32_t PCR[32]; - __IO uint32_t GPCLR; - __IO uint32_t GPCHR; - uint32_t RESERVED0[6]; - __IO uint32_t ISFR; -} PORT_TypeDef; - -typedef struct -{ - __IO uint8_t C1; - __IO uint8_t C2; - __IO uint8_t C3; - __IO uint8_t C4; - __IO uint8_t C5; - __IO uint8_t C6; - __IO uint8_t S; - uint8_t RESERVED0[1]; - __IO uint8_t SC; - uint8_t RESERVED1[1]; - __IO uint8_t ATCVH; - __IO uint8_t ATCVL; - __IO uint8_t C7; - __IO uint8_t C8; - __IO uint8_t C9; - __IO uint8_t C10; -} MCG_TypeDef; - -typedef struct -{ - __IO uint8_t CR; -} OSC_TypeDef; - -typedef struct -{ - __IO uint32_t SAR; - __IO uint32_t DAR; - __IO uint32_t DSR_BCR; - __IO uint32_t DCR; -} DMAChannel_TypeDef; - -typedef struct -{ - DMAChannel_TypeDef ch[4]; -} DMA_TypeDef; - -typedef struct -{ - __IO uint8_t CHCFG[4]; -} DMAMUX_TypeDef; - -typedef struct -{ - __IO uint32_t SC; - __IO uint32_t CNT; - __IO uint32_t MOD; - struct { // Channels - __IO uint32_t SC; - __IO uint32_t V; - } C[6]; - uint32_t RESERVED0[5]; - __IO uint32_t STATUS; - uint32_t RESERVED1[12]; - __IO uint32_t CONF; -} TPM_TypeDef; - -typedef struct -{ - __IO uint32_t SC1A; // ADC Status and Control Registers 1 - __IO uint32_t SC1B; // ADC Status and Control Registers 1 - __IO uint32_t CFG1; // ADC Configuration Register 1 - __IO uint32_t CFG2; // ADC Configuration Register 2 - __I uint32_t RA; // ADC Data Result Register - __I uint32_t RB; // ADC Data Result Register - __IO uint32_t CV1; // Compare Value Registers - __IO uint32_t CV2; // Compare Value Registers - __IO uint32_t SC2; // Status and Control Register 2 - __IO uint32_t SC3; // Status and Control Register 3 - __IO uint32_t OFS; // ADC Offset Correction Register - __IO uint32_t PG; // ADC Plus-Side Gain Register - __IO uint32_t MG; // ADC Minus-Side Gain Register - __IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register - uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t PSR; - __IO uint32_t CMR; - __I uint32_t CNR; -} LPTMR_TypeDef; - -typedef struct -{ - __IO uint32_t GENCS; - __IO uint32_t DATA; - __IO uint32_t TSHD; -} TSI_TypeDef; - -typedef struct -{ - __IO uint32_t PDOR; - __IO uint32_t PSOR; - __IO uint32_t PCOR; - __IO uint32_t PTOR; - __IO uint32_t PDIR; - __IO uint32_t PDDR; -} GPIO_TypeDef; - -typedef struct -{ - __IO uint8_t C1; - __IO uint8_t C2; - __IO uint8_t BR; - __IO uint8_t S; - uint8_t RESERVED0[1]; - __IO uint8_t D; - uint8_t RESERVED1[1]; - __IO uint8_t M; -} SPI_TypeDef; - -typedef struct -{ - __IO uint8_t A1; - __IO uint8_t F; - __IO uint8_t C1; - __IO uint8_t S; - __IO uint8_t D; - __IO uint8_t C2; - __IO uint8_t FLT; - __IO uint8_t RA; - __IO uint8_t SMB; - __IO uint8_t A2; - __IO uint8_t SLTH; - __IO uint8_t SLTL; -} I2C_TypeDef; - -typedef struct -{ - __IO uint8_t BDH; - __IO uint8_t BDL; - __IO uint8_t C1; - __IO uint8_t C2; - __IO uint8_t S1; - __IO uint8_t S2; - __IO uint8_t C3; - __IO uint8_t D; - __IO uint8_t C4; -} UART_TypeDef; - -typedef struct -{ - __IO uint8_t BDH; - __IO uint8_t BDL; - __IO uint8_t C1; - __IO uint8_t C2; - __IO uint8_t S1; - __IO uint8_t S2; - __IO uint8_t C3; - __IO uint8_t D; - __IO uint8_t MA1; - __IO uint8_t MA2; - __IO uint8_t C4; - __IO uint8_t C5; -} UARTLP_TypeDef; - -typedef struct -{ - __IO uint8_t LVDSC1; - __IO uint8_t LVDSC2; - __IO uint8_t REGSC; -} PMC_TypeDef; - -/****************************************************************/ -/* Peripheral memory map */ -/****************************************************************/ -#define DMA_BASE ((uint32_t)0x40008100) -#define DMAMUX_BASE ((uint32_t)0x40021000) -#define TPM0_BASE ((uint32_t)0x40038000) -#define TPM1_BASE ((uint32_t)0x40039000) -#define TPM2_BASE ((uint32_t)0x4003A000) -#define ADC0_BASE ((uint32_t)0x4003B000) -#define LPTMR0_BASE ((uint32_t)0x40040000) -#define TSI0_BASE ((uint32_t)0x40045000) -#define SIM_BASE ((uint32_t)0x40047000) -#define PORTA_BASE ((uint32_t)0x40049000) -#define PORTB_BASE ((uint32_t)0x4004A000) -#define PORTC_BASE ((uint32_t)0x4004B000) -#define PORTD_BASE ((uint32_t)0x4004C000) -#define PORTE_BASE ((uint32_t)0x4004D000) -#define MCG_BASE ((uint32_t)0x40064000) -#define OSC0_BASE ((uint32_t)0x40065000) -#define I2C0_BASE ((uint32_t)0x40066000) -#define I2C1_BASE ((uint32_t)0x40067000) -#define UART0_BASE ((uint32_t)0x4006A000) -#define UART1_BASE ((uint32_t)0x4006B000) -#define UART2_BASE ((uint32_t)0x4006C000) -#define SPI0_BASE ((uint32_t)0x40076000) -#define SPI1_BASE ((uint32_t)0x40077000) -#define LLWU_BASE ((uint32_t)0x4007C000) -#define PMC_BASE ((uint32_t)0x4007D000) -#define GPIOA_BASE ((uint32_t)0x400FF000) -#define GPIOB_BASE ((uint32_t)0x400FF040) -#define GPIOC_BASE ((uint32_t)0x400FF080) -#define GPIOD_BASE ((uint32_t)0x400FF0C0) -#define GPIOE_BASE ((uint32_t)0x400FF100) - -/****************************************************************/ -/* Peripheral declaration */ -/****************************************************************/ -#define DMA ((DMA_TypeDef *) DMA_BASE) -#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) -#define TPM0 ((TPM_TypeDef *) TPM0_BASE) -#define TPM1 ((TPM_TypeDef *) TPM1_BASE) -#define TPM2 ((TPM_TypeDef *) TPM2_BASE) -#define ADC0 ((ADC_TypeDef *) ADC0_BASE) -#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) -#define TSI0 ((TSI_TypeDef *) TSI0_BASE) -#define SIM ((SIM_TypeDef *) SIM_BASE) -#define LLWU ((LLWU_TypeDef *) LLWU_BASE) -#define PMC ((PMC_TypeDef *) PMC_BASE) -#define PORTA ((PORT_TypeDef *) PORTA_BASE) -#define PORTB ((PORT_TypeDef *) PORTB_BASE) -#define PORTC ((PORT_TypeDef *) PORTC_BASE) -#define PORTD ((PORT_TypeDef *) PORTD_BASE) -#define PORTE ((PORT_TypeDef *) PORTE_BASE) -#define MCG ((MCG_TypeDef *) MCG_BASE) -#define OSC0 ((OSC_TypeDef *) OSC0_BASE) -#define SPI0 ((SPI_TypeDef *) SPI0_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define UART0 ((UARTLP_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) - -/****************************************************************/ -/* Peripheral Registers Bits Definition */ -/****************************************************************/ - -/****************************************************************/ -/* */ -/* System Integration Module (SIM) */ -/* */ -/****************************************************************/ -/********* Bits definition for SIM_SOPT1 register *************/ -#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ -#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ -#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ -#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ -#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ -#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ - -/******* Bits definition for SIM_SOPT1CFG register ************/ -#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ -#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ -#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ - -/******* Bits definition for SIM_SOPT2 register ************/ -#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */ -#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */ -#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */ -#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ -#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ -#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ -#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ -#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ -#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ -#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ -#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ -#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ - -/******* Bits definition for SIM_SCGC4 register ************/ -#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ -#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ -#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ -#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ -#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ -#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ -#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ -#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ -#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ - -/******* Bits definition for SIM_SCGC5 register ************/ -#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ -#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ -#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ -#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ -#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ -#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ -#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ -#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ -#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ -#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ -#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ -#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ -#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ -#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ -#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ - -/****** Bits definition for SIM_CLKDIV1 register ***********/ -#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ -#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ -#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ -#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ -#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ -#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ - -/****************************************************************/ -/* */ -/* Low-Leakage Wakeup Unit (LLWU) */ -/* */ -/****************************************************************/ -/********** Bits definition for LLWU_PE1 register *************/ -#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ -#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ -#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ -#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ -#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ -#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ -#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ -#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ -#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ -#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ -#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ -#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ - -/********** Bits definition for LLWU_PE2 register *************/ -#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ -#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ -#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ -#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ -#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ -#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ -#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ -#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ -#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ -#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ -#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ -#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ - -/********** Bits definition for LLWU_PE3 register *************/ -#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ -#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ -#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ -#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ -#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ -#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ -#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ -#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ -#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ -#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ -#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ -#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ - -/********** Bits definition for LLWU_PE4 register *************/ -#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ -#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ -#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ -#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ -#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ -#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ -#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ -#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ -#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ -#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ -#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ -#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ - -/********** Bits definition for LLWU_ME register *************/ -#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ -#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ -#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ -#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ -#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ -#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ -#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ -#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ - -/********** Bits definition for LLWU_F1 register *************/ -#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ -#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ -#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ -#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ -#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ -#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ -#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ -#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ - -/********** Bits definition for LLWU_F2 register *************/ -#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ -#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ -#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ -#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ -#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ -#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ -#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ -#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ - -/********** Bits definition for LLWU_F3 register *************/ -#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ -#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ -#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ -#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ -#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ -#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ -#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ -#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ - -/********** Bits definition for LLWU_FILT1 register *************/ -#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ - -/********** Bits definition for LLWU_FILT2 register *************/ -#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ - -/****************************************************************/ -/* */ -/* Port Control and interrupts (PORT) */ -/* */ -/****************************************************************/ -/******** Bits definition for PORTx_PCRn register *************/ -#define PORTx_PCRn_ISR ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ -#define PORTx_PCRn_IRQC_SHIFT 16 -#define PORTx_PCRn_IRQC_MASK ((uint32_t)0x000F0000) /*!< Interrupt Configuration */ -#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) -#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ -#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */ -#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ -#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ -#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ -#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ -#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ -#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ - -/****************************************************************/ -/* */ -/* Oscillator (OSC) */ -/* */ -/****************************************************************/ -/*********** Bits definition for OSC_CR register **************/ -#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ -#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ -#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ -#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ -#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ -#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ - -/****************************************************************/ -/* */ -/* Direct Memory Access (DMA) */ -/* */ -/****************************************************************/ -/*********** Bits definition for DMA_BCRn register ************/ -#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */ -#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */ -#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */ -#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */ -#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */ -#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */ -#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */ -#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */ -#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */ - -/*********** Bits definition for DMA_DCRn register ************/ -#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */ -#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */ -#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */ -#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */ -#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */ -#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */ -#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */ -#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */ -#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */ -#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */ -#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */ -#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */ -#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */ -#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */ -#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */ -#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */ -#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */ -#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */ -#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */ -#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */ -#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */ -#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */ -#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */ -#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */ -#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */ -#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */ -#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */ -#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */ -#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */ -#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */ - -/****************************************************************/ -/* */ -/* Direct Memory Access Multiplexer (DMAMUX) */ -/* */ -/****************************************************************/ -/******** Bits definition for DMAMUX_CHCFGn register **********/ -#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ -#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ -#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ -#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ -#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ - -/****************************************************************/ -/* */ -/* Analog-to-Digital Converter (ADC) */ -/* */ -/****************************************************************/ -/*********** Bits definition for ADCx_SC1n register ***********/ -#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ -#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ -#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ -#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ -#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ -#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ - -/*********** Bits definition for ADCx_CFG1 register ***********/ -#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ -#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ -#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ -#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ -#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ -#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ -#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ -#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ -#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ -#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ -#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ - -/*********** Bits definition for ADCx_CFG2 register ***********/ -#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ -#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ -#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ -#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ -#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ -#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ - -/*********** Bits definition for ADCx_SC2 register ***********/ -#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ -#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ -#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ -#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ -#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ -#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ -#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ -#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ -#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ - -/*********** Bits definition for ADCx_SC3 register ***********/ -#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ -#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ -#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ -#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ -#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ -#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ -#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ - -/****************************************************************/ -/* */ -/* Low-Power Timer (LPTMR) */ -/* */ -/****************************************************************/ -/********** Bits definition for LPTMRx_CSR register ***********/ -#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ -#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ -#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ -#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ -#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ -#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ -#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ -#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ -#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ - -/********** Bits definition for LPTMRx_PSR register ***********/ -#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ -#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ -#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ -#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ -#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ -#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ -#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ - -/********** Bits definition for LPTMRx_CMR register ***********/ -#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ -#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ -#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ - -/********** Bits definition for LPTMRx_CNR register ***********/ -#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ -#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ -#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ - -/****************************************************************/ -/* */ -/* Touch Sensing Input (TSI) */ -/* */ -/****************************************************************/ -/********** Bits definition for TSIx_GENCS register ***********/ -#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ -#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ -#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ -#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ -#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ -#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ -#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ -#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ -#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ -#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ -#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ -#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ -#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ -#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ -#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ -#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ -#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ -#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ -#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ -#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ -#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ -#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ -#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ -#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ -#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ -#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ -#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ - -/********** Bits definition for TSIx_DATA register ************/ -#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ -#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ -#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ -#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ -#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ -#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ -#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ -#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ - -/********** Bits definition for TSIx_TSHD register ************/ -#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ -#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ -#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ -#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ -#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ -#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ - -/****************************************************************/ -/* */ -/* Multipurpose Clock Generator (MCG) */ -/* */ -/****************************************************************/ -/*********** Bits definition for MCG_C1 register **************/ -#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ -#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ -#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ -#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ -#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ -#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ -#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ -#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ -#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ -#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ -#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ -#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ - -/*********** Bits definition for MCG_C2 register **************/ -#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */ -#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ -#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ -#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ -#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ -#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ -#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ -#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ - -/*********** Bits definition for MCG_C3 register **************/ -#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */ -#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */ -#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */ - -/*********** Bits definition for MCG_C4 register **************/ -#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ -#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ -#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ -#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ -#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ -#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ -#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ -#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */ - -/*********** Bits definition for MCG_C5 register **************/ -#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */ -#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */ -#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */ -#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */ -#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ - -/*********** Bits definition for MCG_C6 register **************/ -#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */ -#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */ -#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */ -#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */ -#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */ -#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ - -/************ Bits definition for MCG_S register **************/ -#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */ -#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */ -#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */ -#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */ -#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ -#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ -#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ -#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ -#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ -#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ -#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ -#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ -#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */ - -/************ Bits definition for MCG_SC register **************/ -#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */ -#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */ -#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */ -#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */ -#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ -#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ -#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ -#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ -#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ -#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ -#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ -#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ -#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ -#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ -#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ -#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */ - -/*********** Bits definition for MCG_ATCVH register ************/ -#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */ -#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */ -#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */ - -/*********** Bits definition for MCG_ATCVL register ************/ -#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */ -#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */ -#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */ - -/************ Bits definition for MCG_C7 register **************/ -/* All MCG_C7 bits are reserved on the KL25Z. */ - -/************ Bits definition for MCG_C8 register **************/ -#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */ - -/************ Bits definition for MCG_C9 register **************/ -/* All MCG_C9 bits are reserved on the KL25Z. */ - -/************ Bits definition for MCG_C10 register *************/ -/* All MCG_C10 bits are reserved on the KL25Z. */ - - -/****************************************************************/ -/* */ -/* Serial Peripheral Interface (SPI) */ -/* */ -/****************************************************************/ -/*********** Bits definition for SPIx_C1 register *************/ -#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ -#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ -#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ -#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ -#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ -#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ -#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ -#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ - -/*********** Bits definition for SPIx_C2 register *************/ -#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ -#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ -#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ -#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ -#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ -#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ -#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ - -/*********** Bits definition for SPIx_BR register *************/ -#define SPIx_BR_SPPR ((uint8_t)0x70) /*!< SPI Baud rate Prescaler Divisor */ -#define SPIx_BR_SPR ((uint8_t)0x0F) /*!< SPI Baud rate Divisor */ - -#define SPIx_BR_SPPR_SHIFT 4 - -/*********** Bits definition for SPIx_S register **************/ -#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ -#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ -#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ -#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ - -/*********** Bits definition for SPIx_D register **************/ -#define SPIx_D_DATA ((uint8_t)0xFF) /*!< Data */ - -/*********** Bits definition for SPIx_M register **************/ -#define SPIx_M_DATA ((uint8_t)0xFF) /*!< SPI HW Compare value for Match */ - -/****************************************************************/ -/* */ -/* Inter-Integrated Circuit (I2C) */ -/* */ -/****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ - -#define I2Cx_A1_AD_SHIT 1 - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ - -#define I2Cx_F_MULT_SHIFT 5 - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S register **************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ - -/*********** Bits definition for I2Cx_FLT register ************/ -#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ -#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ -#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ -#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ - -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ - -#define I2Cx_RA_RAD_SHIFT 1 - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ - -#define I2Cx_A2_SAD_SHIFT 1 - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ - -/****************************************************************/ -/* */ -/* Universal Asynchronous Receiver/Transmitter (UART) */ -/* */ -/****************************************************************/ -/********* Bits definition for UARTx_BDH register *************/ -#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ -#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ -#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ -#define UARTx_BDH_SBR ((uint8_t)0x1F) /*!< Baud Rate Modulo Divisor */ - -/********* Bits definition for UARTx_BDL register *************/ -#define UARTx_BDL_SBR ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ - -/********* Bits definition for UARTx_C1 register **************/ -#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ -#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ -#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ -#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ -#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ -#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ -#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ -#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ -#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ - -/********* Bits definition for UARTx_C2 register **************/ -#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ -#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ -#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ -#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ -#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ -#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ -#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ -#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ - -/********* Bits definition for UARTx_S1 register **************/ -#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ -#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ -#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ -#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ -#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ -#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ -#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ -#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ - -/********* Bits definition for UARTx_S2 register **************/ -#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ -#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ -#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ -#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ -#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ -#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ -#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ -#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ - -/********* Bits definition for UARTx_C3 register **************/ -#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */ -#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ -#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */ -#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ -#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ -#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ -#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ -#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ -#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ -#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ - -/********* Bits definition for UARTx_D register ***************/ -#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ -#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ -#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ -#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ -#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ -#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ -#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ -#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ - -/********* Bits definition for UARTx_MA1 register *************/ -#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ - -/********* Bits definition for UARTx_MA2 register *************/ -#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ - -/********* Bits definition for UARTx_C4 register **************/ -#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ -#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ -#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ -#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ -#define UARTx_C4_RDMAS ((uint8_t)0x80) /*!< Receiver Full DMA Select */ -#define UARTx_C4_OSR ((uint8_t)0x1F) /*!< Over Sampling Ratio */ - -/********* Bits definition for UARTx_C5 register **************/ -#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ -#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ -#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ -#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ -/****************************************************************/ -/* */ -/* Power Management Controller (PMC) */ -/* */ -/****************************************************************/ -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ -#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ -#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ -#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ -#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ -#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ -#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ -#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ -#define PMC_LVDSC2_LVWV_SHIFT 0 -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) -/********* Bits definition for PMC_REGSC register *************/ -#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ -#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ -#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ -#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ - -#endif diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.c b/os/hal/ports/KINETIS/KL2x/pal_lld.c deleted file mode 100644 index a894c6a..0000000 --- a/os/hal/ports/KINETIS/KL2x/pal_lld.c +++ /dev/null @@ -1,225 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013..2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pal_lld.c
- * @brief Kinetis KL2x PAL subsystem low level driver.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 I/O ports configuration.
- * @details Ports A-D(E, F, G, H) clocks enabled.
- *
- * @param[in] config the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
- int i, j;
-
- /* Enable clocking of all Ports */
- SIM->SCGC5 |= SIM_SCGC5_PORTA |
- SIM_SCGC5_PORTB |
- SIM_SCGC5_PORTC |
- SIM_SCGC5_PORTD |
- SIM_SCGC5_PORTE;
-
- for (i = 0; i < TOTAL_PORTS; i++) {
- for (j = 0; j < PADS_PER_PORT; j++) {
- pal_lld_setpadmode(config->ports[i].port,
- j,
- config->ports[i].pads[j]);
- }
- }
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
-
- (void)port;
- (void)mask;
- (void)mode;
-
-}
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-uint8_t pal_lld_readpad(ioportid_t port, uint8_t pad)
-{
- return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
-}
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-void pal_lld_writepad(ioportid_t port, uint8_t pad, uint8_t bit)
-{
- if (bit == PAL_HIGH)
- port->PDOR |= ((uint32_t) 1 << pad);
- else
- port->PDOR &= ~((uint32_t) 1 << pad);
-}
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
-{
- PORT_TypeDef *portcfg = NULL;
-
- osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
-
- if (mode == PAL_MODE_OUTPUT_PUSHPULL)
- port->PDDR |= ((uint32_t) 1 << pad);
- else
- port->PDDR &= ~((uint32_t) 1 << pad);
-
- if (port == IOPORT1)
- portcfg = PORTA;
- else if (port == IOPORT2)
- portcfg = PORTB;
- else if (port == IOPORT3)
- portcfg = PORTC;
- else if (port == IOPORT4)
- portcfg = PORTD;
- else if (port == IOPORT5)
- portcfg = PORTE;
-
- osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() - invalid port");
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_INPUT:
- case PAL_MODE_OUTPUT_PUSHPULL:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
- break;
- case PAL_MODE_INPUT_PULLUP:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE | PORTx_PCRn_PS;
- break;
- case PAL_MODE_INPUT_PULLDOWN:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE;
- break;
- case PAL_MODE_UNCONNECTED:
- case PAL_MODE_INPUT_ANALOG:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(0);
- break;
- case PAL_MODE_ALTERNATIVE_1:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
- break;
- case PAL_MODE_ALTERNATIVE_2:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(2);
- break;
- case PAL_MODE_ALTERNATIVE_3:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(3);
- break;
- case PAL_MODE_ALTERNATIVE_4:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(4);
- break;
- case PAL_MODE_ALTERNATIVE_5:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(5);
- break;
- case PAL_MODE_ALTERNATIVE_6:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(6);
- break;
- case PAL_MODE_ALTERNATIVE_7:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(7);
- break;
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.h b/os/hal/ports/KINETIS/KL2x/pal_lld.h deleted file mode 100644 index 8b38709..0000000 --- a/os/hal/ports/KINETIS/KL2x/pal_lld.h +++ /dev/null @@ -1,331 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pal_lld.h
- * @brief Kinetis KL2x PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-#define PAL_MODE_ALTERNATIVE_1 0x10
-#define PAL_MODE_ALTERNATIVE_2 0x11
-#define PAL_MODE_ALTERNATIVE_3 0x12
-#define PAL_MODE_ALTERNATIVE_4 0x13
-#define PAL_MODE_ALTERNATIVE_5 0x14
-#define PAL_MODE_ALTERNATIVE_6 0x15
-#define PAL_MODE_ALTERNATIVE_7 0x16
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-#define TOTAL_PORTS 5
-#define PADS_PER_PORT 32
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef GPIO_TypeDef * ioportid_t;
-
-typedef struct {
- ioportid_t port;
- iomode_t pads[PADS_PER_PORT];
-} PortConfig;
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct
-{
- PortConfig ports[TOTAL_PORTS];
-} PALConfig;
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief First I/O port identifier.
- * @details Low level drivers can define multiple ports, it is suggested to
- * use this naming convention.
- */
-#define IOPORT1 GPIOA
-#define IOPORT2 GPIOB
-#define IOPORT3 GPIOC
-#define IOPORT4 GPIOD
-#define IOPORT5 GPIOE
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) \
- (port)->PDIR
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) \
- (port)->PDOR
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) \
- (port)->PDOR = (bits)
-
-/**
- * @brief Sets a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) \
- (port)->PSOR = (bits)
-
-/**
- * @brief Clears a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) \
- (port)->PCOR = (bits)
-
-/**
- * @brief Toggles a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be XORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits) \
- (port)->PTOR = (bits)
-
-/**
- * @brief Reads a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) 0
-
-/**
- * @brief Writes a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode) \
- _pal_lld_setpadmode(port, pad, mode)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
- void pal_lld_setpadmode(ioportid_t port,
- uint8_t pad,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/platform.mk b/os/hal/ports/KINETIS/KL2x/platform.mk index f9d3c67..8ababc3 100644 --- a/os/hal/ports/KINETIS/KL2x/platform.mk +++ b/os/hal/ports/KINETIS/KL2x/platform.mk @@ -1,13 +1,15 @@ # List of all platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/adc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/st_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.c b/os/hal/ports/KINETIS/KL2x/pwm_lld.c index 4ba7d6e..2f56216 100644 --- a/os/hal/ports/KINETIS/KL2x/pwm_lld.c +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.c @@ -27,18 +27,6 @@ #if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define KINETIS_TPM0_CHANNELS 6
-#define KINETIS_TPM1_CHANNELS 2
-#define KINETIS_TPM2_CHANNELS 2
-
-#define KINETIS_TPM0_HANDLER Vector84
-#define KINETIS_TPM1_HANDLER Vector88
-#define KINETIS_TPM2_HANDLER Vector8C
-
-/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -80,25 +68,25 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { sr = pwmp->tpm->STATUS;
pwmp->tpm->STATUS = 0xFFFFFFFF;
- if (((sr & TPM_SC_TOF) != 0) &&
+ if (((sr & TPMx_STATUS_TOF) != 0) &&
(pwmp->config->callback != NULL))
pwmp->config->callback(pwmp);
- if (((sr & TPM_STATUS_CH0F) != 0) &&
+ if (((sr & TPMx_STATUS_CH0F) != 0) &&
(pwmp->config->channels[0].callback != NULL))
pwmp->config->channels[0].callback(pwmp);
- if (((sr & TPM_STATUS_CH1F) != 0) &&
+ if (((sr & TPMx_STATUS_CH1F) != 0) &&
(pwmp->config->channels[1].callback != NULL))
pwmp->config->channels[1].callback(pwmp);
- if (((sr & TPM_STATUS_CH2F) != 0) &&
+ if (((sr & TPMx_STATUS_CH2F) != 0) &&
(pwmp->config->channels[2].callback != NULL))
pwmp->config->channels[2].callback(pwmp);
- if (((sr & TPM_STATUS_CH3F) != 0) &&
+ if (((sr & TPMx_STATUS_CH3F) != 0) &&
(pwmp->config->channels[3].callback != NULL))
pwmp->config->channels[3].callback(pwmp);
- if (((sr & TPM_STATUS_CH4F) != 0) &&
+ if (((sr & TPMx_STATUS_CH4F) != 0) &&
(pwmp->config->channels[4].callback != NULL))
pwmp->config->channels[4].callback(pwmp);
- if (((sr & TPM_STATUS_CH5F) != 0) &&
+ if (((sr & TPMx_STATUS_CH5F) != 0) &&
(pwmp->config->channels[5].callback != NULL))
pwmp->config->channels[5].callback(pwmp);
}
@@ -113,7 +101,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM0_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD1);
@@ -127,7 +115,7 @@ OSAL_IRQ_HANDLER(KINETIS_TPM0_HANDLER) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM1_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD2);
@@ -141,7 +129,7 @@ OSAL_IRQ_HANDLER(KINETIS_TPM1_HANDLER) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM2_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD3);
@@ -238,7 +226,7 @@ void pwm_lld_start(PWMDriver *pwmp) { CPWM up-counting mode
Timer overflow interrupt disabled
DMA disabled.*/
- pwmp->tpm->SC = TPM_SC_CMOD_LPTPM_CLK | i;
+ pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i;
/* Configure period.*/
pwmp->tpm->MOD = pwmp->period - 1;
}
@@ -297,19 +285,19 @@ void pwm_lld_stop(PWMDriver *pwmp) { void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
- uint32_t mode = TPM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+ uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/
switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= TPM_CnSC_ELSB;
+ mode |= TPMx_CnSC_ELSB;
break;
case PWM_OUTPUT_ACTIVE_LOW:
- mode |= TPM_CnSC_ELSA;
+ mode |= TPMx_CnSC_ELSA;
break;
}
- if (pwmp->tpm->C[channel].SC & TPM_CnSC_CHIE)
- mode |= TPM_CnSC_CHIE;
+ if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE)
+ mode |= TPMx_CnSC_CHIE;
pwmp->tpm->C[channel].SC = mode;
pwmp->tpm->C[channel].V = width;
@@ -344,7 +332,7 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { */
void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->tpm->SC |= TPM_SC_TOIE;
+ pwmp->tpm->SC |= TPMx_SC_TOIE;
}
/**
@@ -358,7 +346,7 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { */
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->tpm->SC &= ~TPM_SC_TOIE;
+ pwmp->tpm->SC &= ~TPMx_SC_TOIE;
}
/**
@@ -375,7 +363,7 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel) {
- pwmp->tpm->C[channel].SC |= TPM_CnSC_CHIE;
+ pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE;
}
/**
@@ -392,7 +380,7 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel) {
- pwmp->tpm->C[channel].SC &= ~TPM_CnSC_CHIE;
+ pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE;
}
#endif /* HAL_USE_PWM */
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.h b/os/hal/ports/KINETIS/KL2x/pwm_lld.h index fe255bd..5a3d7c2 100644 --- a/os/hal/ports/KINETIS/KL2x/pwm_lld.h +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.h @@ -25,8 +25,6 @@ #ifndef _PWM_LLD_H_
#define _PWM_LLD_H_
-#include "kinetis_tpm.h"
-
#if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
@@ -65,16 +63,80 @@ #if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
#define KINETIS_PWM_USE_ADVANCED FALSE
#endif
+
+/**
+ * @brief TPM0 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM1 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM2 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2
+#endif
+
/** @} */
/*===========================================================================*/
/* Configuration checks. */
/*===========================================================================*/
+#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0
+#error "TPM0 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1
+#error "TPM1 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2
+#error "TPM2 not present in the selected device"
+#endif
+
#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
#error "PWM driver activated but no TPM peripheral assigned"
#endif
+#if KINETIS_PWM_USE_TPM0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_TPM0_IRQ_VECTOR)
+#error "KINETIS_TPM0_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM1_IRQ_VECTOR)
+#error "KINETIS_TPM1_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM2_IRQ_VECTOR)
+#error "KINETIS_TPM2_IRQ_VECTOR not defined"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.c b/os/hal/ports/KINETIS/KL2x/serial_lld.c deleted file mode 100644 index f0cbc46..0000000 --- a/os/hal/ports/KINETIS/KL2x/serial_lld.c +++ /dev/null @@ -1,353 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/serial_lld.c
- * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "kl25z.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SD1 driver identifier.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- 38400
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] u pointer to an UART I/O block
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- UARTLP_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_RDRF) {
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- u->C2 &= ~UARTx_C2_TIE;
- } else {
- u->D = b;
- }
- }
-
- if (u->S1 & UARTx_S1_IDLE)
- u->S1 = UARTx_S1_IDLE; // Clear IDLE (S1 bits are write-1-to-clear).
-
- if (u->S1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- // FIXME: need to add set_error()
- // Clear flags (S1 bits are write-1-to-clear).
- u->S1 = UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
-}
-
-/**
- * @brief Attempts a TX preload
- */
-static void preload(SerialDriver *sdp) {
- UARTLP_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b = oqGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- return;
- }
- u->D = b;
- u->C2 |= UARTx_C2_TIE;
- }
-}
-
-/**
- * @brief Driver output notification.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD1);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
-}
-#endif
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(UARTLP_TypeDef *uart, const SerialConfig *config)
-{
- uint32_t uart_clock;
-
- uart->C1 = 0;
- uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
- uart->S1 = UARTx_S1_IDLE | UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- while (uart->S1 & UARTx_S1_RDRF) {
- (void)uart->D;
- }
-
-#if KINETIS_SERIAL_USE_UART0
- if (uart == UART0) {
- /* UART0 can be clocked from several sources. */
- uart_clock = KINETIS_UART0_CLOCK_FREQ;
- }
-#endif
-#if KINETIS_SERIAL_USE_UART1
- if (uart == UART1) {
- uart_clock = KINETIS_BUSCLK_FREQUENCY;
- }
-#endif
-#if KINETIS_SERIAL_USE_UART2
- if (uart == UART2) {
- uart_clock = KINETIS_BUSCLK_FREQUENCY;
- }
-#endif
-
- /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
- uint16_t divisor = (uart_clock / 16) / config->sc_speed;
- uart->C4 = UARTx_C4_OSR & (16 - 1);
- uart->BDH = (divisor >> 8) & UARTx_BDH_SBR;
- uart->BDL = (divisor & UARTx_BDL_SBR);
-
- uart->C2 = UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector70) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector74) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector78) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if KINETIS_SERIAL_USE_UART0
- /* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
- SD1.uart = UART0;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- /* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
- SD2.uart = UART1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart = UART2;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- SIM->SCGC4 |= SIM_SCGC4_UART0;
- SIM->SOPT2 =
- (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
- SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- SIM->SCGC4 |= SIM_SCGC4_UART1;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- SIM->SCGC4 |= SIM_SCGC4_UART2;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART2 */
-
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- /* TODO: Resets the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- nvicDisableVector(UART0_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART0;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- nvicDisableVector(UART1_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART1;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- nvicDisableVector(UART2_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART2;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.h b/os/hal/ports/KINETIS/KL2x/st_lld.h deleted file mode 100644 index 24044e5..0000000 --- a/os/hal/ports/KINETIS/KL2x/st_lld.h +++ /dev/null @@ -1,156 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/st_lld.h
- * @brief ST Driver subsystem low level driver header.
- * @details This header is designed to be include-able without having to
- * include other files from the HAL.
- *
- * @addtogroup ST
- * @{
- */
-
-#ifndef _ST_LLD_H_
-#define _ST_LLD_H_
-
-#include "mcuconf.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SysTick timer IRQ priority.
- */
-#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_ST_IRQ_PRIORITY 8
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void st_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Driver inline functions. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the time counter value.
- *
- * @return The counter value.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_counter(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Starts the alarm.
- * @note Makes sure that no spurious alarms are triggered after
- * this call.
- *
- * @param[in] time the time to be set for the first alarm
- *
- * @notapi
- */
-static inline void st_lld_start_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-
-}
-
-/**
- * @brief Sets the alarm time.
- *
- * @param[in] time the time to be set for the next alarm
- *
- * @notapi
- */
-static inline void st_lld_set_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Returns the current alarm time.
- *
- * @return The currently set alarm time.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_alarm(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Determines if the alarm is active.
- *
- * @return The alarm status.
- * @retval false if the alarm is not active.
- * @retval true is the alarm is active
- *
- * @notapi
- */
-static inline bool st_lld_is_alarm_active(void) {
-
- return false;
-}
-
-#endif /* _ST_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/ext_lld.c b/os/hal/ports/KINETIS/LLD/ext_lld.c index e85f032..21bb6e0 100644 --- a/os/hal/ports/KINETIS/LLD/ext_lld.c +++ b/os/hal/ports/KINETIS/LLD/ext_lld.c @@ -89,6 +89,19 @@ static void ext_lld_exti_irq_enable(void) { #if KINETIS_EXT_PORTA_WIDTH > 0
nvicEnableVector(PINA_IRQn, KINETIS_EXT_PORTA_IRQ_PRIORITY);
#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicEnableVector(PINBCDE_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicEnableVector(PINCD_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
#if KINETIS_EXT_PORTB_WIDTH > 0
nvicEnableVector(PINB_IRQn, KINETIS_EXT_PORTB_IRQ_PRIORITY);
#endif
@@ -101,6 +114,7 @@ static void ext_lld_exti_irq_enable(void) { #if KINETIS_EXT_PORTE_WIDTH > 0
nvicEnableVector(PINE_IRQn, KINETIS_EXT_PORTE_IRQ_PRIORITY);
#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
}
/**
@@ -113,6 +127,19 @@ static void ext_lld_exti_irq_disable(void) { #if KINETIS_EXT_PORTA_WIDTH > 0
nvicDisableVector(PINA_IRQn);
#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicDisableVector(PINBCDE_IRQn);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicDisableVector(PINCD_IRQn);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
#if KINETIS_EXT_PORTB_WIDTH > 0
nvicDisableVector(PINB_IRQn);
#endif
@@ -125,6 +152,7 @@ static void ext_lld_exti_irq_disable(void) { #if KINETIS_EXT_PORTE_WIDTH > 0
nvicDisableVector(PINE_IRQn);
#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
}
/*===========================================================================*/
@@ -164,6 +192,49 @@ OSAL_IRQ_HANDLER(KINETIS_PORTA_IRQ_VECTOR) { }
#endif /* KINETIS_EXT_PORTA_WIDTH > 0 */
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTB_WIDTH > 0)
+ irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
+#endif
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+#if (KINETIS_EXT_PORTE_WIDTH > 0)
+ irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
/**
* @brief PORTB interrupt handler.
*
@@ -224,6 +295,8 @@ OSAL_IRQ_HANDLER(KINETIS_PORTE_IRQ_VECTOR) { }
#endif /* KINETIS_EXT_PORTE_WIDTH > 0 */
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.c b/os/hal/ports/KINETIS/LLD/gpt_lld.c index 09d759b..6e88f88 100644 --- a/os/hal/ports/KINETIS/K20x/gpt_lld.c +++ b/os/hal/ports/KINETIS/LLD/gpt_lld.c @@ -30,11 +30,6 @@ /* Driver local definitions. */
/*===========================================================================*/
-#define KINETIS_PIT0_HANDLER VectorB8
-#define KINETIS_PIT1_HANDLER VectorBC
-#define KINETIS_PIT2_HANDLER VectorC0
-#define KINETIS_PIT3_HANDLER VectorC4
-
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -75,6 +70,10 @@ GPTDriver GPTD4; /* Driver local variables and types. */
/*===========================================================================*/
+#if KINETIS_HAS_PIT_COMMON_IRQ
+static uint8_t active_channels = 0;
+#endif /* KINETIS_HAS_PIT_COMMON_IRQ */
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -87,7 +86,7 @@ GPTDriver GPTD4; static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
/* Clear the interrupt */
- gptp->channel->TFLG |= PIT_TCTRL_TIE;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
if (gptp->state == GPT_ONESHOT) {
gptp->state = GPT_READY; /* Back in GPT_READY state. */
@@ -100,82 +99,89 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
#if KINETIS_GPT_USE_PIT0
-#if !defined(KINETIS_PIT0_HANDLER)
-#error "KINETIS_PIT0_HANDLER not defined"
-#endif
/**
* @brief PIT1 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT0_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD1);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT0 */
#if KINETIS_GPT_USE_PIT1
-#if !defined(KINETIS_PIT1_HANDLER)
-#error "KINETIS_PIT1_HANDLER not defined"
-#endif
/**
* @brief PIT1 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT1_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD2);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT1 */
#if KINETIS_GPT_USE_PIT2
-#if !defined(KINETIS_PIT2_HANDLER)
-#error "KINETIS_PIT2_HANDLER not defined"
-#endif
/**
* @brief PIT2 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT2_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD3);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT2 */
#if KINETIS_GPT_USE_PIT3
-#if !defined(KINETIS_PIT3_HANDLER)
-#error "KINETIS_PIT3_HANDLER not defined"
-#endif
/**
* @brief PIT3 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT3_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT3_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD4);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT3 */
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+/**
+ * @brief Common PIT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+#if KINETIS_GPT_USE_PIT0
+ if(GPTD1.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD1);
+#endif /* KINETIS_GPT_USE_PIT0 */
+#if KINETIS_GPT_USE_PIT1
+ if(GPTD2.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD2);
+#endif /* KINETIS_GPT_USE_PIT1 */
+#if KINETIS_GPT_USE_PIT2
+ if(GPTD3.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD3);
+#endif /* KINETIS_GPT_USE_PIT2 */
+#if KINETIS_GPT_USE_PIT3
+ if(GPTD4.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD4);
+#endif /* KINETIS_GPT_USE_PIT3 */
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -227,6 +233,8 @@ void gpt_lld_start(GPTDriver *gptp) { SIM->SCGC6 |= SIM_SCGC6_PIT;
gptp->clock = KINETIS_SYSCLK_FREQUENCY;
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
#if KINETIS_GPT_USE_PIT0
if (&GPTD1 == gptp) {
nvicEnableVector(PITChannel0_IRQn, KINETIS_GPT_PIT0_IRQ_PRIORITY);
@@ -248,6 +256,10 @@ void gpt_lld_start(GPTDriver *gptp) { }
#endif
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ nvicEnableVector(PIT_IRQn, KINETIS_GPT_PIT_IRQ_PRIORITY);
+ active_channels++;
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
}
/* Prescaler value calculation.*/
@@ -275,7 +287,9 @@ void gpt_lld_stop(GPTDriver *gptp) { gptp->channel->TCTRL = 0;
/* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLG_TIF;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
+
+#if !KINETIS_HAS_PIT_COMMON_IRQ
#if KINETIS_GPT_USE_PIT0
if (&GPTD1 == gptp) {
@@ -297,6 +311,11 @@ void gpt_lld_stop(GPTDriver *gptp) { nvicDisableVector(PITChannel3_IRQn);
}
#endif
+
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ if(--active_channels == 0)
+ nvicDisableVector(PIT_IRQn);
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
}
}
@@ -311,13 +330,13 @@ void gpt_lld_stop(GPTDriver *gptp) { void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
/* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLG_TIF;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
/* Set the interval */
- gptp->channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
+ gpt_lld_change_interval(gptp, interval);
/* Start the timer */
- gptp->channel->TCTRL |= PIT_TCTRL_TIE | PIT_TCTRL_TEN;
+ gptp->channel->TCTRL |= PIT_TCTRLn_TIE | PIT_TCTRLn_TEN;
}
/**
@@ -351,16 +370,16 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { channel->TCTRL = 0;
/* Clear the interrupt flag */
- channel->TFLG |= PIT_TFLG_TIF;
+ channel->TFLG |= PIT_TFLGn_TIF;
/* Set the interval */
channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
/* Enable Timer but keep interrupts disabled */
- channel->TCTRL = PIT_TCTRL_TEN;
+ channel->TCTRL = PIT_TCTRLn_TEN;
/* Wait for the interrupt flag to be set */
- while (!(channel->TFLG & PIT_TFLG_TIF))
+ while (!(channel->TFLG & PIT_TFLGn_TIF))
;
/* Disable timer and disable interrupts */
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.h b/os/hal/ports/KINETIS/LLD/gpt_lld.h index 0e72309..5c3e233 100644 --- a/os/hal/ports/KINETIS/K20x/gpt_lld.h +++ b/os/hal/ports/KINETIS/LLD/gpt_lld.h @@ -103,6 +103,14 @@ #define KINETIS_GPT_PIT3_IRQ_PRIORITY 7
#endif
+/**
+ * @brief GPTD* common interrupt priority level setting.
+ */
+#if (KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_GPT_PIT_IRQ_PRIORITY)) \
+ || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT_IRQ_PRIORITY 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -123,31 +131,60 @@ #error "PIT3 not present in the selected device"
#endif
-#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
+#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
!KINETIS_GPT_USE_PIT2 && !KINETIS_GPT_USE_PIT3
#error "GPT driver activated but no PIT peripheral assigned"
#endif
-#if KINETIS_GPT_USE_PIT0 && \
+#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT0"
#endif
-#if KINETIS_GPT_USE_PIT1 && \
+#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT1"
#endif
-#if KINETIS_GPT_USE_PIT2 && \
+#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT2"
#endif
-#if KINETIS_GPT_USE_PIT3 && \
+#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT3"
#endif
+#if KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT"
+#endif
+
+#if KINETIS_GPT_USE_PIT0 && !defined(KINETIS_PIT0_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT0_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !defined(KINETIS_PIT1_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT1_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !defined(KINETIS_PIT2_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT2_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !defined(KINETIS_PIT3_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT3_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_PIT_IRQ_VECTOR)
+#error "KINETIS_PIT_IRQ_VECTOR not defined"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -226,7 +263,9 @@ struct GPTDriver { * @notapi
*/
#define gpt_lld_change_interval(gptp, interval) \
- ((gptp)->channel->LDVAL = (uint32_t)((interval)))
+ ((gptp)->channel->LDVAL = (uint32_t)( \
+ ( (gptp)->clock / (gptp)->config->frequency ) * \
+ ( interval ) ))
/**
* @brief Returns the interval of GPT peripheral.
@@ -237,7 +276,9 @@ struct GPTDriver { *
* @notapi
*/
-#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].LDVAL)
+#define gpt_lld_get_interval(gptp) \
+ ((uint32_t)( ( (uint64_t)(gptp)->channel->LDVAL * (gptp)->config->frequency ) / \
+ ( (uint32_t)(gptp)->clock ) ))
/**
* @brief Returns the counter value of GPT peripheral.
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.c b/os/hal/ports/KINETIS/LLD/i2c_lld.c index 4e42d16..3659a93 100644 --- a/os/hal/ports/KINETIS/LLD/i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/i2c_lld.c
+ * @file KINETIS/LLD/i2c_lld.c
* @brief KINETIS I2C subsystem low level driver source.
*
* @addtogroup I2C
@@ -191,8 +191,7 @@ OSAL_IRQ_HANDLER(KINETIS_I2C0_IRQ_VECTOR) { #if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/* FIXME: KL2x has I2C1 on Vector64; K2x don't have I2C1! */
-OSAL_IRQ_HANDLER(Vector64) {
+OSAL_IRQ_HANDLER(KINETIS_I2C1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&I2CD2);
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.h b/os/hal/ports/KINETIS/LLD/i2c_lld.h index 11de3ae..5f1ed87 100644 --- a/os/hal/ports/KINETIS/LLD/i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/i2c_lld.h
+ * @file KINETIS/LLD/i2c_lld.h
* @brief KINETIS I2C subsystem low level driver header.
*
* @addtogroup I2C
@@ -63,10 +63,38 @@ #endif
/** @} */
+/**
+ * @brief I2C0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C0_PRIORITY 12
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C1_PRIORITY 12
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/** @brief error checks */
+#if KINETIS_I2C_USE_I2C0 && !KINETIS_HAS_I2C0
+#error "I2C0 not present in the selected device"
+#endif
+
+#if KINETIS_I2C_USE_I2C1 && !KINETIS_HAS_I2C1
+#error "I2C1 not present in the selected device"
+#endif
+
+
+#if !(KINETIS_I2C_USE_I2C0 || KINETIS_I2C_USE_I2C1)
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.c b/os/hal/ports/KINETIS/LLD/pal_lld.c index 101d574..b307833 100644 --- a/os/hal/ports/KINETIS/K20x/pal_lld.c +++ b/os/hal/ports/KINETIS/LLD/pal_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file MK20D5/pal_lld.c
+ * @file KINETIS/LLD/pal_lld.c
* @brief PAL subsystem low level driver.
*
* @addtogroup PAL
@@ -108,7 +108,7 @@ void _pal_lld_setpadmode(ioportid_t port, PORT_TypeDef *portcfg = NULL;
- chDbgAssert(pad <= 31, "pal_lld_setpadmode() #1, invalid pad");
+ chDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
if (mode == PAL_MODE_OUTPUT_PUSHPULL)
port->PDDR |= ((uint32_t) 1 << pad);
@@ -134,10 +134,14 @@ void _pal_lld_setpadmode(ioportid_t port, case PAL_MODE_OUTPUT_PUSHPULL:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
break;
+#if KINETIS_GPIO_HAS_OPENDRAIN
case PAL_MODE_OUTPUT_OPENDRAIN:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
PORTx_PCRn_ODE;
break;
+#else
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+#endif
case PAL_MODE_INPUT_PULLUP:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
PORTx_PCRn_PE |
diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.h b/os/hal/ports/KINETIS/LLD/pal_lld.h index 242583a..2bd9872 100644 --- a/os/hal/ports/KINETIS/K20x/pal_lld.h +++ b/os/hal/ports/KINETIS/LLD/pal_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file MK20D5/pal_lld.h
+ * @file KINETIS/LLD/pal_lld.h
* @brief PAL subsystem low level driver header.
*
* @addtogroup PAL
@@ -31,13 +31,13 @@ /* Unsupported modes and specific modes */
/*===========================================================================*/
-#define PAL_MODE_ALTERNATIVE_1 10
-#define PAL_MODE_ALTERNATIVE_2 11
-#define PAL_MODE_ALTERNATIVE_3 12
-#define PAL_MODE_ALTERNATIVE_4 13
-#define PAL_MODE_ALTERNATIVE_5 14
-#define PAL_MODE_ALTERNATIVE_6 15
-#define PAL_MODE_ALTERNATIVE_7 16
+#define PAL_MODE_ALTERNATIVE_1 0x10
+#define PAL_MODE_ALTERNATIVE_2 0x11
+#define PAL_MODE_ALTERNATIVE_3 0x12
+#define PAL_MODE_ALTERNATIVE_4 0x13
+#define PAL_MODE_ALTERNATIVE_5 0x14
+#define PAL_MODE_ALTERNATIVE_6 0x15
+#define PAL_MODE_ALTERNATIVE_7 0x16
#define PIN_MUX_ALTERNATIVE(x) PORTx_PCRn_MUX(x)
@@ -151,7 +151,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_readport(port) (port)->PDIR
+#define pal_lld_readport(port) \
+ (port)->PDIR
/**
* @brief Reads the output latch.
@@ -163,7 +164,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_readlatch(port) (port)->PDOR
+#define pal_lld_readlatch(port) \
+ (port)->PDOR
/**
* @brief Writes a bits mask on a I/O port.
@@ -173,7 +175,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_writeport(port, bits) (port)->PDOR = (bits)
+#define pal_lld_writeport(port, bits) \
+ (port)->PDOR = (bits)
/**
* @brief Sets a bits mask on a I/O port.
@@ -186,7 +189,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_setport(port, bits) (port)->PSOR = (bits)
+#define pal_lld_setport(port, bits) \
+ (port)->PSOR = (bits)
/**
* @brief Clears a bits mask on a I/O port.
@@ -199,7 +203,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_clearport(port, bits) (port)->PCOR = (bits)
+#define pal_lld_clearport(port, bits) \
+ (port)->PCOR = (bits)
/**
* @brief Toggles a bits mask on a I/O port.
@@ -212,7 +217,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_toggleport(port, bits) (port)->PTOR = (bits)
+#define pal_lld_toggleport(port, bits) \
+ (port)->PTOR = (bits)
/**
* @brief Reads a group of bits.
@@ -364,6 +370,11 @@ extern "C" { void _pal_lld_setpadmode(ioportid_t port,
uint8_t pad,
iomode_t mode);
+ uint8_t _pal_lld_readpad(ioportid_t port,
+ uint8_t pad);
+ void _pal_lld_writepad(ioportid_t port,
+ uint8_t pad,
+ uint8_t bit);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/KINETIS/LLD/serial_lld.c b/os/hal/ports/KINETIS/LLD/serial_lld.c new file mode 100644 index 0000000..c80cf22 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/serial_lld.c @@ -0,0 +1,583 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.c
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] isr UART s1 register value
+ */
+static void set_error(SerialDriver *sdp, uint8_t s1) {
+ eventflags_t sts = 0;
+
+ if (s1 & UARTx_S1_OR)
+ sts |= SD_OVERRUN_ERROR;
+ if (s1 & UARTx_S1_PF)
+ sts |= SD_PARITY_ERROR;
+ if (s1 & UARTx_S1_FE)
+ sts |= SD_FRAMING_ERROR;
+ if (s1 & UARTx_S1_NF)
+ sts |= SD_NOISE_ERROR;
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common error IRQ handler.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_error_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
+ /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ * then reading D.*/
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1) {
+ if(s1 & UARTx_S1_IDLE) {
+ *(u->s1_p) |= UARTx_S1_IDLE;
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ }
+ return;
+ }
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
+ }
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ if (s1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&sdp->iqueue, *(u->d_p)) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (s1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ *(u->c2_p) &= ~UARTx_C2_TIE;
+ } else {
+ *(u->d_p) = b;
+ }
+ }
+
+ serve_error_interrupt(sdp);
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+
+ if (*(u->s1_p) & UARTx_S1_TDRE) {
+ msg_t b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ *(u->d_p) = b;
+ *(u->c2_p) |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
+
+ UART_w_TypeDef *uart = &(sdp->uart);
+ uint32_t divisor;
+
+ /* Discard any incoming data. */
+ while (*(uart->s1_p) & UARTx_S1_RDRF) {
+ (void)*(uart->d_p);
+ }
+
+ /* Disable UART while configuring */
+ *(uart->c2_p) &= ~(UARTx_C2_RE | UARTx_C2_TE);
+
+ /* The clock sources for various UARTs can be different. */
+ divisor=KINETIS_BUSCLK_FREQUENCY;
+
+#if defined(KL2x)
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ /* UART0 can be clocked from several sources on KL2x. */
+ divisor = KINETIS_UART0_CLOCK_FREQ;
+ /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
+ /* Note: OSR only works on KL2x/UART0; further UARTs have fixed 16. */
+ *(uart->c4_p) = UARTx_C4_OSR(16 - 1);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#elif defined(K20x) /* KL2x */
+
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+#if KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART0 */
+#if KINETIS_SERIAL_USE_UART1
+ if(sdp == &SD2)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#else /* K20x */
+#error Baud rate selection not implemented for this MCU type
+#endif /* K20x */
+
+ divisor = (divisor * 2 + 1) / config->sc_speed;
+
+ *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
+ *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
+#if defined(K20x)
+ *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
+#endif /* K20x */
+
+ /* Line settings. */
+ *(uart->c1_p) = 0;
+ /* Enable error event interrupts (overrun, noise, framing, parity) */
+ *(uart->c3_p) = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+ /* Enable the peripheral; including receive interrupts. */
+ *(uart->c2_p) |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+#if ! KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.bdh_p = &(UART0->BDH);
+ SD1.uart.bdl_p = &(UART0->BDL);
+ SD1.uart.c1_p = &(UART0->C1);
+ SD1.uart.c2_p = &(UART0->C2);
+ SD1.uart.c3_p = &(UART0->C3);
+ SD1.uart.c4_p = &(UART0->C4);
+ SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
+ SD1.uart.s2_p = &(UART0->S2);
+ SD1.uart.d_p = &(UART0->D);
+#else /* ! KINETIS_SERIAL0_IS_LPUART */
+ /* little endian! */
+ SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD1.uart.c2_p = ((uint8_t *)&(LPUART0->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD1.uart.c3_p = ((uint8_t *)&(LPUART0->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD1.uart.c4_p = ((uint8_t *)&(LPUART0->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD1.uart.s1_p = ((uint8_t *)&(LPUART0->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD1.uart.s2_p = ((uint8_t *)&(LPUART0->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD1.uart.d_p = ((uint8_t *)&(LPUART0->DATA)) + 0; /* D: DATA, byte 4 */
+#endif /* ! KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SD1.uart.uartlp_p = UART0;
+ SD1.uart.uart_p = NULL;
+#elif KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.lpuart_p = LPUART0;
+ SD1.uart.uart_p = NULL;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SD1.uart.uart_p = UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+#if ! KINETIS_SERIAL1_IS_LPUART
+ SD2.uart.bdh_p = &(UART1->BDH);
+ SD2.uart.bdl_p = &(UART1->BDL);
+ SD2.uart.c1_p = &(UART1->C1);
+ SD2.uart.c2_p = &(UART1->C2);
+ SD2.uart.c3_p = &(UART1->C3);
+ SD2.uart.c4_p = &(UART1->C4);
+ SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
+ SD2.uart.s2_p = &(UART1->S2);
+ SD2.uart.d_p = &(UART1->D);
+ SD2.uart.uart_p = UART1;
+#else /* ! KINETIS_SERIAL1_IS_LPUART */
+ /* little endian! */
+ SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD2.uart.c2_p = ((uint8_t *)&(LPUART1->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD2.uart.c3_p = ((uint8_t *)&(LPUART1->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD2.uart.c4_p = ((uint8_t *)&(LPUART1->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD2.uart.s1_p = ((uint8_t *)&(LPUART1->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD2.uart.s2_p = ((uint8_t *)&(LPUART1->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD2.uart.d_p = ((uint8_t *)&(LPUART1->DATA)) + 0; /* D: DATA, byte 4 */
+ SD2.uart.lpuart_p = LPUART1;
+ SD2.uart.uart_p = NULL;
+#endif /* ! KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart.bdh_p = &(UART2->BDH);
+ SD3.uart.bdl_p = &(UART2->BDL);
+ SD3.uart.c1_p = &(UART2->C1);
+ SD3.uart.c2_p = &(UART2->C2);
+ SD3.uart.c3_p = &(UART2->C3);
+ SD3.uart.c4_p = &(UART2->C4);
+ SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
+ SD3.uart.s2_p = &(UART2->S2);
+ SD3.uart.d_p = &(UART2->D);
+ SD3.uart.uart_p = UART2;
+#endif /* KINETIS_SERIAL_USE_UART2 */
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART0;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) |
+ SIM_SOPT2_LPUART0SRC(KINETIS_UART0_CLOCK_SRC);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
+ SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
+#endif /* KINETIS_SERIAL0_IS_UARTLP */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ nvicEnableVector(UART0Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicEnableVector(LPUART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART1;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) |
+ SIM_SOPT2_LPUART1SRC(KINETIS_UART1_CLOCK_SRC);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ nvicEnableVector(UART1Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicEnableVector(LPUART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ nvicEnableVector(UART2Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART0Status_IRQn);
+ nvicDisableVector(UART0Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicDisableVector(LPUART0_IRQn);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicDisableVector(UART0_IRQn);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART0;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART1Status_IRQn);
+ nvicDisableVector(UART1Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicDisableVector(LPUART1_IRQn);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicDisableVector(UART1_IRQn);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART1;
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART2Status_IRQn);
+ nvicDisableVector(UART2Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicDisableVector(UART2_IRQn);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.h b/os/hal/ports/KINETIS/LLD/serial_lld.h index 2d003b0..cc66eb3 100644 --- a/os/hal/ports/KINETIS/KL2x/serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/serial_lld.h @@ -82,12 +82,44 @@ #define KINETIS_SERIAL_UART2_PRIORITY 12
#endif
+/**
+ * @brief UART0 clock source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1 /* MCGFLLCLK clock, or MCGPLLCLK/2; or IRC48M */
+#endif
+
+/**
+ * @brief UART1 clock source.
+ */
+#if !defined(KINETIS_UART1_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART1_CLOCK_SRC 1 /* IRC48M */
+#endif
+
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/** @brief error checks */
+#if KINETIS_SERIAL_USE_UART0 && !KINETIS_HAS_SERIAL0
+#error "UART0 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !KINETIS_HAS_SERIAL1
+#error "UART1 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !KINETIS_HAS_SERIAL2
+#error "UART2 not present in the selected device"
+#endif
+
+#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
+ KINETIS_SERIAL_USE_UART2)
+#error "Serial driver activated but no UART peripheral assigned"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -108,6 +140,31 @@ typedef struct { } SerialConfig;
/**
+ * @brief Generic UART register structure.
+ * @note Individual UART register blocks (even within the same chip) can differ.
+ */
+
+typedef struct {
+ volatile uint8_t* bdh_p;
+ volatile uint8_t* bdl_p;
+ volatile uint8_t* c1_p;
+ volatile uint8_t* c2_p;
+ volatile uint8_t* c3_p;
+ volatile uint8_t* c4_p;
+ volatile uint8_t* s1_p;
+ volatile uint8_t* s2_p;
+ volatile uint8_t* d_p;
+ UART_TypeDef *uart_p;
+#if KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP
+ UARTLP_TypeDef *uartlp_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP */
+#if (KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART) \
+ || (KINETIS_SERIAL_USE_UART1 && KINETIS_SERIAL1_IS_LPUART)
+ LPUART_TypeDef *lpuart_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART */
+} UART_w_TypeDef;
+
+/**
* @brief @p SerialDriver specific data.
*/
#define _serial_driver_data \
@@ -124,7 +181,7 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the UART registers block.*/ \
- UARTLP_TypeDef *uart;
+ UART_w_TypeDef uart;
/*===========================================================================*/
/* Driver macros. */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.c b/os/hal/ports/KINETIS/LLD/st_lld.c index 1f8cb63..e6ed9e5 100644 --- a/os/hal/ports/KINETIS/KL2x/st_lld.c +++ b/os/hal/ports/KINETIS/LLD/st_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/KL2x/st_lld.c
+ * @file KINETIS/LLD/st_lld.c
* @brief ST Driver subsystem low level driver code.
*
* @addtogroup ST
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.h b/os/hal/ports/KINETIS/LLD/st_lld.h index 24044e5..c67a5d0 100644 --- a/os/hal/ports/KINETIS/K20x/st_lld.h +++ b/os/hal/ports/KINETIS/LLD/st_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/st_lld.h
+ * @file KINETIS/LLD/st_lld.h
* @brief ST Driver subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
diff --git a/os/hal/ports/KINETIS/LLD/usb_lld.c b/os/hal/ports/KINETIS/LLD/usb_lld.c new file mode 100644 index 0000000..159aef9 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/usb_lld.c @@ -0,0 +1,832 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.c
+ * @brief KINETIS USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USB0 driver identifier.*/
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief IN EP0 state.
+ */
+USBInEndpointState ep0in;
+
+/**
+ * @brief OUT EP0 state.
+ */
+USBOutEndpointState ep0out;
+
+/**
+ * @brief Buffer for the EP0 setup packets.
+ */
+static uint8_t ep0setup_buffer[8];
+
+/**
+ * @brief EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+ USB_EP_MODE_TYPE_CTRL,
+ _usb_ep0setup,
+ _usb_ep0in,
+ _usb_ep0out,
+ 64,
+ 64,
+ &ep0in,
+ &ep0out,
+ 1,
+ ep0setup_buffer
+};
+
+/*
+ * Buffer Descriptor Table (BDT)
+ */
+
+/*
+ * Buffer Descriptor (BD)
+ * */
+typedef struct {
+ uint32_t desc;
+ uint8_t* addr;
+} bd_t;
+
+/*
+ * Buffer Descriptor fields - p.889
+ */
+#define BDT_OWN 0x80
+#define BDT_DATA 0x40
+#define BDT_KEEP 0x20
+#define BDT_NINC 0x10
+#define BDT_DTS 0x08
+#define BDT_STALL 0x04
+
+#define BDT_DESC(bc, data) (BDT_OWN | BDT_DTS | ((data&0x1)<<6) | ((bc) << 16))
+
+/*
+ * BDT PID - p.891
+ */
+#define BDT_PID_OUT 0x01
+#define BDT_PID_IN 0x09
+#define BDT_PID_SETUP 0x0D
+#define BDT_TOK_PID(n) (((n)>>2)&0xF)
+
+/*
+ * BDT index fields
+ */
+#define DATA0 0
+#define DATA1 1
+
+#define RX 0
+#define TX 1
+
+#define EVEN 0
+#define ODD 1
+
+#define BDT_INDEX(endpoint, tx, odd) (((endpoint)<<2) | ((tx)<<1) | (odd))
+/*
+ * Get RX-ed/TX-ed bytes count from BDT entry
+ */
+#define BDT_BC(n) (((n)>>16)&0x3FF)
+
+/* The USB-FS needs 2 BDT entry per endpoint direction
+ * that adds to: 2*2*16 BDT entries for 16 bi-directional EP
+ */
+static volatile bd_t _bdt[(KINETIS_USB_ENDPOINTS)*2*2] __attribute__((aligned(512)));
+
+/* FIXME later with dyn alloc
+ * 16 EP
+ * 2 directions per EP
+ * 2 buffer per direction
+ * => 64 buffers
+ */
+static uint8_t _usbb[KINETIS_USB_ENDPOINTS*4][64] __attribute__((aligned(4)));
+static volatile uint8_t _usbbn=0;
+uint8_t* usb_alloc(uint8_t size)
+{
+ (void)size;
+ if(_usbbn < (KINETIS_USB_ENDPOINTS)*4)
+ return _usbb[_usbbn++];
+ while(1); /* Should not happen, ever */
+}
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/* Called from locked ISR. */
+void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBInEndpointState *isp = epc->in_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
+
+ if (n > (size_t)epc->in_maxsize)
+ n = (size_t)epc->in_maxsize;
+
+ /* Copy from buf to _usbb[] */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ bd->addr[i] = isp->txbuf[i];
+
+ /* Update the Buffer status */
+ bd->desc = BDT_DESC(n, isp->data_bank);
+ /* Toggle the odd and data bits for next TX */
+ isp->data_bank ^= DATA1;
+ isp->odd_even ^= ODD;
+}
+
+/* Called from locked ISR. */
+void usb_packet_receive(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBOutEndpointState *osp = epc->out_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, RX, osp->odd_even)];
+
+ if (n > (size_t)epc->out_maxsize)
+ n = (size_t)epc->out_maxsize;
+
+ /* Copy from _usbb[] to buf */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ osp->rxbuf[i] = bd->addr[i];
+
+ /* Update the Buffer status
+ * Set current buffer to same DATA bank and then toggle.
+ * Since even/odd buffers are ping-pong and setup re-initialized them
+ * this should work correctly */
+ bd->desc = BDT_DESC(epc->out_maxsize, osp->data_bank);
+ osp->data_bank ^= DATA1;
+ usb_lld_start_out(usbp, ep);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*============================================================================*/
+
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+/**
+ * @brief USB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
+ USBDriver *usbp = &USBD1;
+ uint8_t istat = USB0->ISTAT;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* 04 - Bit2 - Start Of Frame token received */
+ if(istat & USBx_ISTAT_SOFTOK) {
+ _usb_isr_invoke_sof_cb(usbp);
+ USB0->ISTAT = USBx_ISTAT_SOFTOK;
+ }
+
+ /* 08 - Bit3 - Token processing completed */
+ while(istat & USBx_ISTAT_TOKDNE) {
+ uint8_t stat = USB0->STAT;
+ uint8_t ep = stat >> 4;
+ if(ep > KINETIS_USB_ENDPOINTS) {
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+ const USBEndpointConfig *epc = usbp->epc[ep];
+
+ /* Get the correct BDT entry */
+ uint8_t odd_even = (stat & USBx_STAT_ODD_MASK) >> USBx_STAT_ODD_SHIFT;
+ uint8_t tx_rx = (stat & USBx_STAT_TX_MASK) >> USBx_STAT_TX_SHIFT;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep,tx_rx,odd_even)];
+
+ /* Update the ODD/EVEN state for RX */
+ if(tx_rx == RX && epc->out_state != NULL)
+ epc->out_state->odd_even = odd_even;
+
+ switch(BDT_TOK_PID(bd->desc))
+ {
+ case BDT_PID_SETUP: // SETUP
+ {
+ /* Clear any pending IN stuff */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ /* Also in the chibios state machine */
+ (usbp)->receiving &= ~1;
+ /* After a SETUP, IN is always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
+
+ /* Call SETUP function (ChibiOS core), which sends back stuff */
+ _usb_isr_invoke_setup_cb(usbp, ep);
+ /* Buffer is released by the above callback. */
+ /* from Paul: "unfreeze the USB, now that we're ready" */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+ } break;
+ case BDT_PID_IN: // IN
+ {
+ if(epc->in_state == NULL)
+ break;
+ /* Special case for SetAddress for EP0 */
+ if(ep == 0 && (((uint16_t)usbp->setup[0]<<8)|usbp->setup[1]) == 0x0500)
+ {
+ usbp->address = usbp->setup[2];
+ usb_lld_set_address(usbp);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
+ usbp->state = USB_SELECTED;
+ }
+ uint16_t txed = BDT_BC(bd->desc);
+ epc->in_state->txcnt += txed;
+ if(epc->in_state->txcnt < epc->in_state->txsize)
+ {
+ epc->in_state->txbuf += txed;
+ osalSysLockFromISR();
+ usb_packet_transmit(usbp,ep,epc->in_state->txsize - epc->in_state->txcnt);
+ osalSysUnlockFromISR();
+ }
+ else
+ {
+ if(epc->in_cb != NULL)
+ _usb_isr_invoke_in_cb(usbp,ep);
+ }
+ } break;
+ case BDT_PID_OUT: // OUT
+ {
+ if(epc->out_state == NULL)
+ break;
+ uint16_t rxed = BDT_BC(bd->desc);
+
+ osalSysLockFromISR();
+ usb_packet_receive(usbp,ep,rxed);
+ osalSysUnlockFromISR();
+ if(rxed)
+ {
+ epc->out_state->rxbuf += rxed;
+
+ /* Update transaction data */
+ epc->out_state->rxcnt += rxed;
+ epc->out_state->rxsize -= rxed;
+ epc->out_state->rxpkts -= 1;
+
+ /* The transaction is completed if the specified number of packets
+ has been received or the current packet is a short packet.*/
+ if ((rxed < epc->out_maxsize) || (epc->out_state->rxpkts == 0))
+ {
+ if(epc->out_cb != NULL)
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+ }
+ } break;
+ default:
+ break;
+ }
+ USB0->ISTAT = USBx_ISTAT_TOKDNE;
+ istat = USB0->ISTAT;
+ }
+
+ /* 01 - Bit0 - Valid USB Reset received */
+ if(istat & USBx_ISTAT_USBRST) {
+ _usb_reset(usbp);
+ USB0->ISTAT = USBx_ISTAT_USBRST;
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+
+ /* 80 - Bit7 - STALL handshake received */
+ if(istat & USBx_ISTAT_STALL) {
+ USB0->ISTAT = USBx_ISTAT_STALL;
+ }
+
+ /* 02 - Bit1 - ERRSTAT condition triggered */
+ if(istat & USBx_ISTAT_ERROR) {
+ uint8_t err = USB0->ERRSTAT;
+ USB0->ERRSTAT = err;
+ USB0->ISTAT = USBx_ISTAT_ERROR;
+ }
+
+ /* 10 - Bit4 - Constant IDLE on USB bus detected */
+ if(istat & USBx_ISTAT_SLEEP) {
+ /* This seems to fire a few times before the device is
+ * configured - need to ignore those occurences somehow. */
+ /* The other option would be to only activate INTEN_SLEEPEN
+ * on CONFIGURED event, but that would need to be done in
+ * user firmware. */
+ if(usbp->state == USB_ACTIVE) {
+ _usb_suspend(usbp);
+ /* Enable interrupt on resume */
+ USB0->INTEN |= USBx_INTEN_RESUMEEN;
+ }
+
+ // low-power version (check!):
+ // enable wakeup interrupt on resume USB signaling
+ // (check that it was a wakeup int with USBx_USBTRC0_USB_RESUME_INT)
+ //? USB0->USBTRC0 |= USBx_USBTRC0_USBRESMEN
+ // suspend the USB module
+ //? USB0->USBCTRL |= USBx_USBCTRL_SUSP;
+
+ USB0->ISTAT = USBx_ISTAT_SLEEP;
+ }
+
+ /* 20 - Bit5 - Resume - Only allowed in sleep=suspend mode */
+ if(istat & USBx_ISTAT_RESUME) {
+ /* Disable interrupt on resume (should be disabled
+ * during normal operation according to datasheet). */
+ USB0->INTEN &= ~USBx_INTEN_RESUMEEN;
+
+ // low power version (check!):
+ // desuspend the USB module
+ //? USB0->USBCTRL &= ~USBx_USBCTRL_SUSP;
+ // maybe also
+ //? USB0->CTL = USBx_CTL_USBENSOFEN;
+ _usb_wakeup(usbp);
+ USB0->ISTAT = USBx_ISTAT_RESUME;
+ }
+
+ /* 40 - Bit6 - ATTACH - used */
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_USB_USE_USB0 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+ /* Driver initialization.*/
+ usbObjectInit(&USBD1);
+
+#if KINETIS_USB_USE_USB0
+
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC;
+
+#if defined(K20x5) || defined(K20x7)
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+
+ /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ #define KINETIS_USBCLK_FREQUENCY 48000000UL
+ uint32_t i,j;
+ for(i=0; i < 2; i++) {
+ for(j=0; j < 8; j++) {
+ if((KINETIS_PLLCLK_FREQUENCY * (i+1)) == (KINETIS_USBCLK_FREQUENCY*(j+1))) {
+ SIM->CLKDIV2 = i | SIM_CLKDIV2_USBDIV(j);
+ goto usbfrac_match_found;
+ }
+ }
+ }
+ usbfrac_match_found:
+ chDbgAssert(i<2 && j <8,"USB Init error");
+
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error USB clock setting not implemented for this KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#elif defined(KL25) || defined (KL26) || defined(KL27)
+
+ /* No extra clock dividers for USB clock */
+
+#else /* defined(KL25) || defined (KL26) || defined(KL27) */
+#error USB driver not implemented for your MCU type
+#endif
+
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Configures and activates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+ /* Clear BDT */
+ uint8_t i;
+ for(i=0;i<KINETIS_USB_ENDPOINTS;i++) {
+ _bdt[i].desc=0;
+ _bdt[i].addr=0;
+ }
+
+ /* Enable Clock */
+#if KINETIS_USB0_IS_USBOTG
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG;
+#else /* KINETIS_USB0_IS_USBOTG */
+ SIM->SCGC4 |= SIM_SCGC4_USBFS;
+#endif /* KINETIS_USB0_IS_USBOTG */
+
+#if KINETIS_HAS_USB_CLOCK_RECOVERY
+ USB0->CLK_RECOVER_IRC_EN |= USBx_CLK_RECOVER_IRC_EN_IRC_EN;
+ USB0->CLK_RECOVER_CTRL |= USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN;
+#endif /* KINETIS_HAS_USB_CLOCK_RECOVERY */
+
+ /* Reset USB module, wait for completion */
+ USB0->USBTRC0 |= USBx_USBTRC0_USBRESET;
+ while ((USB0->USBTRC0 & USBx_USBTRC0_USBRESET));
+
+ /* Set BDT Address */
+ USB0->BDTPAGE1 = ((uint32_t)_bdt) >> 8;
+ USB0->BDTPAGE2 = ((uint32_t)_bdt) >> 16;
+ USB0->BDTPAGE3 = ((uint32_t)_bdt) >> 24;
+
+ /* Clear all ISR flags */
+ USB0->ISTAT = 0xFF;
+ USB0->ERRSTAT = 0xFF;
+#if KINETIS_USB0_IS_USBOTG
+ USB0->OTGISTAT = 0xFF;
+#endif /* KINETIS_USB0_IS_USBOTG */
+ USB0->USBTRC0 |= 0x40; //a hint was given that this is an undocumented interrupt bit
+
+ /* Enable USB */
+ USB0->CTL = USBx_CTL_ODDRST | USBx_CTL_USBENSOFEN;
+ USB0->USBCTRL = 0;
+
+ /* Enable reset interrupt */
+ USB0->INTEN |= USBx_INTEN_USBRSTEN;
+
+ /* Enable interrupt in NVIC */
+#if KINETIS_USB0_IS_USBOTG
+ nvicEnableVector(USB_OTG_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicEnableVector(USB_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief Deactivates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+ /* TODO: If in ready state then disables the USB clock.*/
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+#if KINETIS_USB0_IS_USBOTG
+ nvicDisableVector(USB_OTG_IRQn);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicDisableVector(USB_IRQn);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief USB low level reset routine.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+ // FIXME, dyn alloc
+ _usbbn = 0;
+
+#if KINETIS_USB_USE_USB0
+
+ /* Reset BDT ODD/EVEN bits */
+ USB0->CTL = USBx_CTL_ODDRST;
+
+ /* EP0 initialization.*/
+ usbp->epc[0] = &ep0config;
+ usb_lld_init_endpoint(usbp, 0);
+
+ /* Clear all pending interrupts */
+ USB0->ERRSTAT = 0xFF;
+ USB0->ISTAT = 0xFF;
+
+ /* Set the address to zero during enumeration */
+ usbp->address = 0;
+ USB0->ADDR = 0;
+
+ /* Enable other interrupts */
+ USB0->ERREN = 0xFF;
+ USB0->INTEN = USBx_INTEN_TOKDNEEN |
+ USBx_INTEN_SOFTOKEN |
+ USBx_INTEN_STALLEN |
+ USBx_INTEN_ERROREN |
+ USBx_INTEN_USBRSTEN |
+ USBx_INTEN_SLEEPEN;
+
+ /* "is this necessary?", Paul from PJRC */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Sets the USB address.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+
+#if KINETIS_USB_USE_USB0
+ USB0->ADDR = usbp->address&0x7F;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Enables an endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+
+ if(ep > KINETIS_USB_ENDPOINTS)
+ return;
+
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ uint8_t mask=0;
+
+ if(epc->out_state != NULL)
+ {
+ /* OUT Endpoint */
+ epc->out_state->odd_even = EVEN;
+ epc->out_state->data_bank = DATA0;
+ /* RXe */
+ _bdt[BDT_INDEX(ep, RX, EVEN)].desc = BDT_DESC(epc->out_maxsize, DATA0);
+ _bdt[BDT_INDEX(ep, RX, EVEN)].addr = usb_alloc(epc->out_maxsize);
+ /* RXo */
+ _bdt[BDT_INDEX(ep, RX, ODD)].desc = BDT_DESC(epc->out_maxsize, DATA1);
+ _bdt[BDT_INDEX(ep, RX, ODD)].addr = usb_alloc(epc->out_maxsize);
+ /* Enable OUT direction */
+ mask |= USBx_ENDPTn_EPRXEN;
+ }
+ if(epc->in_state != NULL)
+ {
+ /* IN Endpoint */
+ epc->in_state->odd_even = EVEN;
+ epc->in_state->data_bank = DATA0;
+ /* TXe, not used yet */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, EVEN)].addr = usb_alloc(epc->in_maxsize);
+ /* TXo, not used yet */
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].addr = usb_alloc(epc->in_maxsize);
+ /* Enable IN direction */
+ mask |= USBx_ENDPTn_EPTXEN;
+ }
+
+ /* EPHSHK should be set for CTRL, BULK, INTR not for ISOC*/
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_ISOC)
+ mask |= USBx_ENDPTn_EPHSHK;
+ /* Endpoint is not a CTRL endpoint, disable SETUP transfers */
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL)
+ mask |= USBx_ENDPTn_EPCTLDIS;
+
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V = mask;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+ (void)usbp;
+ uint8_t i;
+#if KINETIS_USB_USE_USB0
+ for(i=1;i<KINETIS_USB_ENDPOINTS;i++)
+ USB0->ENDPT[i].V = 0;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPRXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+#if KINETIS_USB_USE_USB0
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPTXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ * callback in order to read the received setup packet.
+ * @pre In order to use this function the endpoint must have been
+ * initialized as a control endpoint.
+ * @post The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+ /* Get the BDT entry */
+ USBOutEndpointState *os = usbp->epc[ep]->out_state;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even)];
+ /* Copy the 8 bytes of data */
+ uint8_t n;
+ for (n = 0; n < 8; n++) {
+ buf[n] = bd->addr[n];
+ }
+ /* Release the buffer
+ * Setup packet is always DATA0
+ * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ os->data_bank = DATA1;
+}
+
+/**
+ * @brief Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+ USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+ /* Transfer initialization.*/
+ if (osp->rxsize == 0) /* Special case for zero sized packets.*/
+ osp->rxpkts = 1;
+ else
+ osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
+ usbp->epc[ep]->out_maxsize);
+}
+
+/**
+ * @brief Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @note Called from ISR and locked zone.
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ (void)ep;
+ usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
+}
+
+/**
+ * @brief Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/usb_lld.h b/os/hal/ports/KINETIS/LLD/usb_lld.h new file mode 100644 index 0000000..978e8a6 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/usb_lld.h @@ -0,0 +1,428 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.h
+ * @brief KINETIS USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _USB_LLD_H_
+#define _USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum endpoint address.
+ */
+#define USB_MAX_ENDPOINTS 15
+
+/**
+ * @brief Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
+
+/**
+ * @brief Address ack handling
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
+
+/**
+ * @brief This device requires the address change after the status packet.
+ */
+#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief USB1 driver enable switch.
+ * @details If set to @p TRUE the support for USB1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_USB_USE_USB0) || defined(__DOXYGEN__)
+#define KINETIS_USB_USE_USB0 FALSE
+#endif
+
+/**
+ * @brief USB1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_USB_USB0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_USB_USB0_IRQ_PRIORITY 5
+#endif
+
+#if !defined(KINETIS_USB_ENDPOINTS) || defined(__DOXYGEN__)
+ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !KINETIS_HAS_USB
+#error "USB not present in the selected device"
+#endif
+
+#if !KINETIS_USB_USE_USB0
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if KINETIS_USB_USE_USB0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_USB_USB0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_USB_USB0_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_USB_IRQ_VECTOR)
+#error "KINETIS_USB_IRQ_VECTOR not defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an IN endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested transmit transfer size.
+ */
+ size_t txsize;
+ /**
+ * @brief Transmitted bytes so far.
+ */
+ size_t txcnt;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBInEndpointState;
+
+/**
+ * @brief Type of an OUT endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested receive transfer size.
+ */
+ size_t rxsize;
+ /**
+ * @brief Received bytes so far.
+ */
+ size_t rxcnt;
+ /**
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Number of packets to receive.
+ */
+ uint16_t rxpkts;
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBOutEndpointState;
+
+/**
+ * @brief Type of an USB endpoint configuration structure.
+ * @note Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+ /**
+ * @brief Type and mode of the endpoint.
+ */
+ uint32_t ep_mode;
+ /**
+ * @brief Setup packet notification callback.
+ * @details This callback is invoked when a setup packet has been
+ * received.
+ * @post The application must immediately call @p usbReadPacket() in
+ * order to access the received packet.
+ * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+ * endpoints, it should be set to @p NULL for other endpoint
+ * types.
+ */
+ usbepcallback_t setup_cb;
+ /**
+ * @brief IN endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t in_cb;
+ /**
+ * @brief OUT endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t out_cb;
+ /**
+ * @brief IN endpoint maximum packet size.
+ * @details This field must be set to zero if the IN endpoint is not used.
+ */
+ uint16_t in_maxsize;
+ /**
+ * @brief OUT endpoint maximum packet size.
+ * @details This field must be set to zero if the OUT endpoint is not used.
+ */
+ uint16_t out_maxsize;
+ /**
+ * @brief @p USBEndpointState associated to the IN endpoint.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
+ */
+ USBInEndpointState *in_state;
+ /**
+ * @brief @p USBEndpointState associated to the OUT endpoint.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
+ */
+ USBOutEndpointState *out_state;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Reserved field, not currently used.
+ * @note Initialize this field to 1 in order to be forward compatible.
+ */
+ uint16_t ep_buffers;
+ /**
+ * @brief Pointer to a buffer for setup packets.
+ * @details Setup packets require a dedicated 8-bytes buffer, set this
+ * field to @p NULL for non-control endpoints.
+ */
+ uint8_t *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief Type of an USB driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief USB events callback.
+ * @details This callback is invoked when an USB driver event is registered.
+ */
+ usbeventcb_t event_cb;
+ /**
+ * @brief Device GET_DESCRIPTOR request callback.
+ * @note This callback is mandatory and cannot be set to @p NULL.
+ */
+ usbgetdescriptor_t get_descriptor_cb;
+ /**
+ * @brief Requests hook callback.
+ * @details This hook allows to be notified of standard requests or to
+ * handle non standard requests.
+ */
+ usbreqhandler_t requests_hook_cb;
+ /**
+ * @brief Start Of Frame callback.
+ */
+ usbcallback_t sof_cb;
+ /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief Structure representing an USB driver.
+ */
+struct USBDriver {
+ /**
+ * @brief Driver state.
+ */
+ usbstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const USBConfig *config;
+ /**
+ * @brief Bit map of the transmitting IN endpoints.
+ */
+ uint16_t transmitting;
+ /**
+ * @brief Bit map of the receiving OUT endpoints.
+ */
+ uint16_t receiving;
+ /**
+ * @brief Active endpoints configurations.
+ */
+ const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an IN endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *in_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an OUT endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *out_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Endpoint 0 state.
+ */
+ usbep0state_t ep0state;
+ /**
+ * @brief Next position in the buffer to be transferred through endpoint 0.
+ */
+ uint8_t *ep0next;
+ /**
+ * @brief Number of bytes yet to be transferred through endpoint 0.
+ */
+ size_t ep0n;
+ /**
+ * @brief Endpoint 0 end transaction callback.
+ */
+ usbcallback_t ep0endcb;
+ /**
+ * @brief Setup packet buffer.
+ */
+ uint8_t setup[8];
+ /**
+ * @brief Current USB device status.
+ */
+ uint16_t status;
+ /**
+ * @brief Assigned USB address.
+ */
+ uint8_t address;
+ /**
+ * @brief Current USB device configuration.
+ */
+ uint8_t configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+ USB_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the next address in the packet memory.
+ */
+ uint32_t pmnext;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current frame number.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The current frame number.
+ *
+ * @notapi
+ */
+#define usb_lld_get_frame_number(usbp) ((USB0->FRMNUMH<<8)|USB0->FRMNUML)
+
+/**
+ * @brief Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ * @p usbStartReceiveI() because the last packet could have a size
+ * different from the expected one.
+ * @pre The OUT endpoint must have been configured in transaction mode
+ * in order to use this function.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep) \
+ ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief Connects the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_connect_bus)
+#define usb_lld_connect_bus(usbp) (USB0->CONTROL |= USBx_CONTROL_DPPULLUPNONOTG)
+#endif
+
+/**
+ * @brief Disconnect the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_disconnect_bus)
+/* Writing to USB0->CONTROL causes an unhandled exception when USB module is not clocked. */
+#if KINETIS_USB0_IS_USBOTG
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBOTG) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#else /* KINETIS_USB0_IS_USBOTG */
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBFS) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#endif /* KINETIS_USB0_IS_USBOTG */
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void usb_lld_init(void);
+ void usb_lld_start(USBDriver *usbp);
+ void usb_lld_stop(USBDriver *usbp);
+ void usb_lld_reset(USBDriver *usbp);
+ void usb_lld_set_address(USBDriver *usbp);
+ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+ void usb_lld_disable_endpoints(USBDriver *usbp);
+ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+ void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* _USB_LLD_H_ */
+
+/** @} */
|