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-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc.h38
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c5
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h5
-rw-r--r--os/hal/ports/TIVA/LLD/i2c_lld.c2
-rw-r--r--os/various/devices_lib/others/max7219.h14
-rw-r--r--os/various/memtest.cpp15
-rw-r--r--os/various/memtest.h (renamed from os/various/memtest.hpp)29
7 files changed, 73 insertions, 35 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
index 1377735..c21884c 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
@@ -196,19 +196,31 @@ typedef struct {
/**
* @brief BCR register
*/
-#define FSMC_BCR_MBKEN ((uint32_t)0x00000001)
-#define FSMC_BCR_MUXEN ((uint32_t)0x00000002)
-#define FSMC_BCR_MWID_0 ((uint32_t)0x00000010)
-#define FSMC_BCR_FACCEN ((uint32_t)0x00000040)
-#define FSMC_BCR_BURSTEN ((uint32_t)0x00000100)
-#define FSMC_BCR_WAITPOL ((uint32_t)0x00000200)
-#define FSMC_BCR_WRAPMOD ((uint32_t)0x00000400)
-#define FSMC_BCR_WAITCFG ((uint32_t)0x00000800)
-#define FSMC_BCR_WREN ((uint32_t)0x00001000)
-#define FSMC_BCR_WAITEN ((uint32_t)0x00002000)
-#define FSMC_BCR_EXTMOD ((uint32_t)0x00004000)
-#define FSMC_BCR_ASYNCWAIT ((uint32_t)0x00008000)
-#define FSMC_BCR_CBURSTRW ((uint32_t)0x00080000)
+#define FSMC_BCR_MBKEN ((uint32_t)1 << 0)
+#define FSMC_BCR_MUXEN ((uint32_t)1 << 1)
+#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2)
+#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2)
+#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2)
+#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2)
+#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4)
+#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx))
+#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
+#else
+#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
+#endif
+#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4)
+#define FSMC_BCR_FACCEN ((uint32_t)1 << 6)
+#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8)
+#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9)
+#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10)
+#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11)
+#define FSMC_BCR_WREN ((uint32_t)1 << 12)
+#define FSMC_BCR_WAITEN ((uint32_t)1 << 13)
+#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14)
+#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15)
+#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
/*===========================================================================*/
/* Driver pre-compile time settings. */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
index 22ec255..114f9bc 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
@@ -128,8 +128,9 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
"invalid state");
if (sramp->state == SRAM_STOP) {
- sramp->sram->BCR = FSMC_BCR_WREN | FSMC_BCR_MBKEN | FSMC_BCR_MWID_0;
- sramp->sram->BTR = cfgp->btr;
+ sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN;
+ sramp->sram->BTR = cfgp->btr;
+ sramp->sram->BWTR = cfgp->bwtr;
sramp->state = SRAM_READY;
}
}
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h
index a915d75..0abfd86 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h
@@ -109,9 +109,12 @@ typedef struct SRAMDriver SRAMDriver;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
+ * @note Some bits in BCR register will be forced by driver.
*/
typedef struct {
- uint32_t btr;
+ uint32_t bcr;
+ uint32_t btr;
+ uint32_t bwtr;
} SRAMConfig;
/**
diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.c b/os/hal/ports/TIVA/LLD/i2c_lld.c
index 4019a3b..f4c555b 100644
--- a/os/hal/ports/TIVA/LLD/i2c_lld.c
+++ b/os/hal/ports/TIVA/LLD/i2c_lld.c
@@ -216,7 +216,7 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
break;
}
case STATE_READ_NEXT: {
- if(i2cp->rxbytes == 0) {
+ if(i2cp->rxbytes == 2) {
i2cp->intstate = STATE_READ_FINAL;
}
*(i2cp->rxbuf) = dp->MDR;
diff --git a/os/various/devices_lib/others/max7219.h b/os/various/devices_lib/others/max7219.h
index f2bbbdf..e672be9 100644
--- a/os/various/devices_lib/others/max7219.h
+++ b/os/various/devices_lib/others/max7219.h
@@ -120,13 +120,13 @@ typedef enum {
typedef enum {
MAX7219_DM_No_decode = 0x00, /*!< No decode */
MAX7219_DM_CodeB_0 = 0x01, /*!< Code B on Digit 0 */
- MAX7219_DM_CodeB_1 = 0x02, /*!< Code B on Digit 1 */
- MAX7219_DM_CodeB_2 = 0x04, /*!< Code B on Digit 2 */
- MAX7219_DM_CodeB_3 = 0x08, /*!< Code B on Digit 3 */
- MAX7219_DM_CodeB_4 = 0x10, /*!< Code B on Digit 4 */
- MAX7219_DM_CodeB_5 = 0x20, /*!< Code B on Digit 5 */
- MAX7219_DM_CodeB_6 = 0x40, /*!< Code B on Digit 6 */
- MAX7219_DM_CodeB_7 = 0x80 /*!< Code B on Digit 7 */
+ MAX7219_DM_CodeB_1 = 0x03, /*!< Code B on Digits 0-1 */
+ MAX7219_DM_CodeB_2 = 0x07, /*!< Code B on Digits from 0 to 2 */
+ MAX7219_DM_CodeB_3 = 0x0F, /*!< Code B on Digits from 0 to 3 */
+ MAX7219_DM_CodeB_4 = 0x1F, /*!< Code B on Digits from 0 to 4 */
+ MAX7219_DM_CodeB_5 = 0x3F, /*!< Code B on Digits from 0 to 5 */
+ MAX7219_DM_CodeB_6 = 0x7F, /*!< Code B on Digits from 0 to 6 */
+ MAX7219_DM_CodeB_7 = 0xFF /*!< Code B on every digit */
} MAX7219_DM_t;
/**
diff --git a/os/various/memtest.cpp b/os/various/memtest.cpp
index 49828ec..b853fe7 100644
--- a/os/various/memtest.cpp
+++ b/os/various/memtest.cpp
@@ -18,7 +18,9 @@
#include <stddef.h>
#include <stdlib.h>
-#include "memtest.hpp"
+#include "memtest.h"
+
+static unsigned int prng_seed = 42;
/*
*
@@ -156,6 +158,8 @@ static void memtest_sequential(memtest_t *testp, Generator<T> &generator, T seed
const size_t steps = testp->size / sizeof(T);
size_t i;
T *mem = static_cast<T *>(testp->start);
+ T got;
+ T expect;
/* fill ram */
generator.init(seed);
@@ -165,8 +169,10 @@ static void memtest_sequential(memtest_t *testp, Generator<T> &generator, T seed
/* read back and compare */
generator.init(seed);
for (i=0; i<steps; i++) {
- if (mem[i] != generator.get()) {
- testp->ecb(testp, generator.get_type(), i*sizeof(T));
+ got = mem[i];
+ expect = generator.get();
+ if ((got != expect) && (nullptr != testp->errcb)) {
+ testp->errcb(testp, generator.get_type(), i, sizeof(T), got, expect);
return;
}
}
@@ -210,7 +216,8 @@ template <typename T>
static void moving_inversion_rand(memtest_t *testp) {
GeneratorMovingInvRand<T> generator;
T mask = -1;
- memtest_sequential<T>(testp, generator, testp->rand_seed & mask);
+ prng_seed++;
+ memtest_sequential<T>(testp, generator, prng_seed & mask);
}
/*
diff --git a/os/various/memtest.hpp b/os/various/memtest.h
index 200db1f..721b36b 100644
--- a/os/various/memtest.hpp
+++ b/os/various/memtest.h
@@ -14,8 +14,8 @@
limitations under the License.
*/
-#ifndef MEMTEST_HPP_
-#define MEMTEST_HPP_
+#ifndef MEMTEST_H_
+#define MEMTEST_H_
#define MEMTEST_WALKING_ONE (1 << 0)
#define MEMTEST_WALKING_ZERO (1 << 1)
@@ -37,7 +37,8 @@ typedef uint32_t testtype;
/*
* Error call back.
*/
-typedef void (*memtestecb_t)(memtest_t *testp, testtype type, size_t address);
+typedef void (*memtestecb_t)(memtest_t *testp, testtype type, size_t index,
+ size_t current_width, uint32_t got, uint32_t expect);
/*
*
@@ -45,18 +46,32 @@ typedef void (*memtestecb_t)(memtest_t *testp, testtype type, size_t address);
typedef enum {
MEMTEST_WIDTH_8,
MEMTEST_WIDTH_16,
- MEMTEST_WIDTH_32
+ MEMTEST_WIDTH_32,
} memtest_bus_width_t;
/*
*
*/
struct memtest_t {
+ /*
+ * Pointer to the test area start. Must be word aligned.
+ */
void *start;
+ /*
+ * Test area size in bytes.
+ */
size_t size;
+ /*
+ * Maximum width of transactions.
+ * Note: it implies all narrower tests.
+ * Note: width my be wider then your memory interface because AHB is
+ * smart enough to split big transactions to smaller ones.
+ */
memtest_bus_width_t width;
- memtestecb_t ecb;
- unsigned int rand_seed;
+ /*
+ * Error callback pointer. Set to NULL if unused.
+ */
+ memtestecb_t errcb;
};
/*
@@ -70,4 +85,4 @@ extern "C" {
}
#endif
-#endif /* MEMTEST_HPP_ */
+#endif /* MEMTEST_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 12:39:14 +0000