From 25d71d99823bdf9b27a4308063e4936c0a7a1d65 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 12:16:21 +0100
Subject: Added line support in Tiva pal driver.

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c |  30 +--
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 420 +++++++++++++++++--------------
 2 files changed, 250 insertions(+), 200 deletions(-)

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index 4df6665..09076c5 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -250,19 +250,19 @@
  */
 static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
 {
-  HWREG((port) + GPIO_O_DATA)  = config->data;
-  HWREG((port) + GPIO_O_DIR)   = config->dir;
-  HWREG((port) + GPIO_O_AFSEL) = config->afsel;
-  HWREG((port) + GPIO_O_DR2R)  = config->dr2r;
-  HWREG((port) + GPIO_O_DR4R)  = config->dr4r;
-  HWREG((port) + GPIO_O_DR8R)  = config->dr8r;
-  HWREG((port) + GPIO_O_ODR)   = config->odr;
-  HWREG((port) + GPIO_O_PUR)   = config->pur;
-  HWREG((port) + GPIO_O_PDR)   = config->pdr;
-  HWREG((port) + GPIO_O_SLR)   = config->slr;
-  HWREG((port) + GPIO_O_DEN)   = config->den;
-  HWREG((port) + GPIO_O_AMSEL) = config->amsel;
-  HWREG((port) + GPIO_O_PCTL)  = config->pctl;
+  HWREG(port + GPIO_O_DATA)  = config->data;
+  HWREG(port + GPIO_O_DIR)   = config->dir;
+  HWREG(port + GPIO_O_AFSEL) = config->afsel;
+  HWREG(port + GPIO_O_DR2R)  = config->dr2r;
+  HWREG(port + GPIO_O_DR4R)  = config->dr4r;
+  HWREG(port + GPIO_O_DR8R)  = config->dr8r;
+  HWREG(port + GPIO_O_ODR)   = config->odr;
+  HWREG(port + GPIO_O_PUR)   = config->pur;
+  HWREG(port + GPIO_O_PDR)   = config->pdr;
+  HWREG(port + GPIO_O_SLR)   = config->slr;
+  HWREG(port + GPIO_O_DEN)   = config->den;
+  HWREG(port + GPIO_O_AMSEL) = config->amsel;
+  HWREG(port + GPIO_O_PCTL)  = config->pctl;
 }
 
 /**
@@ -275,8 +275,8 @@ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
 static void gpio_unlock(ioportid_t port, ioportmask_t mask)
 {
 
-  HWREG((port) + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD;
-  HWREG((port) + GPIO_O_CR) = mask;
+  HWREG(port + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD;
+  HWREG(port + GPIO_O_CR) = mask;
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 4e7005b..60af102 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -28,7 +28,7 @@
 #if HAL_USE_PAL || defined(__DOXYGEN__)
 
 /*===========================================================================*/
-/* Driver constants.                                                         */
+/* Unsupported modes and specific modes                                      */
 /*===========================================================================*/
 
 #undef PAL_MODE_RESET
@@ -98,9 +98,7 @@
  */
 #define PAL_MODE_ALTERNATE(n)       (PAL_TIVA_AFSEL_ALTERNATE |               \
                                      PAL_TIVA_PCTL(n))
-/**
- * @}
- */
+/** @} */
 
 /**
  * @name    Standard I/O mode flags
@@ -157,98 +155,178 @@
                                          PAL_TIVA_DR2R_ENABLE |               \
                                          PAL_TIVA_ODR_OPENDRAIN |             \
                                          PAL_TIVA_DEN_ENABLE)
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants.                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Port related definitions
+ * @{
+ */
 /**
- * @}
+ * @brief   Width, in bits, of an I/O port.
  */
+#define PAL_IOPORTS_WIDTH 8
 
-/** @brief   GPIOA port identifier.*/
-#define IOPORT1         GPIOA
+/**
+ * @brief   Whole port mask.
+ * @brief   This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
+/** @} */
 
-/** @brief   GPIOB port identifier.*/
-#define IOPORT2         GPIOB
+/**
+ * @name    Line handling macros
+ * @{
+ */
+/**
+ * @brief   Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ *          of this type is platform-dependent.
+ * @note    In this driver the pad number is encoded in the lower 4 bits of
+ *          the GPIO address which are guaranteed to be zero.
+ */
+#define PAL_LINE(port, pad)                                                 \
+  ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
 
-/** @brief   GPIOC port identifier.*/
-#define IOPORT3         GPIOC
+/**
+ * @brief   Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line)                                                      \
+  ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
 
-/** @brief   GPIOD port identifier.*/
-#define IOPORT4         GPIOD
+/**
+ * @brief   Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line)                                                       \
+  ((uint32_t)((uint32_t)(line) & 0x0000000FU))
 
-/** @brief   GPIOE port identifier.*/
-#define IOPORT5         GPIOE
+/**
+ * @brief   Value identifying an invalid line.
+ */
+#define PAL_NOLINE                      0U
+/** @} */
 
-/** @brief   GPIOF port identifier.*/
-#define IOPORT6         GPIOF
+/**
+ * @brief   GPIO port setup info.
+ */
+typedef struct
+{
+  /** @brief Initial value for DATA register.*/
+  uint32_t data;
+  /** @brief Initial value for DIR register.*/
+  uint32_t dir;
+  /** @brief Initial value for AFSEL register.*/
+  uint32_t afsel;
+  /** @brief Initial value for DR2R register.*/
+  uint32_t dr2r;
+  /** @brief Initial value for DR4R register.*/
+  uint32_t dr4r;
+  /** @brief Initial value for DR8R register.*/
+  uint32_t dr8r;
+  /** @brief Initial value for ODR register.*/
+  uint32_t odr;
+  /** @brief Initial value for PUR register.*/
+  uint32_t pur;
+  /** @brief Initial value for PDR register.*/
+  uint32_t pdr;
+  /** @brief Initial value for SLR register.*/
+  uint32_t slr;
+  /** @brief Initial value for DEN register.*/
+  uint32_t den;
+  /** @brief Initial value for AMSEL register.*/
+  uint32_t amsel;
+  /** @brief Initial value for PCTL register.*/
+  uint32_t pctl;
+} tiva_gpio_setup_t;
 
+/**
+ * @brief   Tiva GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ *          system startup time in order to initialized the digital I/O
+ *          subsystem. This represents only the initial setup, specific pads
+ *          or whole ports can be reprogrammed at later time.
+ */
+typedef struct
+{
+  /** @brief GPIO port A setup data.*/
+  tiva_gpio_setup_t     PAData;
+  /** @brief GPIO port B setup data.*/
+  tiva_gpio_setup_t     PBData;
+  /** @brief GPIO port C setup data.*/
+  tiva_gpio_setup_t     PCData;
+  /** @brief GPIO port D setup data.*/
+  tiva_gpio_setup_t     PDData;
+  /** @brief GPIO port E setup data.*/
+  tiva_gpio_setup_t     PEData;
+  /** @brief GPIO port F setup data.*/
+  tiva_gpio_setup_t     PFData;
 #if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-/** @brief Port G setup data.*/
-#define IOPORT7         GPIOG
-#endif /* TIVA_HAS_GPIOG.*/
-
+  /** @brief GPIO port G setup data.*/
+  tiva_gpio_setup_t     PGData;
+#endif
 #if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-/** @brief Port H setup data.*/
-#define IOPORT8         GPIOH
-#endif /* TIVA_HAS_GPIOH.*/
-
+  /** @brief GPIO port H setup data.*/
+  tiva_gpio_setup_t     PHData;
+#endif
 #if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-/** @brief Port J setup data.*/
-#define IOPORT9         GPIOJ
-#endif /* TIVA_HAS_GPIOJ.*/
-
+  /** @brief GPIO port J setup data.*/
+  tiva_gpio_setup_t     PJData;
+#endif
 #if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-/** @brief Port K setup data.*/
-#define IOPORT10        GPIOK
-#endif /* TIVA_HAS_GPIOK.*/
-
+  /** @brief GPIO port K setup data.*/
+  tiva_gpio_setup_t     PKData;
+#endif
 #if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-/** @brief Port L setup data.*/
-#define IOPORT11        GPIOL
-#endif /* TIVA_HAS_GPIOL.*/
-
+  /** @brief GPIO port L setup data.*/
+  tiva_gpio_setup_t     PLData;
+#endif
 #if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-/** @brief Port M setup data.*/
-#define IOPORT12        GPIOM
-#endif /* TIVA_HAS_GPIOM.*/
-
+  /** @brief GPIO port M setup data.*/
+  tiva_gpio_setup_t     PMData;
+#endif
 #if TIVA_HAS_GPION || defined(__DOXYGEN__)
-/** @brief Port N setup data.*/
-#define IOPORT13        GPION
-#endif /* TIVA_HAS_GPION.*/
-
+  /** @brief GPIO port N setup data.*/
+  tiva_gpio_setup_t     PNData;
+#endif
 #if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-/** @brief Port P setup data.*/
-#define IOPORT14        GPIOP
-#endif /* TIVA_HAS_GPIOP.*/
-
+  /** @brief GPIO port P setup data.*/
+  tiva_gpio_setup_t     PPData;
+#endif
 #if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-/** @brief Port Q setup data.*/
-#define IOPORT15        GPIOQ
-#endif /* TIVA_HAS_GPIOQ.*/
-
+  /** @brief GPIO port Q setup data.*/
+  tiva_gpio_setup_t     PQData;
+#endif
 #if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-/** @brief Port R setup data.*/
-#define IOPORT16        GPIOR
-#endif /* TIVA_HAS_GPIOR.*/
-
+  /** @brief GPIO port R setup data.*/
+  tiva_gpio_setup_t     PRData;
+#endif
 #if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-/** @brief Port S setup data.*/
-#define IOPORT17        GPIOS
-#endif /* TIVA_HAS_GPIOS.*/
-
+  /** @brief GPIO port S setup data.*/
+  tiva_gpio_setup_t     PSData;
+#endif
 #if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-/** @brief Port T setup data.*/
-#define IOPORT18        GPIOT
-#endif /* TIVA_HAS_GPIOT.*/
+  /** @brief GPIO port T setup data.*/
+  tiva_gpio_setup_t     PTData;
+#endif
+} PALConfig;
 
 /**
- * @brief   Width, in bits, of an I/O port.
+ * @brief   Digital I/O port sized unsigned type.
  */
-#define PAL_IOPORTS_WIDTH 8
+typedef uint32_t ioportmask_t;
 
 /**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
+ * @brief   Digital I/O modes.
  */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
+typedef uint32_t iomode_t;
+
+/**
+ * @brief   Port Identifier.
+ */
+typedef uint32_t ioportid_t;
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -260,7 +338,6 @@
  * @brief   GPIOA AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
  *          to @p FALSE the APB bus is used to access GPIOA.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOA_USE_AHB             TRUE
@@ -270,7 +347,6 @@
  * @brief   GPIOB AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
  *          to @p FALSE the APB bus is used to access GPIOB.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOB_USE_AHB             TRUE
@@ -280,7 +356,6 @@
  * @brief   GPIOC AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
  *          to @p FALSE the APB bus is used to access GPIOC.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOC_USE_AHB             TRUE
@@ -290,7 +365,6 @@
  * @brief   GPIOD AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
  *          to @p FALSE the APB bus is used to access GPIOD.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOD_USE_AHB             TRUE
@@ -300,7 +374,6 @@
  * @brief   GPIOE AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
  *          to @p FALSE the APB bus is used to access GPIOE.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOE_USE_AHB             TRUE
@@ -310,7 +383,6 @@
  * @brief   GPIOF AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
  *          to @p FALSE the APB bus is used to access GPIOF.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOF_USE_AHB             TRUE
@@ -320,7 +392,6 @@
  * @brief   GPIOG AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
  *          to @p FALSE the APB bus is used to access GPIOG.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOG_USE_AHB             TRUE
@@ -330,7 +401,6 @@
  * @brief   GPIOH AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
  *          to @p FALSE the APB bus is used to access GPIOH.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOH_USE_AHB             TRUE
@@ -340,7 +410,6 @@
  * @brief   GPIOJ AHB enable switch.
  * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
  *          to @p FALSE the APB bus is used to access GPIOJ.
- * @note    The default is TRUE.
  */
 #if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
 #define TIVA_GPIO_GPIOJ_USE_AHB             TRUE
@@ -352,8 +421,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-//#if defined(TM4C123x)
-
 #if TIVA_GPIO_GPIOA_USE_AHB
 #define GPIOA                               GPIO_PORTA_AHB_BASE
 #else
@@ -414,146 +481,131 @@
 #define GPION                               GPIO_PORTN_BASE
 #define GPIOP                               GPIO_PORTP_BASE
 #define GPIOQ                               GPIO_PORTQ_BASE
-
-//#endif
+#define GPIOR                               GPIO_PORTR_BASE
+#define GPIOS                               GPIO_PORTS_BASE
+#define GPIOT                               GPIO_PORTT_BASE
 
 /*===========================================================================*/
-/* Driver data structures and types.                                         */
+/* I/O Ports Identifiers.                                                    */
 /*===========================================================================*/
 
 /**
- * @brief   GPIO port setup info.
+ * @brief   GPIO port A identifier.
  */
-typedef struct 
-{
-  /** @brief Initial value for DATA register.*/
-  uint32_t data;
-  /** @brief Initial value for DIR register.*/
-  uint32_t dir;
-  /** @brief Initial value for AFSEL register.*/
-  uint32_t afsel;
-  /** @brief Initial value for DR2R register.*/
-  uint32_t dr2r;
-  /** @brief Initial value for DR4R register.*/
-  uint32_t dr4r;
-  /** @brief Initial value for DR8R register.*/
-  uint32_t dr8r;
-  /** @brief Initial value for ODR register.*/
-  uint32_t odr;
-  /** @brief Initial value for PUR register.*/
-  uint32_t pur;
-  /** @brief Initial value for PDR register.*/
-  uint32_t pdr;
-  /** @brief Initial value for SLR register.*/
-  uint32_t slr;
-  /** @brief Initial value for DEN register.*/
-  uint32_t den;
-  /** @brief Initial value for AMSEL register.*/
-  uint32_t amsel;
-  /** @brief Initial value for PCTL register.*/
-  uint32_t pctl;
-} tiva_gpio_setup_t;
+#define IOPORT1         GPIOA
 
 /**
- * @brief   Tiva GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
+ * @brief   GPIO port B identifier.
  */
-typedef struct
-{
-  /** @brief Port A setup data.*/
-  tiva_gpio_setup_t     PAData;
-  /** @brief Port B setup data.*/
-  tiva_gpio_setup_t     PBData;
-  /** @brief Port C setup data.*/
-  tiva_gpio_setup_t     PCData;
-  /** @brief Port D setup data.*/
-  tiva_gpio_setup_t     PDData;
-  /** @brief Port E setup data.*/
-  tiva_gpio_setup_t     PEData;
-  /** @brief Port F setup data.*/
-  tiva_gpio_setup_t     PFData;
+#define IOPORT2         GPIOB
+
+/**
+ * @brief   GPIO port C identifier.
+ */
+#define IOPORT3         GPIOC
 
+/**
+ * @brief   GPIO port D identifier.
+ */
+#define IOPORT4         GPIOD
+
+/**
+ * @brief   GPIO port E identifier.
+ */
+#define IOPORT5         GPIOE
+
+/**
+ * @brief   GPIO port F identifier.
+ */
+#define IOPORT6         GPIOF
+
+/**
+ * @brief   GPIO port G identifier.
+ */
 #if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-  /** @brief Port G setup data.*/
-  tiva_gpio_setup_t     PGData;
-#endif /* TIVA_HAS_GPIOG.*/
+#define IOPORT7         GPIOG
+#endif
 
+/**
+ * @brief   GPIO port H identifier.
+ */
 #if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-  /** @brief Port H setup data.*/
-  tiva_gpio_setup_t     PHData;
-#endif /* TIVA_HAS_GPIOH.*/
+#define IOPORT8         GPIOH
+#endif
 
+/**
+ * @brief   GPIO port J identifier.
+ */
 #if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-  /** @brief Port J setup data.*/
-  tiva_gpio_setup_t     PJData;
-#endif /* TIVA_HAS_GPIOJ.*/
+#define IOPORT9         GPIOJ
+#endif
 
+/**
+ * @brief   GPIO port K identifier.
+ */
 #if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-  /** @brief Port K setup data.*/
-  tiva_gpio_setup_t     PKData;
-#endif /* TIVA_HAS_GPIOK.*/
+#define IOPORT10        GPIOK
+#endif
 
+/**
+ * @brief   GPIO port L identifier.
+ */
 #if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-  /** @brief Port L setup data.*/
-  tiva_gpio_setup_t     PLData;
-#endif /* TIVA_HAS_GPIOL.*/
+#define IOPORT11        GPIOL
+#endif
 
+/**
+ * @brief   GPIO port M identifier.
+ */
 #if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-  /** @brief Port M setup data.*/
-  tiva_gpio_setup_t     PMData;
-#endif /* TIVA_HAS_GPIOM.*/
+#define IOPORT12        GPIOM
+#endif
 
+/**
+ * @brief   GPIO port N identifier.
+ */
 #if TIVA_HAS_GPION || defined(__DOXYGEN__)
-  /** @brief Port N setup data.*/
-  tiva_gpio_setup_t     PNData;
-#endif /* TIVA_HAS_GPION.*/
+#define IOPORT13        GPION
+#endif
 
+/**
+ * @brief   GPIO port P identifier.
+ */
 #if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-  /** @brief Port P setup data.*/
-  tiva_gpio_setup_t     PPData;
-#endif /* TIVA_HAS_GPIOP.*/
+#define IOPORT14        GPIOP
+#endif
 
+/**
+ * @brief   GPIO port Q identifier.
+ */
 #if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-  /** @brief Port Q setup data.*/
-  tiva_gpio_setup_t     PQData;
-#endif /* TIVA_HAS_GPIOQ.*/
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-  /** @brief Port R setup data.*/
-  tiva_gpio_setup_t     PRData;
-#endif /* TIVA_HAS_GPIOR.*/
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-  /** @brief Port S setup data.*/
-  tiva_gpio_setup_t     PSData;
-#endif /* TIVA_HAS_GPIOS.*/
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-  /** @brief Port T setup data.*/
-  tiva_gpio_setup_t     PTData;
-#endif /* TIVA_HAS_GPIOT.*/
-} PALConfig;
+#define IOPORT15        GPIOQ
+#endif
 
 /**
- * @brief   Digital I/O port sized unsigned type.
+ * @brief   GPIO port R identifier.
  */
-typedef uint32_t ioportmask_t;
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+#define IOPORT16        GPIOR
+#endif
 
 /**
- * @brief   Digital I/O modes.
+ * @brief   GPIO port S identifier.
  */
-typedef uint32_t iomode_t;
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+#define IOPORT17        GPIOS
+#endif
 
 /**
- * @brief   Port Identifier.
+ * @brief   GPIO port T identifier.
  */
-typedef uint32_t ioportid_t;
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+#define IOPORT18        GPIOT
+#endif
 
 /*===========================================================================*/
-/* Driver macros.                                                            */
+/* Implementation, some of the following macros could be implemented as      */
+/* functions, if so please put them in pal_lld.c.                            */
 /*===========================================================================*/
 
 /**
@@ -757,6 +809,4 @@ extern "C" {
 
 #endif /* HAL_PAL_LLD_H */
 
-/**
- * @}
- */
+/** @} */
-- 
cgit v1.2.3


From 568ed8d0ee46b3ada7bdf13cbb6b1a94f185d788 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 12:27:54 +0100
Subject: Some improvements.

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c | 29 +++++++++++++----------------
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 18 +++++++++---------
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index 09076c5..9adbf11 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -223,9 +223,6 @@
                          GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT |      \
                          GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
 
-/* GPIO lock password.*/
-#define TIVA_GPIO_LOCK_PWD                  0x4C4F434B
-
 #define GPIOC_JTAG_MASK     (0x0F)
 #define GPIOD_NMI_MASK      (0x80)
 #define GPIOF_NMI_MASK      (0x01)
@@ -275,7 +272,7 @@ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
 static void gpio_unlock(ioportid_t port, ioportmask_t mask)
 {
 
-  HWREG(port + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD;
+  HWREG(port + GPIO_O_LOCK) = GPIO_LOCK_KEY;
   HWREG(port + GPIO_O_CR) = mask;
 }
 
@@ -403,18 +400,18 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
     uint32_t bit_mask = (1 << bit);
 
     if ((mask & 1) != 0) {
-      HWREG((port) + GPIO_O_DIR)   = (HWREG((port) + GPIO_O_DIR)   & ~bit_mask)  | dir;
-      HWREG((port) + GPIO_O_AFSEL) = (HWREG((port) + GPIO_O_AFSEL) & ~bit_mask)  | afsel;
-      HWREG((port) + GPIO_O_DR2R)  = (HWREG((port) + GPIO_O_DR2R)  & ~bit_mask)  | dr2r;
-      HWREG((port) + GPIO_O_DR4R)  = (HWREG((port) + GPIO_O_DR4R)  & ~bit_mask)  | dr4r;
-      HWREG((port) + GPIO_O_DR8R)  = (HWREG((port) + GPIO_O_DR8R)  & ~bit_mask)  | dr8r;
-      HWREG((port) + GPIO_O_ODR)   = (HWREG((port) + GPIO_O_ODR)   & ~bit_mask)  | odr;
-      HWREG((port) + GPIO_O_PUR)   = (HWREG((port) + GPIO_O_PUR)   & ~bit_mask)  | pur;
-      HWREG((port) + GPIO_O_PDR)   = (HWREG((port) + GPIO_O_PDR)   & ~bit_mask)  | pdr;
-      HWREG((port) + GPIO_O_SLR)   = (HWREG((port) + GPIO_O_SLR)   & ~bit_mask)  | slr;
-      HWREG((port) + GPIO_O_DEN)   = (HWREG((port) + GPIO_O_DEN)   & ~bit_mask)  | den;
-      HWREG((port) + GPIO_O_AMSEL) = (HWREG((port) + GPIO_O_AMSEL) & ~bit_mask)  | amsel;
-      HWREG((port) + GPIO_O_PCTL)  = (HWREG((port) + GPIO_O_PCTL)  & ~pctl_mask) | pctl;
+      HWREG(port + GPIO_O_DIR)   = (HWREG(port + GPIO_O_DIR)   & ~bit_mask)  | dir;
+      HWREG(port + GPIO_O_AFSEL) = (HWREG(port + GPIO_O_AFSEL) & ~bit_mask)  | afsel;
+      HWREG(port + GPIO_O_DR2R)  = (HWREG(port + GPIO_O_DR2R)  & ~bit_mask)  | dr2r;
+      HWREG(port + GPIO_O_DR4R)  = (HWREG(port + GPIO_O_DR4R)  & ~bit_mask)  | dr4r;
+      HWREG(port + GPIO_O_DR8R)  = (HWREG(port + GPIO_O_DR8R)  & ~bit_mask)  | dr8r;
+      HWREG(port + GPIO_O_ODR)   = (HWREG(port + GPIO_O_ODR)   & ~bit_mask)  | odr;
+      HWREG(port + GPIO_O_PUR)   = (HWREG(port + GPIO_O_PUR)   & ~bit_mask)  | pur;
+      HWREG(port + GPIO_O_PDR)   = (HWREG(port + GPIO_O_PDR)   & ~bit_mask)  | pdr;
+      HWREG(port + GPIO_O_SLR)   = (HWREG(port + GPIO_O_SLR)   & ~bit_mask)  | slr;
+      HWREG(port + GPIO_O_DEN)   = (HWREG(port + GPIO_O_DEN)   & ~bit_mask)  | den;
+      HWREG(port + GPIO_O_AMSEL) = (HWREG(port + GPIO_O_AMSEL) & ~bit_mask)  | amsel;
+      HWREG(port + GPIO_O_PCTL)  = (HWREG(port + GPIO_O_PCTL)  & ~pctl_mask) | pctl;
     }
 
     mask >>= 1;
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 60af102..8f7a1f6 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -421,55 +421,55 @@ typedef uint32_t ioportid_t;
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if TIVA_GPIO_GPIOA_USE_AHB
+#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
 #define GPIOA                               GPIO_PORTA_AHB_BASE
 #else
 #define GPIOA                               GPIO_PORTA_BASE
 #endif
 
-#if TIVA_GPIO_GPIOB_USE_AHB
+#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
 #define GPIOB                               GPIO_PORTB_AHB_BASE
 #else
 #define GPIOB                               GPIO_PORTB_BASE
 #endif
 
-#if TIVA_GPIO_GPIOC_USE_AHB
+#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
 #define GPIOC                               GPIO_PORTC_AHB_BASE
 #else
 #define GPIOC                               GPIO_PORTC_BASE
 #endif
 
-#if TIVA_GPIO_GPIOD_USE_AHB
+#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
 #define GPIOD                               GPIO_PORTD_AHB_BASE
 #else
 #define GPIOD                               GPIO_PORTD_BASE
 #endif
 
-#if TIVA_GPIO_GPIOE_USE_AHB
+#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
 #define GPIOE                               GPIO_PORTE_AHB_BASE
 #else
 #define GPIOE                               GPIO_PORTE_BASE
 #endif
 
-#if TIVA_GPIO_GPIOF_USE_AHB
+#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
 #define GPIOF                               GPIO_PORTF_AHB_BASE
 #else
 #define GPIOF                               GPIO_PORTF_BASE
 #endif
 
-#if TIVA_GPIO_GPIOG_USE_AHB
+#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
 #define GPIOG                               GPIO_PORTG_AHB_BASE
 #else
 #define GPIOG                               GPIO_PORTG_BASE
 #endif
 
-#if TIVA_GPIO_GPIOH_USE_AHB
+#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
 #define GPIOH                               GPIO_PORTH_AHB_BASE
 #else
 #define GPIOH                               GPIO_PORTH_BASE
 #endif
 
-#if TIVA_GPIO_GPIOJ_USE_AHB
+#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
 #define GPIOJ                               GPIO_PORTJ_AHB_BASE
 #else
 #define GPIOJ                               GPIO_PORTJ_BASE
-- 
cgit v1.2.3


From 548c3592db460bad5803232b36f22e967fc61c2b Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 14:13:31 +0100
Subject: Fixed errors introduced by line feature.

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 8f7a1f6..a2d84ac 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -195,7 +195,7 @@
  * @brief   Decodes a port identifier from a line identifier.
  */
 #define PAL_PORT(line)                                                      \
-  ((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
+  ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFFF0U))
 
 /**
  * @brief   Decodes a pad identifier from a line identifier.
@@ -323,6 +323,11 @@ typedef uint32_t ioportmask_t;
  */
 typedef uint32_t iomode_t;
 
+/**
+ * @brief   Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
 /**
  * @brief   Port Identifier.
  */
-- 
cgit v1.2.3


From d10aa9e7a136e41377f40a774fdf3bffb59b358b Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 14:33:58 +0100
Subject: Defined lines in board files.

---
 os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 18 ++++++++++++++++++
 os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 14 ++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
index a59235a..c337e21 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
@@ -94,6 +94,24 @@
 #define GPIOF_PIN6              6
 #define GPIOF_PIN7              7
 
+/*
+ * IO lines assignments.
+ */
+#define LINE_UART0_RX           PAL_LINE(GPIOA, 0U)
+#define LINE_UART0_TX           PAL_LINE(GPIOA, 1U)
+#define LINE_SSI0_CLK           PAL_LINE(GPIOA, 2U)
+#define LINE_SSI0_RX            PAL_LINE(GPIOA, 4U)
+#define LINE_SSI0_TX            PAL_LINE(GPIOA, 5U)
+
+#define LINE_I2C0_SCL           PAL_LINE(GPIOB, 2U)
+#define LINE_I2C0_SDA           PAL_LINE(GPIOB, 3U)
+
+#define LINE_SW2                PAL_LINE(GPIOF, 0U)
+#define LINE_LED_RED            PAL_LINE(GPIOF, 1U)
+#define LINE_LED_BLUE           PAL_LINE(GPIOF, 2U)
+#define LINE_LED_GREEN          PAL_LINE(GPIOF, 3U)
+#define LINE_SW1                PAL_LINE(GPIOF, 4U)
+
 /*
  * I/O ports initial setup, this configuration is established soon after reset
  * in the initialization code.
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
index 9012f7c..982fb1b 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
@@ -183,6 +183,20 @@
 #define GPIOQ_PIN6              6
 #define GPIOQ_PIN7              7
 
+/*
+ * IO lines assignments.
+ */
+#define LINE_UART0_RX           PAL_LINE(GPIOA, 0U)
+#define LINE_UART0_TX           PAL_LINE(GPIOA, 1U)
+
+#define LINE_LED0               PAL_LINE(GPIOF, 0U)
+#define LINE_LED1               PAL_LINE(GPIOF, 4U)
+
+#define LINE_LED2               PAL_LINE(GPION, 0U)
+#define LINE_LED3               PAL_LINE(GPION, 1U)
+
+#define LINE_SW1                PAL_LINE(GPIOJ, 0U)
+
 /*
  * I/O ports initial setup, this configuration is established soon after reset
  * in the initialization code.
-- 
cgit v1.2.3


From 4435bdec242f1518ee0b4fcf93d8eec4341697e3 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 14:34:58 +0100
Subject: Replaced port+pad by line in the demos and testhal.

---
 demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c | 43 +++++++++++++++++--------------
 demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c | 45 +++++++++++++++++++--------------
 testhal/TIVA/TM4C123x/EXT/main.c        | 12 ++++-----
 testhal/TIVA/TM4C123x/GPT/main.c        |  6 ++---
 testhal/TIVA/TM4C123x/I2C/main.c        |  8 +++---
 testhal/TIVA/TM4C123x/PWM/main.c        | 18 ++++++-------
 testhal/TIVA/TM4C123x/SPI/main.c        | 28 ++++++++++----------
 testhal/TIVA/TM4C123x/WDG/main.c        | 15 +++++------
 8 files changed, 94 insertions(+), 81 deletions(-)

diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
index 6723c62..6522049 100644
--- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
+++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
@@ -20,9 +20,8 @@
 
 typedef struct led_config
 {
-  ioportid_t port;
+  ioportid_t line;
   uint32_t sleep;
-  uint8_t  pin;
 } led_config_t;
 
 /*
@@ -36,11 +35,11 @@ static THD_FUNCTION(blinkLed, arg) {
 
   chRegSetThreadName("Blinker");
 
-  palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(ledConfig->line, PAL_MODE_OUTPUT_PUSHPULL);
 
   while (TRUE) {
     chThdSleepMilliseconds(ledConfig->sleep);
-    palTogglePad(ledConfig->port, ledConfig->pin);
+    palToggleLine(ledConfig->line);
   }
 }
 
@@ -62,37 +61,43 @@ int main(void)
   chSysInit();
 
   /* Configure RX and TX pins for UART0.*/
-  palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
-  palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
 
   /* Start the serial driver with the default configuration.*/
   sdStart(&SD1, NULL);
 
-  if (!palReadPad(GPIOF, GPIOF_SW2)) {
+  if (!palReadLine(LINE_SW2)) {
     test_execute((BaseSequentialStream *)&SD1);
   }
 
-  ledRed.port    = GPIOF;
-  ledRed.pin     = GPIOF_LED_RED;
+  ledRed.line    = LINE_LED_RED;
   ledRed.sleep   = 100;
 
-  ledGreen.port  = GPIOF;
-  ledGreen.pin   = GPIOF_LED_GREEN;
+  ledGreen.line  = LINE_LED_GREEN;
   ledGreen.sleep = 101;
 
-  ledBlue.port   = GPIOF;
-  ledBlue.pin    = GPIOF_LED_BLUE;
+  ledBlue.line   = LINE_LED_BLUE;
   ledBlue.sleep  = 102;
 
   /* Creating the blinker threads.*/
-  chThdCreateStatic(waBlinkLedRed, sizeof(waBlinkLedRed), NORMALPRIO, blinkLed,
+  chThdCreateStatic(waBlinkLedRed,
+                    sizeof(waBlinkLedRed),
+                    NORMALPRIO,
+                    blinkLed,
                     &ledRed);
 
-  chThdCreateStatic(waBlinkLedGreen, sizeof(waBlinkLedGreen), NORMALPRIO,
-                    blinkLed, &ledGreen);
-
-  chThdCreateStatic(waBlinkLedBlue, sizeof(waBlinkLedBlue), NORMALPRIO,
-                    blinkLed, &ledBlue);
+  chThdCreateStatic(waBlinkLedGreen,
+                    sizeof(waBlinkLedGreen),
+                    NORMALPRIO,
+                    blinkLed,
+                    &ledGreen);
+
+  chThdCreateStatic(waBlinkLedBlue,
+                    sizeof(waBlinkLedBlue),
+                    NORMALPRIO,
+                    blinkLed,
+                    &ledBlue);
 
   /* Normal main() thread activity.*/
   while (TRUE) {
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
index 5184e3e..968a8e5 100644
--- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
@@ -20,9 +20,8 @@
 
 typedef struct led_config
 {
-  ioportid_t port;
+  ioportid_t line;
   uint32_t sleep;
-  uint8_t  pin;
 } led_config_t;
 
 /*
@@ -38,11 +37,11 @@ static THD_FUNCTION(blinkLed, arg) {
   chRegSetThreadName("Blinker");
 
   /* Configure pin as push-pull output.*/
-  palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(ledConfig->line, PAL_MODE_OUTPUT_PUSHPULL);
 
   while (TRUE) {
     chThdSleepMilliseconds(ledConfig->sleep);
-    palTogglePad(ledConfig->port, ledConfig->pin);
+    palToggleLine(ledConfig->line);
   }
 }
 
@@ -64,43 +63,51 @@ int main(void)
   chSysInit();
 
   /* Configure RX and TX pins for UART0.*/
-  palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
-  palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
 
   /* Start the serial driver with the default configuration.*/
   sdStart(&SD1, NULL);
 
-  if (!palReadPad(GPIOJ, GPIOJ_SW1)) {
+  if (!palReadLine(LINE_SW1)) {
     test_execute((BaseSequentialStream *)&SD1);
   }
 
-  led1.port  = GPIOF;
-  led1.pin   = GPIOF_LED0;
+  led1.line  = LINE_LED0;
   led1.sleep = 100;
 
-  led2.port  = GPIOF;
-  led2.pin   = GPIOF_LED1;
+  led2.line  = LINE_LED1;
   led2.sleep = 101;
 
-  led3.port  = GPION;
-  led3.pin   = GPION_LED2;
+  led3.line  = LINE_LED2;
   led3.sleep = 102;
 
-  led4.port  = GPION;
-  led4.pin   = GPION_LED3;
+  led4.line  = LINE_LED3;
   led4.sleep = 103;
 
   /* Creating the blinker threads.*/
-  chThdCreateStatic(waBlinkLed1, sizeof(waBlinkLed1), NORMALPRIO, blinkLed,
+  chThdCreateStatic(waBlinkLed1,
+                    sizeof(waBlinkLed1),
+                    NORMALPRIO,
+                    blinkLed,
                     &led1);
 
-  chThdCreateStatic(waBlinkLed2, sizeof(waBlinkLed2), NORMALPRIO, blinkLed,
+  chThdCreateStatic(waBlinkLed2,
+                    sizeof(waBlinkLed2),
+                    NORMALPRIO,
+                    blinkLed,
                     &led2);
 
-  chThdCreateStatic(waBlinkLed3, sizeof(waBlinkLed3), NORMALPRIO, blinkLed,
+  chThdCreateStatic(waBlinkLed3,
+                    sizeof(waBlinkLed3),
+                    NORMALPRIO,
+                    blinkLed,
                     &led3);
 
-  chThdCreateStatic(waBlinkLed4, sizeof(waBlinkLed4), NORMALPRIO, blinkLed,
+  chThdCreateStatic(waBlinkLed4,
+                    sizeof(waBlinkLed4),
+                    NORMALPRIO,
+                    blinkLed,
                     &led4);
 
   /*
diff --git a/testhal/TIVA/TM4C123x/EXT/main.c b/testhal/TIVA/TM4C123x/EXT/main.c
index 4370794..6da2ef9 100644
--- a/testhal/TIVA/TM4C123x/EXT/main.c
+++ b/testhal/TIVA/TM4C123x/EXT/main.c
@@ -22,7 +22,7 @@ static void extcb1(EXTDriver *extp, expchannel_t channel)
   (void)extp;
   (void)channel;
 
-  palTogglePad(GPIOF, GPIOF_LED_RED);
+  palToggleLine(LINE_LED_RED);
 }
 
 static void extcb2(EXTDriver *extp, expchannel_t channel)
@@ -30,7 +30,7 @@ static void extcb2(EXTDriver *extp, expchannel_t channel)
   (void)extp;
   (void)channel;
 
-  palTogglePad(GPIOF, GPIOF_LED_GREEN);
+  palToggleLine(LINE_LED_GREEN);
 }
 
 static const EXTConfig extcfg =
@@ -108,10 +108,10 @@ int main(void)
   halInit();
   chSysInit();
 
-  palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
-  palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
-  palSetPadMode(GPIOF, GPIOF_SW1, PAL_MODE_INPUT_PULLUP);
-  palSetPadMode(GPIOF, GPIOF_SW2, PAL_MODE_INPUT_PULLUP);
+  palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_SW1, PAL_MODE_INPUT_PULLUP);
+  palSetLineMode(LINE_SW2, PAL_MODE_INPUT_PULLUP);
 
   extStart(&EXTD1, &extcfg);
 
diff --git a/testhal/TIVA/TM4C123x/GPT/main.c b/testhal/TIVA/TM4C123x/GPT/main.c
index 4e19b14..f92b13b 100644
--- a/testhal/TIVA/TM4C123x/GPT/main.c
+++ b/testhal/TIVA/TM4C123x/GPT/main.c
@@ -23,7 +23,7 @@
 static void gpt1cb(GPTDriver *gptp)
 {
   (void)gptp;
-  palClearPad(GPIOF, GPIOF_LED_RED);
+  palClearLine(LINE_LED_RED);
 }
 
 /*
@@ -32,7 +32,7 @@ static void gpt1cb(GPTDriver *gptp)
 static void gpt7cb(GPTDriver *gptp)
 {
   (void)gptp;
-  palSetPad(GPIOF, GPIOF_LED_RED);
+  palSetLine(LINE_LED_RED);
   chSysLockFromISR();
   gptStartOneShotI(&GPTD1, 31250);  /* 0.1 second pulse.*/
   chSysUnlockFromISR();
@@ -71,7 +71,7 @@ int main(void)
   halInit();
   chSysInit();
 
-  palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
 
   /*
    * Start the gpt drivers with the custom configurations.
diff --git a/testhal/TIVA/TM4C123x/I2C/main.c b/testhal/TIVA/TM4C123x/I2C/main.c
index 5f58176..5c5e704 100644
--- a/testhal/TIVA/TM4C123x/I2C/main.c
+++ b/testhal/TIVA/TM4C123x/I2C/main.c
@@ -70,8 +70,8 @@ int main(void)
   chSysInit();
 
   /* Configure RX and TX pins for UART0.*/
-  palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
-  palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
+  palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
 
   /*
    * Start the serial driver with the default configuration.
@@ -79,8 +79,8 @@ int main(void)
   sdStart(&SD1, NULL);
 
   /* Configure SCK and SCL pins for I2C0.*/
-  palSetPadMode(GPIOB, GPIOB_I2C0_SCL, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(3));
-  palSetPadMode(GPIOB, GPIOB_I2C0_SDA, PAL_MODE_OUTPUT_OPENDRAIN | PAL_MODE_ALTERNATE(3));
+  palSetLineMode(LINE_I2C0_SCL, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(3));
+  palSetLineMode(LINE_I2C0_SDA, PAL_MODE_OUTPUT_OPENDRAIN | PAL_MODE_ALTERNATE(3));
 
   /*
    * Start the i2c driver with the custom configuration.
diff --git a/testhal/TIVA/TM4C123x/PWM/main.c b/testhal/TIVA/TM4C123x/PWM/main.c
index 4772e6c..14fd967 100644
--- a/testhal/TIVA/TM4C123x/PWM/main.c
+++ b/testhal/TIVA/TM4C123x/PWM/main.c
@@ -20,27 +20,27 @@
 static void pwmpcb(PWMDriver *pwmp)
 {
   (void)pwmp;
-  palClearPad(GPIOF, GPIOF_LED_RED);
-  palClearPad(GPIOF, GPIOF_LED_GREEN);
-  palClearPad(GPIOF, GPIOF_LED_BLUE);
+  palClearLine(LINE_LED_RED);
+  palClearLine(LINE_LED_GREEN);
+  palClearLine(LINE_LED_BLUE);
 }
 
 static void pwmc1cb0(PWMDriver *pwmp)
 {
   (void)pwmp;
-  palSetPad(GPIOF, GPIOF_LED_RED);
+  palSetLine(LINE_LED_RED);
 }
 
 static void pwmc1cb1(PWMDriver *pwmp)
 {
   (void)pwmp;
-  palSetPad(GPIOF, GPIOF_LED_GREEN);
+  palSetLine(LINE_LED_GREEN);
 }
 
 static void pwmc1cb2(PWMDriver *pwmp)
 {
   (void)pwmp;
-  palSetPad(GPIOF, GPIOF_LED_BLUE);
+  palSetLine(LINE_LED_BLUE);
 }
 
 static PWMConfig pwmcfg = {
@@ -74,9 +74,9 @@ int main(void)
   halInit();
   chSysInit();
 
-  palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
-  palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
-  palSetPadMode(GPIOF, GPIOF_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);
 
   /*
    * Start PWM driver
diff --git a/testhal/TIVA/TM4C123x/SPI/main.c b/testhal/TIVA/TM4C123x/SPI/main.c
index 7fa05ee..d4bbad2 100644
--- a/testhal/TIVA/TM4C123x/SPI/main.c
+++ b/testhal/TIVA/TM4C123x/SPI/main.c
@@ -104,15 +104,11 @@ int main(void)
   halInit();
   chSysInit();
 
-  palSetPadMode(GPIOA, GPIOA_SSI0_CLK,  PAL_MODE_OUTPUT_PUSHPULL |
-                                        PAL_MODE_ALTERNATE(2));
-  palSetPadMode(GPIOA, GPIOA_SSI0_RX,   PAL_MODE_OUTPUT_PUSHPULL |
-                                        PAL_MODE_ALTERNATE(2));
-  palSetPadMode(GPIOA, GPIOA_SSI0_TX,   PAL_MODE_OUTPUT_PUSHPULL |
-                                        PAL_MODE_ALTERNATE(2));
-  palSetPadMode(GPIOA, GPIOA_PIN3,      PAL_MODE_OUTPUT_PUSHPULL);
-
-  palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_SSI0_CLK, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(2));
+  palSetLineMode(LINE_SSI0_RX, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(2));
+  palSetLineMode(LINE_SSI0_TX, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(2));
+  palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetPadMode(GPIOA, GPIOA_PIN3, PAL_MODE_OUTPUT_PUSHPULL);
 
   /*
    * Prepare transmit pattern.
@@ -124,10 +120,16 @@ int main(void)
   /*
    * Starting the transmitter and receiver threads.
    */
-  chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
-                    NORMALPRIO + 1, spi_thread_1, NULL);
-  chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
-                    NORMALPRIO + 1, spi_thread_2, NULL);
+  chThdCreateStatic(spi_thread_1_wa,
+                    sizeof(spi_thread_1_wa),
+                    NORMALPRIO + 1,
+                    spi_thread_1,
+                    NULL);
+  chThdCreateStatic(spi_thread_2_wa,
+                    sizeof(spi_thread_2_wa),
+                    NORMALPRIO + 1,
+                    spi_thread_2,
+                    NULL);
 
   /*
    * Normal main() thread activity
diff --git a/testhal/TIVA/TM4C123x/WDG/main.c b/testhal/TIVA/TM4C123x/WDG/main.c
index d5fa9e6..63f76f5 100644
--- a/testhal/TIVA/TM4C123x/WDG/main.c
+++ b/testhal/TIVA/TM4C123x/WDG/main.c
@@ -21,7 +21,7 @@ static bool watchdog_timeout(WDGDriver *wdgp)
 {
   (void)wdgp;
 
-  palSetPad(GPIOF, GPIOF_LED_RED);
+  palSetLine(LINE_LED_RED);
 
   /* Return true to prevent a reset on the next timeout.*/
   return true;
@@ -54,11 +54,10 @@ int main(void) {
   halInit();
   chSysInit();
 
-  palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
-  palSetPadMode(GPIOF, GPIOF_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetLineMode(LINE_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);
 
-  palSetPadMode(GPIOF, GPIOF_SW1, PAL_MODE_INPUT_PULLUP);
-  palSetPadMode(GPIOF, GPIOF_SW2, PAL_MODE_INPUT_PULLUP);
+  palSetLineMode(LINE_SW1, PAL_MODE_INPUT_PULLUP);
 
   /*
    * Starting the watchdog driver.
@@ -69,13 +68,13 @@ int main(void) {
    * Normal main() thread activity, it resets the watchdog.
    */
   while (true) {
-    if (palReadPad(GPIOF, GPIOF_SW1)) {
+    if (palReadLine(LINE_SW1)) {
       /* Only reset the watchdog if the button is not pressed */
       wdgReset(&WDGD1);
-      palClearPad(GPIOF, GPIOF_LED_RED);
+      palClearLine(LINE_LED_RED);
     }
 
-    palTogglePad(GPIOF, GPIOF_LED_BLUE);
+    palToggleLine(LINE_LED_BLUE);
 
     chThdSleepMilliseconds(500);
   }
-- 
cgit v1.2.3


From b783488ec677927879b14cef1e043133cfecedcc Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 14:37:02 +0100
Subject: Added check for a valid device in the TM4C129x series.

---
 os/hal/ports/TIVA/TM4C129x/tiva_registry.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
index 99e4f81..a139c09 100644
--- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -25,6 +25,23 @@
 #ifndef _TIVA_REGISTRY_H_
 #define _TIVA_REGISTRY_H_
 
+#if !defined(PART_TM4C1290NCPDT) && !defined(PART_TM4C1290NCZAD) && !defined(PART_TM4C1292NCPDT)\
+  && !defined(PART_TM4C1292NCZAD) && !defined(PART_TM4C1294KCPDT) && !defined(PART_TM4C1294NCPDT)\
+  && !defined(PART_TM4C1294NCZAD) && !defined(PART_TM4C1297NCZAD) && !defined(PART_TM4C1299KCZAD)\
+  && !defined(PART_TM4C1299NCZAD) && !defined(PART_TM4C129CNCPDT) && !defined(PART_TM4C129CNCZAD)\
+  && !defined(PART_TM4C129DNCPDT) && !defined(PART_TM4C129DNCZAD) && !defined(PART_TM4C129EKCPDT)\
+  && !defined(PART_TM4C129ENCPDT) && !defined(PART_TM4C129ENCZAD) && !defined(PART_TM4C129LNCZAD)\
+  && !defined(PART_TM4C129XKCZAD) && !defined(PART_TM4C129XNCZAD)
+#error "No valid device defined."
+#endif
+
+/**
+ * @brief   Sub-family identifier.
+ */
+#if !defined(TM4C129x) || defined(__DOXYGEN__)
+#define TM4C129x
+#endif
+
 /*===========================================================================*/
 /* Platform capabilities.                                                    */
 /*===========================================================================*/
-- 
cgit v1.2.3


From 79fc9cfe5dd29e672511e20012e4fa699d07f678 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 30 Oct 2016 14:38:02 +0100
Subject: Added checks and defines for device revisions.

This can be used for errata workarounds in the drivers.
---
 os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 3 ++-
 os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 3 ++-
 os/hal/ports/TIVA/TM4C123x/tiva_registry.h  | 6 ++++++
 os/hal/ports/TIVA/TM4C129x/tiva_registry.h  | 4 ++++
 4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
index c337e21..7660c09 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
@@ -28,9 +28,10 @@
 #define BOARD_NAME              "Texas Instruments TM4C123G Launchpad"
 
 /*
- * MCU type as defined in the TI header.
+ * MCU type and revision as defined in the TI header.
  */
 #define PART_TM4C123GH6PM
+#define TARGET_IS_TM4C123_RB1
 
 /*
  * Board oscillators-related settings.
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
index 982fb1b..57fd268 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
@@ -36,9 +36,10 @@
 //#define BOARD_PHY_RMII
 
 /*
- * MCU type as defined in the TI header.
+ * MCU type and revision as defined in the TI header.
  */
 #define PART_TM4C1294NCPDT
+#define TARGET_IS_TM4C129_RA0
 
 /*
  * Board oscillators-related settings.
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
index 88cc376..4ff9f60 100644
--- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
@@ -58,6 +58,12 @@
 #error "No valid device defined."
 #endif
 
+#if !defined(TARGET_IS_TM4C123_RA1) && !defined(TARGET_IS_TM4C123_RA2) && \
+    !defined(TARGET_IS_TM4C123_RA3) && !defined(TARGET_IS_TM4C123_RB0) && \
+    !defined(TARGET_IS_TM4C123_RB1)
+#error "No valid device revision defined."
+#endif
+
 /**
  * @brief   Sub-family identifier.
  */
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
index a139c09..235877f 100644
--- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -35,6 +35,10 @@
 #error "No valid device defined."
 #endif
 
+#if !defined(TARGET_IS_TM4C129_RA0)
+#error "No valid device revision defined."
+#endif
+
 /**
  * @brief   Sub-family identifier.
  */
-- 
cgit v1.2.3


From ed9c079d623b0a2c2f90a4c9efc8063aba9a6456 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 11 Nov 2016 23:01:07 +0100
Subject: Fixed the MAC driver.

While moving the MAC driver to TivaWare the addresses used in the HWREG macros were incorrect. The base address was missing.
---
 os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c | 100 ++++++++++++++++----------------
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
index cf64bbb..7c33a85 100644
--- a/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
+++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c
@@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
  */
 static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
 {
-  HWREG(EMAC_O_MIIDATA) = value;
-  HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
+  HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = value;
+  HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
 
-  while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
+  while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
     ;
 }
 
@@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
  */
 static uint32_t mii_read(MACDriver *macp, uint32_t reg)
 {
-  HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
+  HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
 
-  while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
+  while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
     ;
 
-  return HWREG(EMAC_O_MIIDATA);
+  return HWREG(EMAC0_BASE + EMAC_O_MIIDATA);
 }
 
 /**
@@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp)
 #endif
     for (i = 0; i < 31; i++) {
       macp->phyaddr = i << 11;
-      HWREG(EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
+      HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
       if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
           ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
         return;
@@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p)
 {
   /* MAC address configuration, only a single address comparator is used,
      hash table not used.*/
-  HWREG(EMAC_O_ADDR0H)   = ((uint32_t)p[5] << 8) |
+  HWREG(EMAC0_BASE + EMAC_O_ADDR0H)   = ((uint32_t)p[5] << 8) |
                   ((uint32_t)p[4] << 0);
-  HWREG(EMAC_O_ADDR0L)   = ((uint32_t)p[3] << 24) |
+  HWREG(EMAC0_BASE + EMAC_O_ADDR0L)   = ((uint32_t)p[3] << 24) |
                   ((uint32_t)p[2] << 16) |
                   ((uint32_t)p[1] << 8) |
                   ((uint32_t)p[0] << 0);
-  HWREG(EMAC_O_ADDR1H)   = 0x0000FFFF;
-  HWREG(EMAC_O_ADDR1L)   = 0xFFFFFFFF;
-  HWREG(EMAC_O_ADDR2H)   = 0x0000FFFF;
-  HWREG(EMAC_O_ADDR2L)   = 0xFFFFFFFF;
-  HWREG(EMAC_O_ADDR3H)   = 0x0000FFFF;
-  HWREG(EMAC_O_ADDR3L)   = 0xFFFFFFFF;
-  HWREG(EMAC_O_HASHTBLH) = 0;
-  HWREG(EMAC_O_HASHTBLL) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR1H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR1L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR2H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR2L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR3H)   = 0x0000FFFF;
+  HWREG(EMAC0_BASE + EMAC_O_ADDR3L)   = 0xFFFFFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_HASHTBLH) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_HASHTBLL) = 0;
 }
 
 /*===========================================================================*/
@@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
 
   CH_IRQ_PROLOGUE();
 
-  dmaris = HWREG(EMAC_O_DMARIS);
-  HWREG(EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
+  dmaris = HWREG(EMAC0_BASE + EMAC_O_DMARIS);
+  HWREG(EMAC0_BASE + EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
 
   if (dmaris & (1 << 6)) {
     /* Data Received.*/
@@ -280,7 +280,7 @@ void mac_lld_init(void)
     ;
 
   /* Set PHYHOLD bit */
-  HWREG(EMAC_O_PC) |= 1;
+  HWREG(EMAC0_BASE + EMAC_O_PC) |= 1;
 
   /* Enable PHY clock */
   HWREG(SYSCTL_RCGCEPHY) = 1;
@@ -292,9 +292,9 @@ void mac_lld_init(void)
   while (HWREG(SYSCTL_PREPHY) != 0x01)
     ;
 #if BOARD_PHY_RMII
-  HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
+  HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
 #else
-  HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG;
+  HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG;
 #endif
 
   /*
@@ -310,12 +310,12 @@ void mac_lld_init(void)
   /* Set done bit after writing EMACPC register */
   mii_write(&ETHD1, TIVA_CFG1, (1 << 15) | mii_read(&ETHD1, TIVA_CFG1));
 
-  while(HWREG(EMAC_O_DMABUSMOD) & 1)
+  while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
     ;
 
   /* Reset MAC */
-  HWREG(EMAC_O_DMABUSMOD) |= 1;
-  while (HWREG(EMAC_O_DMABUSMOD) & 1)
+  HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) |= 1;
+  while (HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
     ;
 
   /* PHY address setup.*/
@@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp)
 #endif
 
   /* MAC configuration.*/
-  HWREG(EMAC_O_FRAMEFLTR) = 0;
-  HWREG(EMAC_O_FLOWCTL) = 0;
-  HWREG(EMAC_O_VLANTG) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_FLOWCTL) = 0;
+  HWREG(EMAC0_BASE + EMAC_O_VLANTG) = 0;
 
   /* MAC address setup.*/
   if (macp->config->mac_address == NULL)
@@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp)
      Note that the complete setup of the MAC is performed when the link
      status is detected.*/
 #if TIVA_MAC_IP_CHECKSUM_OFFLOAD
-  HWREG(EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
+  HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
 #else
-  HWREG(EMAC_O_CFG) =             (1 << 3) | (1 << 2);
+  HWREG(EMAC0_BASE + EMAC_O_CFG) =             (1 << 3) | (1 << 2);
 #endif
 
   /* DMA configuration:
      Descriptor chains pointers.*/
-  HWREG(EMAC_O_RXDLADDR) = (uint32_t)rd;
-  HWREG(EMAC_O_TXDLADDR) = (uint32_t)td;
+  HWREG(EMAC0_BASE + EMAC_O_RXDLADDR) = (uint32_t)rd;
+  HWREG(EMAC0_BASE + EMAC_O_TXDLADDR) = (uint32_t)td;
 
   /* Enabling required interrupt sources.*/
-  HWREG(EMAC_O_DMARIS) &= 0xFFFF;
-  HWREG(EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
+  HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
+  HWREG(EMAC0_BASE + EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
 
   /* DMA general settings.*/
-  HWREG(EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
+  HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
 
   /* Transmit FIFO flush.*/
-  HWREG(EMAC_O_DMAOPMODE) = (1 << 20);
-  while (HWREG(EMAC_O_DMAOPMODE) & (1 << 20))
+  HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 20);
+  while (HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) & (1 << 20))
     ;
 
   /* DMA final configuration and start.*/
-  HWREG(EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
+  HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
                         (1 << 13) | (1 << 1);
 }
 
@@ -449,10 +449,10 @@ void mac_lld_stop(MACDriver *macp)
 #endif
 
     /* MAC and DMA stopped.*/
-    HWREG(EMAC_O_CFG) = 0;
-    HWREG(EMAC_O_DMAOPMODE) = 0;
-    HWREG(EMAC_O_DMAIM) = 0;
-    HWREG(EMAC_O_DMARIS) &= 0xFFFF;
+    HWREG(EMAC0_BASE + EMAC_O_CFG) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMAIM) = 0;
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
 
     /* MAC clocks stopped.*/
     HWREG(SYSCTL_RCGCEMAC) = 0;
@@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
   tdp->physdesc->locked = 0;
 
   /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((HWREG(EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
-    HWREG(EMAC_O_DMARIS)   = (1 << 2);
-    HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
+  if ((HWREG(EMAC0_BASE + EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS)   = (1 << 2);
+    HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
   }
 
   osalSysUnlock();
@@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
   rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
 
   /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((HWREG(EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
-    HWREG(EMAC_O_DMARIS)   = (1 << 7);
-    HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
+  if ((HWREG(EMAC0_BASE + EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
+    HWREG(EMAC0_BASE + EMAC_O_DMARIS)   = (1 << 7);
+    HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
   }
 
   osalSysUnlock();
@@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
 {
   uint32_t maccfg, bmsr, bmcr;
 
-  maccfg = HWREG(EMAC_O_CFG);
+  maccfg = HWREG(EMAC0_BASE + EMAC_O_CFG);
 
   /* PHY CR and SR registers read.*/
   (void)mii_read(macp, MII_BMSR);
@@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
   }
 
   /* Changes the mode in the MAC.*/
-  HWREG(EMAC_O_CFG) = maccfg;
+  HWREG(EMAC0_BASE + EMAC_O_CFG) = maccfg;
 
   /* Returns the link status.*/
   return macp->link_up = true;
-- 
cgit v1.2.3


From 3ad1b1b07c3372b5d1289531af7c069310843480 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 11 Nov 2016 23:01:39 +0100
Subject: Deleted custom Tiva CMSIS headers.

---
 os/hal/ports/TIVA/TM4C123x/tm4c123x.h |  958 ----------------------------
 os/hal/ports/TIVA/TM4C129x/tm4c129x.h | 1131 ---------------------------------
 2 files changed, 2089 deletions(-)
 delete mode 100644 os/hal/ports/TIVA/TM4C123x/tm4c123x.h
 delete mode 100644 os/hal/ports/TIVA/TM4C129x/tm4c129x.h

diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
deleted file mode 100644
index d64afa8..0000000
--- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
+++ /dev/null
@@ -1,958 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @addtogroup CMSIS
- * @{
- */
-
-/**
- * @addtogroup TM4C123x
- * @{
- */
-
-#ifndef __TM4C123x_H
-#define __TM4C123x_H
-
-/** 
- * @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
-#define __MPU_PRESENT           1       /**< MPU present                     */
-#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
-#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
-#define __FPU_PRESENT           1       /**< FPU present                     */
-
-/**
- * @brief   TM4C123x Interrupt Number Definitions
- */
-typedef enum IRQn
-{
-  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
-  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
-  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
-  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
-  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
-  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
-  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
-  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
-  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
-  /***** TM4C123x Specific Interrupt Numbers *********************************/
-  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
-  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
-  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
-  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
-  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
-  UART0_IRQn            = 5,    /**< UART0                                   */
-  UART1_IRQn            = 6,    /**< UART1                                   */
-  SSI0_IRQn             = 7,    /**< SSI0                                    */
-  I2C0_IRQn             = 8,    /**< I2C0                                    */
-  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
-  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
-  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
-  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
-  QEI0_IRQn             = 13,   /**< QEI0                                    */
-  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
-  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
-  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
-  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
-  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
-  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
-  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
-  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
-  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
-  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
-  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
-  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
-  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
-  SYSCON_IRQn           = 28,   /**< System Control                          */
-  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
-  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
-  UART2_IRQn            = 33,   /**< UART2                                   */
-  SSI1_IRQn             = 34,   /**< SSI1                                    */
-  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
-  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
-  I2C1_IRQn             = 37,   /**< I2C1                                    */
-  QEI1_IRQn             = 38,   /**< QEI1                                    */
-  CAN0_IRQn             = 39,   /**< CAN0                                    */
-  CAN1_IRQn             = 40,   /**< CAN1                                    */
-  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
-  USB_IRQn              = 44,   /**< USB                                     */
-  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
-  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
-  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
-  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
-  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
-  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
-  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
-  SSI2_IRQn             = 57,   /**< SSI2                                    */
-  SSI3_IRQn             = 58,   /**< SSI3                                    */
-  UART3_IRQn            = 59,   /**< UART3                                   */
-  UART4_IRQn            = 60,   /**< UART4                                   */
-  UART5_IRQn            = 61,   /**< UART5                                   */
-  UART6_IRQn            = 62,   /**< UART6                                   */
-  UART7_IRQn            = 63,   /**< UART7                                   */
-  I2C2_IRQn             = 68,   /**< I2C2                                    */
-  I2C3_IRQn             = 69,   /**< I2C3                                    */
-  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
-  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
-  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
-  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
-  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
-  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
-  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
-  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
-  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
-  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
-  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
-  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
-  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
-  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
-  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
-  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
-  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
-  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
-  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
-  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
-  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
-  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
-} IRQn_Type;
- 
-/**
- * @}
- */
-
-#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
-#include <stdint.h>
-
-/**
- * @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog Comparator
- */
-typedef struct
-{
-  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __I  uint32_t STAT0;          /**< Status 0                                */
-  __IO uint32_t CTL0;           /**< Control 0                               */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t STAT1;          /**< Status 1                                */
-  __IO uint32_t CTL1;           /**< Control 1                               */
-  __I  uint32_t _RESERVED3[990];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} ACMP_TypeDef;
-
-/**
- * @brief Analog-to-Digital Converter
- */
-typedef struct
-{
-  __IO uint32_t MUX;            /**< Sample Sequence Input Multiplexer
-                                     Select                                  */
-  __IO uint32_t CTL;            /**< Sample Sequence Control                 */
-  __I  uint32_t FIFO;           /**< Sample Sequence Result FIFO             */
-  __I  uint32_t FSTAT;          /**< Sample Sequence FIFO Status             */
-  __IO uint32_t OP;             /**< Sample Sequence Operation               */
-  __IO uint32_t DC;             /**< Sample Sequence Digital Comparator
-                                     Select                                  */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-} ADC_SS_t;
-
-typedef struct
-{
-  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t OSTAT;          /**< Overflow Status                         */
-  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
-  __IO uint32_t USTAT;          /**< Underflow Status                        */
-  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
-  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
-  __IO uint32_t SPC;            /**< Sample Phase Control                    */
-  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t SAC;            /**< Sample Averaging Control                */
-  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and
-                                     Clear                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  ADC_SS_t SS[4];               /**< Sample Sequence 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[784];/**< Reserved */
-  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
-                                     Conditions                              */
-  __I  uint32_t _RESERVED3[63]; /**< Reserved                                */
-  __IO uint32_t DCCTL[8];       /**< Digital Comparator Control 0 - 7        */
-  __I  uint32_t _RESERVED4[8];  /**< Reserved                                */
-  __IO uint32_t DCCMP[8];       /**< Digital Comparator Range 0 - 7          */
-  __I  uint32_t _RESERVED5[88]; /**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __IO uint32_t PC;             /**< Peripheral Configuration                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} ADC_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
-  __IO uint32_t CRQ;            /**< Command Request                         */
-  __IO uint32_t CMSK;           /**< Command Mask                            */
-  __IO uint32_t MSK[2];         /**< Mask 1 and 2                            */
-  __IO uint32_t ARB[2];         /**< Arbitration 1 and 2                     */
-  __IO uint32_t MCTL;           /**< Message Control                         */
-  __IO uint32_t DA[2];          /**< Data A1 and A2                          */
-  __IO uint32_t DB[2];          /**< Data B1 and B2                          */
-  __I  uint32_t _RESERVED0[13]; /**< Reserved                                */
-} CAN_INTERFACE_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t STS;            /**< Status                                  */
-  __I  uint32_t ERR;            /**< Error Counter                           */
-  __IO uint32_t BIT;            /**< Bit Timing                              */
-  __I  uint32_t INT;            /**< Interrupt                               */
-  __IO uint32_t TST;            /**< Test                                    */
-  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  CAN_INTERFACE_t IF[2];        /**< IF1 and IF2                             */
-  __I  uint32_t _RESERVED1[8];  /**< Reserved                                */
-  __I  uint32_t TXRQ[2];        /**< Transmission Request 1 and 2            */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t NWDA[2];        /**< New Data 1 and 2                        */
-  __I  uint32_t _RESERVED3[6];  /**< Reserved                                */
-  __I  uint32_t MSGINT[2];      /**< Message 1 and 2 Interrupt Pending       */
-  __I  uint32_t _RESERVED4[6];  /**< Reserved                                */
-  __I  uint32_t MSGVAL[2];      /**< Message 1 and 2 Valid                   */
-} CAN_TypeDef;
-
-/**
- * @brief EEPROM Memory
- */
-typedef struct
-{
-  __IO uint32_t EESIZE;         /**< Size Information                        */
-  __IO uint32_t EEBLOCK;        /**< Current Block                           */
-  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t EERDWR;         /**< Read-Write                              */
-  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
-  __IO uint32_t EEDONE;         /**< Done Status                             */
-  __IO uint32_t EESUPP;         /**< Support Control and Status              */
-  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t EEPROT;         /**< Protection                              */
-  __IO uint32_t EEPASS[3];      /**< Password                                */
-  __IO uint32_t EEINT;          /**< Interrupt                               */
-  __I  uint32_t _RESERVED2[3];  /**< Reserved                                */
-  __IO uint32_t EEHIDE;         /**< Block Hide                              */
-  __I  uint32_t _RESERVED3[11]; /**< Reserved                                */
-  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
-  __I  uint32_t _RESERVED4[975];/**< Reserved                                */
-  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
-} EEPROM_TypeDef;
-
-/**
- * @brief Flash Memory
- */
-typedef struct
-{
-  __IO uint32_t FMA;            /**< Flash Memory Address                    */
-  __IO uint32_t FMD;            /**< Flash Memory Data                       */
-  __IO uint32_t FMC;            /**< Flash Memory Control                    */
-  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
-  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
-  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
-  __I  uint32_t _RESERVED2[51]; /**< Reserved                                */
-  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
-  __I  uint32_t _RESERVED3[943];/**< Reserved                                */
-  __I  uint32_t FSIZE;          /**< Flash Size                              */
-  __I  uint32_t SSIZE;          /**< SRAM Size                               */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
-} FLASH_TypeDef;
-
-/**
- * @brief General Purpose Input/Outputs
- */
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
-    struct {
-      __I  uint32_t _RESERVED0[255];    /**< Reserved                        */
-      __IO uint32_t DATA;       /**< Data                                    */
-    };
-  };
-  __IO uint32_t DIR;            /**< Direction                               */
-  __IO uint32_t IS;             /**< Interrupt Sense                         */
-  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
-  __IO uint32_t IEV;            /**< Interrupt Event                         */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
-  __I  uint32_t _RESERVED1[55]; /**< Reserved                                */
-  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
-  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
-  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
-  __IO uint32_t ODR;            /**< Open Drain Select                       */
-  __IO uint32_t PUR;            /**< Pull-Up Select                          */
-  __IO uint32_t PDR;            /**< Pull-Down Select                        */
-  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
-  __IO uint32_t DEN;            /**< Digital Enable                          */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-  __IO uint32_t CR;             /**< Commit                                  */
-  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
-  __IO uint32_t PCTL;           /**< Port Control                            */
-  __IO uint32_t ADCCTL;         /**< ADC Control                             */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-} GPIO_TypeDef;
-
-/**
- * @brief General Purpose Timer
- */
-typedef struct
-{
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t TAMR;           /**< Timer A Mode                            */
-  __IO uint32_t TBMR;           /**< Timer B Mode                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t SYNC;           /**< Synchronize                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t IMR;            /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
-  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
-  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
-  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
-  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
-  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
-  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
-  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
-  __I  uint32_t TAR;            /**< Timer A                                 */
-  __I  uint32_t TBR;            /**< Timer B                                 */
-  __IO uint32_t TAV;            /**< Timer A Value                           */
-  __IO uint32_t TBV;            /**< Timer B Value                           */
-  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
-  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
-  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
-  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
-  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
-  __I  uint32_t _RESERVED1[981];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} GPT_TypeDef;
-
-/**
- * @brief Hibernation Module
- */
-typedef struct
-{
-  __I  uint32_t RTCC;           /**< RTC Counter                             */
-  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t RTCLD;          /**< RTC Load                                */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __IO uint32_t IC;             /**< Interrupt Clear                         */
-  __IO uint32_t RTCT;           /**< RTC Trim                                */
-  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t DATA;           /**< Data                                    */
-} HIB_TypeDef;
-
-/**
- * @brief Inter-Integrated Circuit
- */
-typedef struct
-{
-  __IO uint32_t MSA;            /**< Master Slave Address                    */
-  __IO uint32_t MCS;            /**< Master Control/Status                   */
-  __IO uint32_t MDR;            /**< Master Data                             */
-  __IO uint32_t MTPR;           /**< Master Timer Period                     */
-  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
-  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
-  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
-  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
-  __IO uint32_t MCR;            /**< Master Configuration                    */
-  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
-  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
-  __I  uint32_t _RESERVED1[497];/**< Reserved                                */
-  __IO uint32_t SOAR;           /**< Slave Own Address                       */
-  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
-  __IO uint32_t SDR;            /**< Slave Data                              */
-  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
-  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
-  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
-  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
-  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
-  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
-  __I  uint32_t _RESERVED2[487];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t PC;             /**< Peripheral Configuration                */
-} I2C_TypeDef;
-
-/*
- * @brief Pulse Width Modulator
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t COUNT;          /**< Counter                                 */
-  __IO uint32_t CMP[2];         /**< Compare A, B                            */
-  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
-  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
-  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
-  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
-  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
-  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
-} PWM_GENERATOR_T;
-
-typedef struct
-{
-  union {
-    __IO uint32_t SEN;          /**< Fault Pin Logic Sense, for GEN 0 and 1  */
-    __I  uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3               */
-  };
-  __IO uint32_t STAT[2];        /**< Fault Status                            */
-  __I  uint32_t _RESERVED1[29]; /**< Reserved                                */
-} PWM_FLT_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Master Control                          */
-  __IO uint32_t SYNC;           /**< Time Base Sync                          */
-  __IO uint32_t ENABLE;         /**< Output Enable                           */
-  __IO uint32_t INVERT;         /**< Output Inversion                        */
-  __IO uint32_t FAULT;          /**< Output Fault                            */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __I  uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
-  __IO uint32_t ENUPD;          /**< Enable Update                           */
-  __I  uint32_t _RESERVED0[5];  /**< Reserved                                */
-  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
-  __I  uint32_t _RESERVED1[432];/**< Reserved                                */
-  PWM_FLT_t FLT[4];             /**< Fault registers 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[368];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} PWM_TypeDef;
-
-/**
- * @brief Quadrature Encoder Interface
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t STAT;           /**< Status                                  */
-  __IO uint32_t POS;            /**< Position                                */
-  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
-  __IO uint32_t LOAD;           /**< Timer Load                              */
-  __I  uint32_t TIME;           /**< Timer                                   */
-  __I  uint32_t COUNT;          /**< Velocity Counter                        */
-  __I  uint32_t SPEED;          /**< Velocity                                */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-} QEI_TypeDef;
-
-/**
- * @brief Synchronous Serial Interface
- */
-typedef struct
-{
-  __IO uint32_t CR0;            /**< Control 0                               */
-  __IO uint32_t CR1;            /**< Control 1                               */
-  __IO uint32_t DR;             /**< Data                                    */
-  __I  uint32_t SR;             /**< Status                                  */
-  __IO uint32_t CPSR;           /**< Clock Prescale                          */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED0[1000];/**< Reserved                               */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} SSI_TypeDef;
-
-/** 
- * @brief System Control
- */
-typedef struct
-{
-  __I  uint32_t DID0;           /**< Device Identification 0                 */
-  __I  uint32_t DID1;           /**< Device Identification 1                 */
-  __I  uint32_t RESERVED0[10];  /**< Reserved                                */
-  __IO uint32_t PBORCTL;        /**< Brown-Out Reset Control                 */
-  __I  uint32_t RESERVED1[7];   /**< Reserved                                */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
-  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
-  __IO uint32_t RESC;           /**< Reset Cause                             */
-  __IO uint32_t RCC;            /**< Run-Mode Clock Configuration            */
-  __I  uint32_t RESERVED2[2];   /**< Reserved                                */
-  __IO uint32_t GPIOHBCTL;      /**< GPIO High-Performance Bus Control       */
-  __IO uint32_t RCC2;           /**< Run-Mode Clock Configuration 2          */
-  __I  uint32_t RESERVED3[2];   /**< Reserved                                */
-  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control                 */
-  __I  uint32_t RESERVED4[49];  /**< Reserved                                */
-  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
-  __I  uint32_t RESERVED5[1];   /**< Reserved                                */
-  __I  uint32_t SYSPROP;        /**< System Properties                       */
-  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
-  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
-  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
-  __I  uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
-  __I  uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
-  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
-  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
-  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
-  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
-  __I  uint32_t RESERVED8[9];   /**< Reserved                                */
-  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
-  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
-  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
-  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
-  __I  uint32_t RESERVED9[2];   /**< Reserved                                */
-  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
-  __I  uint32_t RESERVED10[76]; /**< Reserved                                */
-  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
-  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
-  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
-  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
-  __I  uint32_t RESERVED11[1];  /**< Reserved                                */
-  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
-  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
-  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
-  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
-  __I  uint32_t RESERVED12[1];  /**< Reserved                                */
-  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
-  __I  uint32_t RESERVED13[2];  /**< Reserved                                */
-  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
-  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
-  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
-  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
-  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
-  __I  uint32_t RESERVED14[4];  /**< Reserved                                */
-  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
-  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
-  __I  uint32_t RESERVED15[104];/**< Reserved                                */
-  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
-  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
-  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
-  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
-  __IO uint32_t SRUART;         /**< UART Software Reset                     */
-  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
-  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
-  __I  uint32_t RESERVED17[1];  /**< Reserved                                */
-  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
-  __I  uint32_t RESERVED18[2];  /**< Reserved                                */
-  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
-  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
-  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
-  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
-  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
-  __I  uint32_t RESERVED19[4];  /**< Reserved                                */
-  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
-  __IO uint32_t SRWTIMER;       /**< Wide GPT Software Reset                 */
-  __I  uint32_t RESERVED20[40]; /**< Reserved                                */
-  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
-  __I  uint32_t RESERVED21[1];  /**< Reserved                                */
-  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
-  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
-  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED23[2];  /**< Reserved                                */
-  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
-  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
-  __IO uint32_t RCGCWTIMER;     /**< Wide GPT Run Mode Clock Gating Control  */
-  __I  uint32_t RESERVED25[40]; /**< Reserved                                */
-  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
-  __I  uint32_t RESERVED26[1];  /**< Reserved                                */
-  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED27[1];  /**< Reserved                                */
-  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED28[2];  /**< Reserved                                */
-  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED29[4];  /**< Reserved                                */
-  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
-  __IO uint32_t SCGCWTIMER;     /**< Wide GPT Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED30[40]; /**< Reserved                                */
-  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED31[1];  /**< Reserved                                */
-  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED32[1];  /**< Reserved                                */
-  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED33[2];  /**< Reserved                                */
-  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED34[4];  /**< Reserved                                */
-  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCWTIMER;     /**< Wide GPT Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED35[104];/**< Reserved                                */
-  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
-  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
-  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
-  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
-  __I  uint32_t RESERVED36[1];  /**< Reserved                                */
-  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
-  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
-  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
-  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
-  __I  uint32_t RESERVED37[1];  /**< Reserved                                */
-  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
-  __I  uint32_t RESERVED38[2];  /**< Reserved                                */
-  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
-  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
-  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
-  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
-  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
-  __I  uint32_t RESERVED39[4];  /**< Reserved                                */
-  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
-  __IO uint32_t PRWTIMER;       /**< Wide GPT Peripheral Ready               */
-} SYSCTL_TypeDef;
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter
- */
-typedef struct
-{
-  __IO uint32_t DR;             /**< Data                                    */
-  union  {
-    __I  uint32_t RSR;          /**< Receive Status                          */
-    __O  uint32_t ECR;          /**< Error Clear                             */
-  };
-  __I  uint32_t _RESERVED0[4];  /**< Reserved                                */
-  __I  uint32_t FR;             /**< Flag                                    */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
-  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
-  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
-  __IO uint32_t LCRH;           /**< Line Control                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O uint32_t ICR;             /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED2[22]; /**< Reserved                                */
-  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
-  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
-  __I  uint32_t _RESERVED3[965];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} UART_TypeDef;
-
-/**
- * @brief Micro Direct Memory Access
- */
-typedef struct
-{
-  __IO uint32_t SET;            /**< Set                                     */
-  __O  uint32_t CLR;            /**< Clear                                   */
-} UDMA_SC_t;
-
-typedef struct
-{
-  __IO uint32_t STAT;           /**< Status                                  */
-  __O  uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
-  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
-  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
-  __O  uint32_t SWREQ;          /**< Channel Software Request                */
-  __IO uint32_t USEBURSTSET;    /**< Channel Useburst Set                    */
-  __O  uint32_t USEBURSTCLR;    /**< Channel Useburst Clear                  */
-  __IO uint32_t REQMASKSET;     /**< Channel Request Mask Set                */
-  __O  uint32_t REQMASKCLR;     /**< Channel Request Mask Clear              */
-  __IO uint32_t ENASET;         /**< Channel Enable Set                      */
-  __O  uint32_t ENACLR;         /**< Channel Enable Clear                    */
-  __IO uint32_t ALTSET;         /**< Channel Primary Alternate Set           */
-  __O  uint32_t ALTCLR;         /**< Channel Primary Alternate Clear         */
-  __IO uint32_t PRIOSET;        /**< Channel Priority Set                    */
-  __O  uint32_t PRIOCLR;        /**< Channel Priority Clear                  */
-  __I  uint32_t _RESERVED0[3];  /**< Reserved                                */
-  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
-  __I  uint32_t _RESERVED1[300];/**< Reserved                                */
-  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
-  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
-  __I  uint32_t _RESERVED2[2];  /**< Reserved                                */
-  __IO uint32_t CHMAP[4];       /**< Channel Map Select 0, 1, 2 and 3        */
-} UDMA_TypeDef;
-
-// USB
-
-/**
- * @brief Watchdog Timer
- */
-typedef struct
-{
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t VALUE;          /**< Value                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t _RESERVED0[256];/**< Reserved                                */
-  __IO uint32_t TEST;           /**< Test                                    */
-  __I  uint32_t _RESERVED1[505];/**< Reserved                                */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-} WDT_TypeDef;
-
-/**
- * @}
- */
-
-/**
- * @addtogroup Peripheral_memorymap
- * @{
- */
-
-#define SYSCTL_BASE     0x400FE000
-#define HIB_BASE        0x400FC000
-#define FLASH_BASE      0x400FD000
-#define EEPROM_BASE     0x400AF000
-#define UDMA_BASE       0x400FF000
-#define GPIOA_APB_BASE  0x40004000
-#define GPIOA_AHB_BASE  0x40058000
-#define GPIOB_APB_BASE  0x40005000
-#define GPIOB_AHB_BASE  0x40059000
-#define GPIOC_APB_BASE  0x40006000
-#define GPIOC_AHB_BASE  0x4005A000
-#define GPIOD_APB_BASE  0x40007000
-#define GPIOD_AHB_BASE  0x4005B000
-#define GPIOE_APB_BASE  0x40024000
-#define GPIOE_AHB_BASE  0x4005C000
-#define GPIOF_APB_BASE  0x40025000
-#define GPIOF_AHB_BASE  0x4005D000
-#define GPIOG_APB_BASE  0x40026000
-#define GPIOG_AHB_BASE  0x4005E000
-#define GPIOH_APB_BASE  0x40027000
-#define GPIOH_AHB_BASE  0x4005F000
-#define GPIOJ_APB_BASE  0x4003D000
-#define GPIOJ_AHB_BASE  0x40060000
-#define GPIOK_AHB_BASE  0x40061000
-#define GPIOL_AHB_BASE  0x40062000
-#define GPIOM_AHB_BASE  0x40063000
-#define GPION_AHB_BASE  0x40064000
-#define GPIOP_AHB_BASE  0x40065000
-#define GPIOQ_AHB_BASE  0x40066000
-#define GPT0_BASE       0x40030000
-#define GPT1_BASE       0x40031000
-#define GPT2_BASE       0x40032000
-#define GPT3_BASE       0x40033000
-#define GPT4_BASE       0x40034000
-#define GPT5_BASE       0x40035000
-#define WGPT0_BASE      0x40036000
-#define WGPT1_BASE      0x40037000
-#define WGPT2_BASE      0x4004C000
-#define WGPT3_BASE      0x4004D000
-#define WGPT4_BASE      0x4004E000
-#define WGPT5_BASE      0x4004F000
-#define WDT0_BASE       0x40000000
-#define WDT1_BASE       0x40001000
-#define ADC0_BASE       0x40038000
-#define ADC1_BASE       0x40039000
-#define UART0_BASE      0x4000C000
-#define UART1_BASE      0x4000D000
-#define UART2_BASE      0x4000E000
-#define UART3_BASE      0x4000F000
-#define UART4_BASE      0x40010000
-#define UART5_BASE      0x40011000
-#define UART6_BASE      0x40012000
-#define UART7_BASE      0x40013000
-#define SSI0_BASE       0x40008000
-#define SSI1_BASE       0x40009000
-#define SSI2_BASE       0x4000A000
-#define SSI3_BASE       0x4000B000
-#define I2C0_BASE       0x40020000
-#define I2C1_BASE       0x40021000
-#define I2C2_BASE       0x40022000
-#define I2C3_BASE       0x40023000
-#define I2C4_BASE       0x40023000
-#define I2C5_BASE       0x40023000
-#define CAN0_BASE       0x40040000
-#define CAN1_BASE       0x40041000
-// usb
-#define ACMP_BASE       0x4003C000
-#define PWM0_BASE       0x40028000
-#define PWM1_BASE       0x40029000
-#define QEI0_BASE       0x4002C000
-#define QEI1_BASE       0x4002D000
-
-/**
- * @}
- */
-
-/** 
- * @addtogroup Peripheral_declaration
- * @{
- */
-
-#define SYSCTL          ((SYSCTL_TypeDef *) SYSCTL_BASE)
-#define HIB             ((HIB_TypeDef *)    HIB_BASE)
-#define FLASH           ((FLASH_TypeDef *)  FLASH_BASE)
-#define EEPROM          ((EEPROM_TypeDef *) EEPROM_BASE)
-#define UDMA            ((UDMA_TypeDef *)   UDMA_BASE)
-#define GPIOA_APB       ((GPIO_TypeDef *)   GPIOA_APB_BASE)
-#define GPIOA_AHB       ((GPIO_TypeDef *)   GPIOA_AHB_BASE)
-#define GPIOB_APB       ((GPIO_TypeDef *)   GPIOB_APB_BASE)
-#define GPIOB_AHB       ((GPIO_TypeDef *)   GPIOB_AHB_BASE)
-#define GPIOC_APB       ((GPIO_TypeDef *)   GPIOC_APB_BASE)
-#define GPIOC_AHB       ((GPIO_TypeDef *)   GPIOC_AHB_BASE)
-#define GPIOD_APB       ((GPIO_TypeDef *)   GPIOD_APB_BASE)
-#define GPIOD_AHB       ((GPIO_TypeDef *)   GPIOD_AHB_BASE)
-#define GPIOE_APB       ((GPIO_TypeDef *)   GPIOE_APB_BASE)
-#define GPIOE_AHB       ((GPIO_TypeDef *)   GPIOE_AHB_BASE)
-#define GPIOF_APB       ((GPIO_TypeDef *)   GPIOF_APB_BASE)
-#define GPIOF_AHB       ((GPIO_TypeDef *)   GPIOF_AHB_BASE)
-#define GPIOG_APB       ((GPIO_TypeDef *)   GPIOG_APB_BASE)
-#define GPIOG_AHB       ((GPIO_TypeDef *)   GPIOG_AHB_BASE)
-#define GPIOH_APB       ((GPIO_TypeDef *)   GPIOH_APB_BASE)
-#define GPIOH_AHB       ((GPIO_TypeDef *)   GPIOH_AHB_BASE)
-#define GPIOJ_APB       ((GPIO_TypeDef *)   GPIOJ_APB_BASE)
-#define GPIOJ_AHB       ((GPIO_TypeDef *)   GPIOJ_AHB_BASE)
-#define GPIOK_AHB       ((GPIO_TypeDef *)   GPIOK_AHB_BASE)
-#define GPIOL_AHB       ((GPIO_TypeDef *)   GPIOL_AHB_BASE)
-#define GPIOM_AHB       ((GPIO_TypeDef *)   GPIOM_AHB_BASE)
-#define GPION_AHB       ((GPIO_TypeDef *)   GPION_AHB_BASE)
-#define GPIOP_AHB       ((GPIO_TypeDef *)   GPIOP_AHB_BASE)
-#define GPIOQ_AHB       ((GPIO_TypeDef *)   GPIOQ_AHB_BASE)
-#define GPT0            ((GPT_TypeDef *)    GPT0_BASE)
-#define GPT1            ((GPT_TypeDef *)    GPT1_BASE)
-#define GPT2            ((GPT_TypeDef *)    GPT2_BASE)
-#define GPT3            ((GPT_TypeDef *)    GPT3_BASE)
-#define GPT4            ((GPT_TypeDef *)    GPT4_BASE)
-#define GPT5            ((GPT_TypeDef *)    GPT5_BASE)
-#define WGPT0           ((GPT_TypeDef *)    WGPT0_BASE)
-#define WGPT1           ((GPT_TypeDef *)    WGPT1_BASE)
-#define WGPT2           ((GPT_TypeDef *)    WGPT2_BASE)
-#define WGPT3           ((GPT_TypeDef *)    WGPT3_BASE)
-#define WGPT4           ((GPT_TypeDef *)    WGPT4_BASE)
-#define WGPT5           ((GPT_TypeDef *)    WGPT5_BASE)
-#define WDT0            ((WDT_TypeDef *)    WDT0_BASE)
-#define WDT1            ((WDT_TypeDef *)    WDT1_BASE)
-#define ADC0            ((ADC_TypeDef*)     ADC0_BASE)
-#define ADC1            ((ADC_TypeDef*)     ADC1_BASE)
-#define UART0           ((UART_TypeDef *)   UART0_BASE)
-#define UART1           ((UART_TypeDef *)   UART1_BASE)
-#define UART2           ((UART_TypeDef *)   UART2_BASE)
-#define UART3           ((UART_TypeDef *)   UART3_BASE)
-#define UART4           ((UART_TypeDef *)   UART4_BASE)
-#define UART5           ((UART_TypeDef *)   UART5_BASE)
-#define UART6           ((UART_TypeDef *)   UART6_BASE)
-#define UART7           ((UART_TypeDef *)   UART7_BASE)
-#define SSI0            ((SSI_TypeDef *)    SSI0_BASE)
-#define SSI1            ((SSI_TypeDef *)    SSI1_BASE)
-#define SSI2            ((SSI_TypeDef *)    SSI2_BASE)
-#define SSI3            ((SSI_TypeDef *)    SSI3_BASE)
-#define I2C0            ((I2C_TypeDef *)    I2C0_BASE)
-#define I2C1            ((I2C_TypeDef *)    I2C1_BASE)
-#define I2C2            ((I2C_TypeDef *)    I2C2_BASE)
-#define I2C3            ((I2C_TypeDef *)    I2C3_BASE)
-#define I2C4            ((I2C_TypeDef *)    I2C4_BASE)
-#define I2C5            ((I2C_TypeDef *)    I2C5_BASE)
-#define CAN0            ((CAN_TypeDef *)    CAN0_BASE)
-#define CAN1            ((CAN_TypeDef *)    CAN1_BASE)
-// usb
-#define ACMP            ((ACMP_TypeDef *)   ACMP_BASE)
-#define PWM0            ((PWM_TypeDef *)    PWM0_BASE)
-#define PWM1            ((PWM_TypeDef *)    PWM1_BASE)
-#define QEI0            ((QEI_TypeDef *)    QEI0_BASE)
-#define QEI1            ((QEI_TypeDef *)    QEI1_BASE)
-
-/**
- * @}
- */
-
-#endif /* __TM4C123x_H */
-
-/**
- * @}
- */
- 
-/**
- * @}
- */
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
deleted file mode 100644
index 5a5f4f2..0000000
--- a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
+++ /dev/null
@@ -1,1131 +0,0 @@
-/*
-    Copyright (C) 2014..2016 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @addtogroup CMSIS
- * @{
- */
-
-/**
- * @addtogroup TM4C129x
- * @{
- */
-
-#ifndef __TM4C129x_H
-#define __TM4C129x_H
-
-/** 
- * @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
-#define __MPU_PRESENT           1       /**< MPU present                     */
-#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
-#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
-#define __FPU_PRESENT           1       /**< FPU present                     */
-
-/**
- * @brief   TM4C129x Interrupt Number Definitions
- */
-typedef enum IRQn
-{
-  /* TODO: check interrupt numbers with tm4c129 device */
-  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
-  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
-  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
-  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
-  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
-  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
-  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
-  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
-  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
-  /***** TM4C129x Specific Interrupt Numbers *********************************/
-  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
-  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
-  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
-  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
-  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
-  UART0_IRQn            = 5,    /**< UART0                                   */
-  UART1_IRQn            = 6,    /**< UART1                                   */
-  SSI0_IRQn             = 7,    /**< SSI0                                    */
-  I2C0_IRQn             = 8,    /**< I2C0                                    */
-  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
-  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
-  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
-  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
-  QEI0_IRQn             = 13,   /**< QEI0                                    */
-  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
-  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
-  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
-  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
-  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
-  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
-  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
-  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
-  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
-  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
-  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
-  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
-  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
-  SYSCON_IRQn           = 28,   /**< System Control                          */
-  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
-  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
-  UART2_IRQn            = 33,   /**< UART2                                   */
-  SSI1_IRQn             = 34,   /**< SSI1                                    */
-  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
-  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
-  I2C1_IRQn             = 37,   /**< I2C1                                    */
-  QEI1_IRQn             = 38,   /**< QEI1                                    */
-  CAN0_IRQn             = 39,   /**< CAN0                                    */
-  CAN1_IRQn             = 40,   /**< CAN1                                    */
-  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
-  USB_IRQn              = 44,   /**< USB                                     */
-  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
-  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
-  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
-  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
-  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
-  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
-  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
-  SSI2_IRQn             = 57,   /**< SSI2                                    */
-  SSI3_IRQn             = 58,   /**< SSI3                                    */
-  UART3_IRQn            = 59,   /**< UART3                                   */
-  UART4_IRQn            = 60,   /**< UART4                                   */
-  UART5_IRQn            = 61,   /**< UART5                                   */
-  UART6_IRQn            = 62,   /**< UART6                                   */
-  UART7_IRQn            = 63,   /**< UART7                                   */
-  I2C2_IRQn             = 68,   /**< I2C2                                    */
-  I2C3_IRQn             = 69,   /**< I2C3                                    */
-  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
-  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
-  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
-  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
-  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
-  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
-  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
-  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
-  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
-  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
-  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
-  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
-  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
-  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
-  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
-  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
-  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
-  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
-  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
-  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
-  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
-  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
-} IRQn_Type;
- 
-/**
- * @}
- */
-
-#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
-#include <stdint.h>
-
-/**
- * @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog Comparator
- */
-typedef struct
-{
-  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __I  uint32_t STAT0;          /**< Status 0                                */
-  __IO uint32_t CTL0;           /**< Control 0                               */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t STAT1;          /**< Status 1                                */
-  __IO uint32_t CTL1;           /**< Control 1                               */
-  __I  uint32_t _RESERVED3[990];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} ACMP_TypeDef;
-
-/**
- * @brief Analog-to-Digital Converter
- */
-typedef struct
-{
-  __IO uint32_t MUX;            /**< Sample Sequence Input Multiplexer
-                                     Select                                  */
-  __IO uint32_t CTL;            /**< Sample Sequence Control                 */
-  __I  uint32_t FIFO;           /**< Sample Sequence Result FIFO             */
-  __I  uint32_t FSTAT;          /**< Sample Sequence FIFO Status             */
-  __IO uint32_t OP;             /**< Sample Sequence Operation               */
-  __IO uint32_t DC;             /**< Sample Sequence Digital Comparator
-                                     Select                                  */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-} ADC_SS_t;
-
-typedef struct
-{
-  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t OSTAT;          /**< Overflow Status                         */
-  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
-  __IO uint32_t USTAT;          /**< Underflow Status                        */
-  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
-  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
-  __IO uint32_t SPC;            /**< Sample Phase Control                    */
-  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t SAC;            /**< Sample Averaging Control                */
-  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and
-                                     Clear                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  ADC_SS_t SS[4];               /**< Sample Sequence 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[784];/**< Reserved */
-  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
-                                     Conditions                              */
-  __I  uint32_t _RESERVED3[63]; /**< Reserved                                */
-  __IO uint32_t DCCTL[8];       /**< Digital Comparator Control 0 - 7        */
-  __I  uint32_t _RESERVED4[8];  /**< Reserved                                */
-  __IO uint32_t DCCMP[8];       /**< Digital Comparator Range 0 - 7          */
-  __I  uint32_t _RESERVED5[88]; /**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __IO uint32_t PC;             /**< Peripheral Configuration                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} ADC_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
-  __IO uint32_t CRQ;            /**< Command Request                         */
-  __IO uint32_t CMSK;           /**< Command Mask                            */
-  __IO uint32_t MSK[2];         /**< Mask 1 and 2                            */
-  __IO uint32_t ARB[2];         /**< Arbitration 1 and 2                     */
-  __IO uint32_t MCTL;           /**< Message Control                         */
-  __IO uint32_t DA[2];          /**< Data A1 and A2                          */
-  __IO uint32_t DB[2];          /**< Data B1 and B2                          */
-  __I  uint32_t _RESERVED0[13]; /**< Reserved                                */
-} CAN_INTERFACE_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t STS;            /**< Status                                  */
-  __I  uint32_t ERR;            /**< Error Counter                           */
-  __IO uint32_t BIT;            /**< Bit Timing                              */
-  __I  uint32_t INT;            /**< Interrupt                               */
-  __IO uint32_t TST;            /**< Test                                    */
-  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  CAN_INTERFACE_t IF[2];        /**< IF1 and IF2                             */
-  __I  uint32_t _RESERVED1[8];  /**< Reserved                                */
-  __I  uint32_t TXRQ[2];        /**< Transmission Request 1 and 2            */
-  __I  uint32_t _RESERVED2[6];  /**< Reserved                                */
-  __I  uint32_t NWDA[2];        /**< New Data 1 and 2                        */
-  __I  uint32_t _RESERVED3[6];  /**< Reserved                                */
-  __I  uint32_t MSGINT[2];      /**< Message 1 and 2 Interrupt Pending       */
-  __I  uint32_t _RESERVED4[6];  /**< Reserved                                */
-  __I  uint32_t MSGVAL[2];      /**< Message 1 and 2 Valid                   */
-} CAN_TypeDef;
-
-/**
- * @brief EEPROM Memory
- */
-typedef struct
-{
-  __IO uint32_t EESIZE;         /**< Size Information                        */
-  __IO uint32_t EEBLOCK;        /**< Current Block                           */
-  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t EERDWR;         /**< Read-Write                              */
-  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
-  __IO uint32_t EEDONE;         /**< Done Status                             */
-  __IO uint32_t EESUPP;         /**< Support Control and Status              */
-  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t EEPROT;         /**< Protection                              */
-  __IO uint32_t EEPASS[3];      /**< Password                                */
-  __IO uint32_t EEINT;          /**< Interrupt                               */
-  __I  uint32_t _RESERVED2[3];  /**< Reserved                                */
-  __IO uint32_t EEHIDE;         /**< Block Hide                              */
-  __I  uint32_t _RESERVED3[11]; /**< Reserved                                */
-  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
-  __I  uint32_t _RESERVED4[975];/**< Reserved                                */
-  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
-} EEPROM_TypeDef;
-
-/**
- * @brief Flash Memory
- */
-typedef struct
-{
-  __IO uint32_t FMA;            /**< Flash Memory Address                    */
-  __IO uint32_t FMD;            /**< Flash Memory Data                       */
-  __IO uint32_t FMC;            /**< Flash Memory Control                    */
-  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
-  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
-  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
-  __I  uint32_t _RESERVED0[2];  /**< Reserved                                */
-  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
-  __I  uint32_t _RESERVED1[3];  /**< Reserved                                */
-  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
-  __I  uint32_t _RESERVED2[51]; /**< Reserved                                */
-  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
-  __I  uint32_t _RESERVED3[943];/**< Reserved                                */
-  __I  uint32_t FSIZE;          /**< Flash Size                              */
-  __I  uint32_t SSIZE;          /**< SRAM Size                               */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
-} FLASH_TypeDef;
-
-
-
-/**
- * @brief General Purpose Input/Outputs
- */
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
-    struct {
-      __I  uint32_t _RESERVED0[255];    /**< Reserved                        */
-      __IO uint32_t DATA;       /**< Data                                    */
-    };
-  };
-  __IO uint32_t DIR;            /**< Direction                               */
-  __IO uint32_t IS;             /**< Interrupt Sense                         */
-  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
-  __IO uint32_t IEV;            /**< Interrupt Event                         */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
-  __I  uint32_t _RESERVED1[55]; /**< Reserved                                */
-  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
-  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
-  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
-  __IO uint32_t ODR;            /**< Open Drain Select                       */
-  __IO uint32_t PUR;            /**< Pull-Up Select                          */
-  __IO uint32_t PDR;            /**< Pull-Down Select                        */
-  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
-  __IO uint32_t DEN;            /**< Digital Enable                          */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-  __IO uint32_t CR;             /**< Commit                                  */
-  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
-  __IO uint32_t PCTL;           /**< Port Control                            */
-  __IO uint32_t ADCCTL;         /**< ADC Control                             */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __IO uint32_t SI;             /**< */
-  __IO uint32_t DR12R;          /**< */
-  __IO uint32_t WAKEPEN;        /**< */
-  __IO uint32_t WAKELVL;        /**< */
-  __IO uint32_t WAKESTAT;       /**< */
-  __I  uint32_t _RESERVED2[669];/**< */
-  __I  uint32_t PP;             /**< */
-  __IO uint32_t PC;             /**< */
-} GPIO_TypeDef;
-
-/**
- * @brief General Purpose Timer
- */
-typedef struct
-{
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t TAMR;           /**< Timer A Mode                            */
-  __IO uint32_t TBMR;           /**< Timer B Mode                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t SYNC;           /**< Synchronize                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t IMR;            /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
-  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
-  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
-  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
-  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
-  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
-  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
-  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
-  __I  uint32_t TAR;            /**< Timer A                                 */
-  __I  uint32_t TBR;            /**< Timer B                                 */
-  __IO uint32_t TAV;            /**< Timer A Value                           */
-  __IO uint32_t TBV;            /**< Timer B Value                           */
-  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
-  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
-  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
-  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
-  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
-  __I  uint32_t _RESERVED1[981];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} GPT_TypeDef;
-
-/**
- * @brief Hibernation Module
- */
-typedef struct
-{
-  __I  uint32_t RTCC;           /**< RTC Counter                             */
-  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __IO uint32_t RTCLD;          /**< RTC Load                                */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __IO uint32_t IC;             /**< Interrupt Clear                         */
-  __IO uint32_t RTCT;           /**< RTC Trim                                */
-  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t DATA;           /**< Data                                    */
-} HIB_TypeDef;
-
-/**
- * @brief Inter-Integrated Circuit
- */
-typedef struct
-{
-  __IO uint32_t MSA;            /**< Master Slave Address                    */
-  __IO uint32_t MCS;            /**< Master Control/Status                   */
-  __IO uint32_t MDR;            /**< Master Data                             */
-  __IO uint32_t MTPR;           /**< Master Timer Period                     */
-  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
-  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
-  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
-  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
-  __IO uint32_t MCR;            /**< Master Configuration                    */
-  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
-  __I  uint32_t _RESERVED0[1];  /**< Reserved                                */
-  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
-  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
-  __I  uint32_t _RESERVED1[497];/**< Reserved                                */
-  __IO uint32_t SOAR;           /**< Slave Own Address                       */
-  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
-  __IO uint32_t SDR;            /**< Slave Data                              */
-  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
-  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
-  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
-  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
-  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
-  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
-  __I  uint32_t _RESERVED2[487];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t PC;             /**< Peripheral Configuration                */
-} I2C_TypeDef;
-
-/*
- * @brief Pulse Width Modulator
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t COUNT;          /**< Counter                                 */
-  __IO uint32_t CMP[2];         /**< Compare A, B                            */
-  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
-  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
-  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
-  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
-  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
-  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
-} PWM_GENERATOR_T;
-
-typedef struct
-{
-  union {
-    __IO uint32_t SEN;          /**< Fault Pin Logic Sense, for GEN 0 and 1  */
-    __I  uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3               */
-  };
-  __IO uint32_t STAT[2];        /**< Fault Status                            */
-  __I  uint32_t _RESERVED1[29]; /**< Reserved                                */
-} PWM_FLT_t;
-
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Master Control                          */
-  __IO uint32_t SYNC;           /**< Time Base Sync                          */
-  __IO uint32_t ENABLE;         /**< Output Enable                           */
-  __IO uint32_t INVERT;         /**< Output Inversion                        */
-  __IO uint32_t FAULT;          /**< Output Fault                            */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-  __I  uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
-  __IO uint32_t ENUPD;          /**< Enable Update                           */
-  __I  uint32_t _RESERVED0[5];  /**< Reserved                                */
-  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
-  __I  uint32_t _RESERVED1[432];/**< Reserved                                */
-  PWM_FLT_t FLT[4];             /**< Fault registers 0, 1, 2 and 3           */
-  __I  uint32_t _RESERVED2[368];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-} PWM_TypeDef;
-
-/**
- * @brief Quadrature Encoder Interface
- */
-typedef struct
-{
-  __IO uint32_t CTL;            /**< Control                                 */
-  __I  uint32_t STAT;           /**< Status                                  */
-  __IO uint32_t POS;            /**< Position                                */
-  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
-  __IO uint32_t LOAD;           /**< Timer Load                              */
-  __I  uint32_t TIME;           /**< Timer                                   */
-  __I  uint32_t COUNT;          /**< Velocity Counter                        */
-  __I  uint32_t SPEED;          /**< Velocity                                */
-  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
-} QEI_TypeDef;
-
-/**
- * @brief Synchronous Serial Interface
- */
-typedef struct
-{
-  __IO uint32_t CR[2];          /**< Control 0, 1                            */
-  __IO uint32_t DR;             /**< Data                                    */
-  __I  uint32_t SR;             /**< Status                                  */
-  __IO uint32_t CPSR;           /**< Clock Prescale                          */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED0[1000];/**< Reserved                               */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} SSI_TypeDef;
-
-/** 
- * @brief System Control
- */
-typedef struct
-{
-  __I  uint32_t DID0;           /**< Device Identification 0                 */
-  __I  uint32_t DID1;           /**< Device Identification 1                 */
-  __I  uint32_t RESERVED0[12];  /**< Reserved                                */
-  __IO uint32_t PBORCTL;        /**< Power-Temp Brown Out Control                 */
-  __I  uint32_t RESERVED1[5];   /**< Reserved                                */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
-  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
-  __IO uint32_t RESC;           /**< Reset Cause                             */
-  __IO uint32_t PWRTC;          /**< Power-Temperature Cause */
-  __IO uint32_t NMIC;           /**< NMI Cause Register */
-  __I  uint32_t RESERVED2[5];   /**< Reserved */
-  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control */
-  __I  uint32_t RESERVED3[12];  /**< Reserved */
-  __IO uint32_t RSCLKCFG;       /**< Run and Sleep Mode Configuration Register */
-  __I  uint32_t RESERVEDx[3];
-  __IO uint32_t MEMTIM0;        /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
-  __I  uint32_t RESERVED4[29];  /**< Reserved */
-  __IO uint32_t ALTCLKCFG;      /**< Alternate Clock Configuration */
-  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
-  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
-  __IO uint32_t DIVSCLK;        /**< Divisor and Source Clock Configuration  */
-  __I  uint32_t SYSPROP;        /**< System Properties                       */
-  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
-  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
-  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
-  __IO uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
-  __IO uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
-  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
-  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
-  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
-  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
-  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
-  __I  uint32_t NVMSTAT;        /**< Non-Volatile Memory Information */
-  __I  uint32_t RESERVED9[4];   /**< Reserved */
-  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
-  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
-  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
-  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
-  __I  uint32_t RESERVED10[2];  /**< Reserved                                */
-  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
-  __I  uint32_t RESERVED11[2];  /**< Reserved */
-  __IO uint32_t RESBEHAVCTL;    /**< Reset Behavior Control Register */
-  __I  uint32_t RESERVED12[6];  /**< Reserved */
-  __IO uint32_t HSSR;           /**< Hardware System Service Request */
-  __I  uint32_t RESERVED[34];   /**< Reserved */
-  __I  uint32_t USBPDS;         /**< USB Power Domain Status */
-  __IO uint32_t USBMPC;         /**< USB Memory Power Control */
-  __I  uint32_t EMACPDS;        /**< Ethernet MAC Power Domain Status */
-  __IO uint32_t EMACMPC;        /**< Ethernet MAC Memory Power Control */
-  __I  uint32_t RESERVED13[2];  /**< Reserved */
-  __I  uint32_t CAN0PDS;        /**< CAN 0 Power Domain Status */
-  __IO uint32_t CAN0MPC;        /**< CAN 0 Memory Power Control */
-  __I  uint32_t CAN1PDS;        /**< CAN 1 Power Domain Status */
-  __IO uint32_t CAN1MPC;        /**< CAN 1 Memory Power Control */
-  __I  uint32_t RESERVED14[22]; /**< Reserved */
-  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
-  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
-  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
-  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
-  __I  uint32_t PPEPI;          /**< EPI Peripheral Present */
-  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
-  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
-  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
-  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
-  __I  uint32_t RESERVED15[1];  /**< Reserved                                */
-  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __I  uint32_t PPEPHY;         /**< Ethernet PHY Peripheral Present */
-  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
-  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
-  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
-  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
-  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
-  __I  uint32_t PPLPC;          /**< Low Pin Count Interface Peripheral Present */
-  __I  uint32_t RESERVED17[1];  /**< Reserved */
-  __I  uint32_t PPPECI;         /**< Platform Environment Control Interface Peripheral Present */
-  __I  uint32_t PPFAN;          /**< Fan Control Peripheral Present */
-  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
-  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
-  __I  uint32_t RESERVED18[4];  /**< Reserved */
-  __I  uint32_t PPRTS;          /**< Remote Temperature Sensor Peripheral Present */
-  __I  uint32_t PPCCM;          /**< CRC Module Peripheral Present */
-  __I  uint32_t RESERVED19[6];  /**< Reserved */
-  __I  uint32_t PPLCD;          /**< LCD Peripheral Present */
-  __I  uint32_t RESERVED20[1];  /**< Reserved */
-  __I  uint32_t PPOWIRE;        /**< 1-Wire Peripheral Present */
-  __I  uint32_t PPEMAC;         /**< Ethernet MAC Peripheral Present */
-  __I  uint32_t PPPRB;          /**< Power Regulator Bus Peripheral Present */
-  __I  uint32_t PPHIM;          /**< Human Interface Master Peripheral Present */
-  __I  uint32_t RESERVED21[86]; /**< Reserved */
-  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
-  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
-  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
-  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
-  __IO uint32_t SREPI;          /**< EPI Software Reset */
-  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
-  __IO uint32_t SRUART;         /**< UART Software Reset                     */
-  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
-  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
-  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
-  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
-  __I  uint32_t RESERVED23[1];  /**< Reserved                                */
-  __IO uint32_t SREPHY;         /**< Ethernet PHY Software Reset */
-  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
-  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
-  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
-  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
-  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
-  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
-  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
-  __I  uint32_t RESERVED25[6];  /**< Reserved */
-  __IO uint32_t SRCCM;          /**< CRC Module Software Reset */
-  __I  uint32_t RESERVED26[9];  /**< Reserved */
-  __IO uint32_t SREMAC;         /**< Ethernet MAC Software Reset */
-  __I  uint32_t RESERVED27[24]; /**< Reserved                                */
-  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCEPI;        /**< EPI Run Mode Clock Gating Control */
-  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
-  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED28[1];  /**< Reserved                                */
-  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED29[1];  /**< Reserved                                */
-  __IO uint32_t RCGCEPHY;       /**< Ethernet PHY Run Mode Clock Gating Control */
-  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
-  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
-  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
-  __I  uint32_t RESERVED30[4];  /**< Reserved                                */
-  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
-  __I  uint32_t RESERVED31[6];  /**< Reserved */
-  __IO uint32_t RCGCCCM;        /**< CRC Module Run Mode Clock Gating Control */
-  __I  uint32_t RESERVED32[9];  /**< Reserved */
-  __IO uint32_t RCGCEMAC;       /**< Ethernet MAC Run Mode Clock Gating Control */
-  __I  uint32_t RESERVED33[24]; /**< Reserved */
-  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCEPI;        /**< EPI Sleep Mode Clock Gating Control */
-  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED34[1];  /**< Reserved                                */
-  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED35[1];  /**< Reserved                                */
-  __IO uint32_t SCGCEPHY;       /**< Ethernet PHY Sleep Mode Clock Gating Control */
-  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
-  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
-  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
-  __I  uint32_t RESERVED36[4];  /**< Reserved                                */
-  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
-  __I  uint32_t RESERVED37[6];  /**< Reserved */
-  __IO uint32_t SCGCCCM;        /**< CRC Module Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED38[9];  /**< Reserved */
-  __IO uint32_t SCGCEMAC;       /**< Ethernet MAC Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED39[24]; /**< Reserved                                */
-  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCEPI;        /**< EPI Deep-Sleep Mode Clock Gating Control */
-  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED40[1];  /**< Reserved                                */
-  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED41[1];  /**< Reserved                                */
-  __IO uint32_t DCGCEPHY;       /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
-  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
-  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
-  __I  uint32_t RESERVED42[4];  /**< Reserved                                */
-  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
-                                     Control                                 */
-  __I  uint32_t RESERVED43[6];  /**< Reserved */
-  __IO uint32_t DCGCCCM;        /**< CRC Module Deep-Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED44[9];  /**< Reserved */
-  __IO uint32_t DCGCEMAC;       /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
-  __I  uint32_t RESERVED45[24]; /**< Reserved                                */
-  __IO uint32_t PCWD;           /**< Watchdog Timer Power Control       */
-  __IO uint32_t PCTIMER;        /**< 16/32-Bit General-Purpose Timer Power Control       */
-  __IO uint32_t PCGPIO;         /**< General-Purpose Input/Output Power Control      */
-  __IO uint32_t PCDMA;          /**< Micro Direct Memory Access Power Control      */
-  __IO uint32_t PCEPI;          /**< External Peripheral Interface Power Control */
-  __IO uint32_t PCHIB;          /**< Hibernation Power Control       */
-  __IO uint32_t PCUART;         /**< Universal Asynchronous Receiver/Transmitter Power Control                   */
-  __IO uint32_t PCSSI;          /**< Synchronous Serial Interface Power Control       */
-  __IO uint32_t PCI2C;          /**< Inter-Integrated Circuit Power Control       */
-  __I  uint32_t RESERVED46[1];  /**< Reserved                                */
-  __IO uint32_t PCUSB;          /**< Universal Serial Bus Power Control       */
-  __I  uint32_t RESERVED47[1];  /**< Reserved                                */
-  __IO uint32_t PCEPHY;         /**< Ethernet PHY Power Control */
-  __IO uint32_t PCCAN;          /**< Controller Area Network Power Control       */
-  __IO uint32_t PCADC;          /**< Analog-to-Digital Converter Power Control       */
-  __IO uint32_t PCACMP;         /**< Analog Comparator Power Control      */
-  __IO uint32_t PCPWM;          /**< Pulse Width Modulator Power Control       */
-  __IO uint32_t PCQEI;          /**< Quadrature Encoder Interface Power Control       */
-  __I  uint32_t RESERVED48[4];  /**< Reserved                                */
-  __IO uint32_t PCEEPROM;       /**< EEPROM Power Control    */
-  __I  uint32_t RESERVED49[6];  /**< Reserved */
-  __IO uint32_t PCCCM;          /**< CRC Module Power Control */
-  __I  uint32_t RESERVED50[9];  /**< Reserved */
-  __IO uint32_t PCEMAC;         /**< Ethernet MAC Power Control */
-  __I  uint32_t RESERVED51[24]; /**< Reserved */
-  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
-  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
-  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
-  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
-  __IO uint32_t PREPI;          /**< EPI Peripheral Ready                                */
-  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
-  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
-  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
-  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
-  __I  uint32_t RESERVED52[1];  /**< Reserved                                */
-  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
-  __I  uint32_t RESERVED53[1];  /**< Reserved                                */
-  __IO uint32_t PREPHY;         /**< Ethernet PHY Peripheral Ready */
-  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
-  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
-  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
-  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
-  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
-  __I  uint32_t RESERVED54[4];  /**< Reserved                                */
-  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
-  __I  uint32_t RESERVED55[6];  /**< Reserved */
-  __IO uint32_t PRCCM;          /**< CRC Module Peripheral Ready               */
-  __I  uint32_t RESERVED56[9];  /**< Reserved */
-  __IO uint32_t PREMAC;         /**< Ethernet MAC Peripheral Ready */
-} SYSCTL_TypeDef;
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter
- */
-typedef struct
-{
-  __IO uint32_t DR;             /**< Data                                    */
-  union  {
-    __I  uint32_t RSR;          /**< Receive Status                          */
-    __O  uint32_t ECR;          /**< Error Clear                             */
-  };
-  __I  uint32_t _RESERVED0[4];  /**< Reserved                                */
-  __I  uint32_t FR;             /**< Flag                                    */
-  __I  uint32_t _RESERVED1[1];  /**< Reserved                                */
-  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
-  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
-  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
-  __IO uint32_t LCRH;           /**< Line Control                            */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __O uint32_t ICR;             /**< Interrupt Clear                         */
-  __IO uint32_t DMACTL;         /**< DMA Control                             */
-  __I  uint32_t _RESERVED2[22]; /**< Reserved                                */
-  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
-  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
-  __I  uint32_t _RESERVED3[965];/**< Reserved                                */
-  __I  uint32_t PP;             /**< Peripheral Properties                   */
-  __I  uint32_t _RESERVED4[1];  /**< Reserved                                */
-  __IO uint32_t CC;             /**< Clock Configuration                     */
-} UART_TypeDef;
-
-/**
- * @brief Micro Direct Memory Access
- */
-typedef struct
-{
-  __IO uint32_t SET;            /**< Set                                     */
-  __O  uint32_t CLR;            /**< Clear                                   */
-} UDMA_SC_t;
-
-typedef struct
-{
-  __IO uint32_t STAT;           /**< Status                                  */
-  __O  uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
-  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
-  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
-  __O  uint32_t SWREQ;          /**< Channel Software Request                */
-  UDMA_SC_t USEBURST;           /**< Channel Useburst registers              */
-  UDMA_SC_t REQMASK;            /**< Channel Request Mask registers          */
-  UDMA_SC_t ENA;                /**< Channel Enable registers                */
-  UDMA_SC_t ALT;                /**< Channel Primary Alternate registers     */
-  UDMA_SC_t PRIO;               /**< Channel Priority registers              */
-  __I  uint32_t _RESERVED0[3];  /**< Reserved                                */
-  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
-  __I  uint32_t _RESERVED1[300];/**< Reserved                                */
-  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
-  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
-  __I  uint32_t _RESERVED2[2];  /**< Reserved                                */
-  __IO uint32_t CHMAP[4];       /**< Channel Map Select 0, 1, 2 and 3        */
-} UDMA_TypeDef;
-
-// USB
-
-/**
- * @brief Watchdog Timer
- */
-typedef struct
-{
-  __IO uint32_t LOAD;           /**< Load                                    */
-  __I  uint32_t VALUE;          /**< Value                                   */
-  __IO uint32_t CTL;            /**< Control                                 */
-  __O  uint32_t ICR;            /**< Interrupt Clear                         */
-  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
-  __I  uint32_t _RESERVED0[256];/**< Reserved                                */
-  __IO uint32_t TEST;           /**< Test                                    */
-  __I  uint32_t _RESERVED1[505];/**< Reserved                                */
-  __IO uint32_t LOCK;           /**< Lock                                    */
-} WDG_TypeDef;
-
-/**
- * @brief   Ethernet peripheral
- */
-typedef struct {
-  __IO uint32_t CFG;            /**< Configuration                           */
-  __IO uint32_t FRAMEFLTR;      /**< Frame Filter                            */
-  __IO uint32_t HASHTBLH;       /**< Hash Table High                         */
-  __IO uint32_t HASHTBLL;       /**< Hash Table Low                          */
-  __IO uint32_t MIIADDR;        /**< MII Address                             */
-  __IO uint32_t MIIDATA;        /**< MII Data Register                       */
-  __IO uint32_t FLOWCTL;        /**< Flow Control                            */
-  __IO uint32_t VLANTG;         /**< VLAN Tag                                */
-  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
-  __IO uint32_t STATUS;         /**< Status                                  */
-  __IO uint32_t RWUFF;          /**< Remote Wake-Up Frame Filter             */
-  __IO uint32_t PMTCTLSTAT;     /**< PMT Control and Status Register         */
-  __I  uint32_t RESERVED1[2];   /**< Reserved                                */
-  __IO uint32_t RIS;            /**< Raw Interrupt Status                    */
-  __IO uint32_t IM;             /**< Interrupt Mask                          */
-  __IO uint32_t ADDR0H;         /**< Address 0 High                          */
-  __IO uint32_t ADDR0L;         /**< Address 0 Low Register                  */
-  __IO uint32_t ADDR1H;         /**< Address 1 High                          */
-  __IO uint32_t ADDR1L;         /**< Address 1 Low                           */
-  __IO uint32_t ADDR2H;         /**< Address 2 High                          */
-  __IO uint32_t ADDR2L;         /**< Address 2 Low                           */
-  __IO uint32_t ADDR3H;         /**< Address 3 High                          */
-  __IO uint32_t ADDR3L;         /**< Address 3 Low                           */
-  __I  uint32_t RESERVED2[31];  /**< Reserved                                */
-  __IO uint32_t WDOGTO;         /**< Watchdog Timeout                        */
-  __I  uint32_t RESERVED3[8];   /**< Reserved                                */
-  __IO uint32_t MMCCTRL;        /**< MMC Control                             */
-  __IO uint32_t MMCRXRIS;       /**< MMC Receive Raw Interrupt Status        */
-  __IO uint32_t MMCTXRIS;       /**< MMC Transmit Raw Interrupt Status       */
-  __IO uint32_t MMCRXIM;        /**< MMC Receive Interrupt Mask              */
-  __IO uint32_t MMCTXIM;        /**< MMC Transmit Interrupt Mask             */
-  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
-  __IO uint32_t TXCNTGB;        /**< Transmit Frame Count for Good and Bad
-                                     Frames                                  */
-  __I  uint32_t RESERVED5[12];  /**< Reserved                                */
-  __IO uint32_t TXCNTSCOL;      /**< Transmit Frame Count for Frames
-                                     Transmitted after Single Collision      */
-  __IO uint32_t TXCNTMCOL;      /**< Transmit Frame Count for Frames
-                                     Transmitted after Multiple Collisions   */
-  __I  uint32_t RESERVED6[4];   /**< Reserved                                */
-  __IO uint32_t TXOCTCNTG;      /**< Transmit Octet Count Good               */
-  __I  uint32_t RESERVED7[6];   /**< Reserved                                */
-  __IO uint32_t RXCNTGB;        /**< Receive Frame Count for Good and Bad
-                                     Frames                                  */
-  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
-  __IO uint32_t RXCNTCRCERR;    /**< Receive Frame Count for CRC Error Frames*/
-  __IO uint32_t RXCNTALGNERR;   /**< Receive Frame Count for Alignment Error
-                                     Frames                                  */
-  __I  uint32_t RESERVED9[10];  /**< Reserved                                */
-  __IO uint32_t RXCNTGUNI;      /**< Receive Frame Count for Good Unicast
-                                     Frames                                  */
-  __I  uint32_t RESERVED10[239];/**< Reserved                                */
-  __IO uint32_t VLNINCREP;      /**< VLAN Tag Inclusion or Replacement       */
-  __IO uint32_t VLANHASH;       /**< VLAN Hash Table                         */
-  __I  uint32_t RESERVED11[93]; /**< Reserved                                */
-  __IO uint32_t TIMSTCTRL;      /**< Timestamp Control                       */
-  __IO uint32_t SUBSECINC;      /**< Sub-Second Increment                    */
-  __IO uint32_t TIMSEC;         /**< System Time - Seconds                   */
-  __IO uint32_t TIMNANO;        /**< System Time - Nanoseconds               */
-  __IO uint32_t TIMSECU;        /**< System Time - Seconds Update            */
-  __IO uint32_t TIMNANOU;       /**< System Time - Nanoseconds Update        */
-  __IO uint32_t TIMADD;         /**< Timestamp Addend                        */
-  __IO uint32_t TARGSEC;        /**< Target Time Seconds                     */
-  __IO uint32_t TARGNANO;       /**< Target Time Nanoseconds                 */
-  __IO uint32_t HWORDSEC;       /**< System Time-Higher Word Seconds         */
-  __IO uint32_t TIMSTAT;        /**< Timestamp Status                        */
-  __IO uint32_t PPSCTRL;        /**< PPS Control                             */
-  __I  uint32_t RESERVED12[12]; /**< Reserved                                */
-  __IO uint32_t PPS0INTVL;      /**< PPS0 Interval                           */
-  __IO uint32_t PPS0WIDTH;      /**< PPS0 Width                              */
-  __I  uint32_t RESERVED13[294];/**< Reserved                                */
-  __IO uint32_t DMABUSMOD;      /**< DMA Bus Mode                            */
-  __O  uint32_t TXPOLLD;        /**< Transmit Poll Demand                    */
-  __O  uint32_t RXPOLLD;        /**< Receive Poll Demand                     */
-  __IO uint32_t RXDLADDR;       /**< Receive Descriptor List Address         */
-  __IO uint32_t TXDLADDR;       /**< Transmit Descriptor List Address        */
-  __IO uint32_t DMARIS;         /**< DMA Interrupt Status                    */
-  __IO uint32_t DMAOPMODE;      /**< DMA Operation Mode                      */
-  __IO uint32_t DMAIM;          /**< DMA Interrupt Mask Register             */
-  __IO uint32_t MFBOC;          /**< Missed Frame and Buffer Overflow Counter*/
-  __IO uint32_t RXINTWDT;       /**< Receive Interrupt Watchdog Timer        */
-  __I  uint32_t RESERVED14[8];  /**< Reserved                                */
-  __IO uint32_t HOSTXDESC;      /**< Current Host Transmit Descriptor        */
-  __IO uint32_t HOSRXDESC;      /**< Current Host Receive Descriptor         */
-  __IO uint32_t HOSTXBA;        /**< Current Host Transmit Buffer Address    */
-  __IO uint32_t HOSRXBA;        /**< Current Host Receive Buffer Address     */
-  __I  uint32_t RESERVED15[218];/**< Reserved                                */
-  __IO uint32_t PP;             /**< Peripheral Property Register            */
-  __IO uint32_t PC;             /**< Peripheral Configuration Register       */
-  __IO uint32_t CC;             /**< Clock Configuration Register            */
-  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
-  __I  uint32_t PHYRIS;         /**< PHY Raw Interrupt Status                */
-  __IO uint32_t PHYIM;          /**< PHY Interrupt Mask                      */
-  __IO uint32_t PHYMISC;        /**< PHY Masked Interrupt Status and Clear   */
-} ETH_TypeDef;
-
-/**
- * @}
- */
-
-/**
- * @addtogroup Peripheral_memorymap
- * @{
- */
-
-#define SYSCTL_BASE 0x400FE000
-#define HIB_BASE    0x400FC000
-#define FLASH_BASE  0x400FD000
-#define EEPROM_BASE 0x400AF000
-#define UDMA_BASE   0x400FF000
-#define GPIOA_BASE  0x40058000
-#define GPIOB_BASE  0x40059000
-#define GPIOC_BASE  0x4005A000
-#define GPIOD_BASE  0x4005B000
-#define GPIOE_BASE  0x4005C000
-#define GPIOF_BASE  0x4005D000
-#define GPIOG_BASE  0x4005E000
-#define GPIOH_BASE  0x4005F000
-#define GPIOJ_BASE  0x40060000
-#define GPIOK_BASE  0x40061000
-#define GPIOL_BASE  0x40062000
-#define GPIOM_BASE  0x40063000
-#define GPION_BASE  0x40064000
-#define GPIOP_BASE  0x40065000
-#define GPIOQ_BASE  0x40066000
-#define GPIOR_BASE  0x40067000
-#define GPIOS_BASE  0x40068000
-#define GPIOT_BASE  0x40069000
-#define GPT0_BASE   0x40030000
-#define GPT1_BASE   0x40031000
-#define GPT2_BASE   0x40032000
-#define GPT3_BASE   0x40033000
-#define GPT4_BASE   0x40034000
-#define GPT5_BASE   0x40035000
-#define GPT6_BASE   0x400E0000
-#define GPT7_BASE   0x400E1000
-#define WDT0_BASE   0x40000000
-#define WDT1_BASE   0x40001000
-#define ADC0_BASE   0x40038000
-#define ADC1_BASE   0x40039000
-#define UART0_BASE  0x4000C000
-#define UART1_BASE  0x4000D000
-#define UART2_BASE  0x4000E000
-#define UART3_BASE  0x4000F000
-#define UART4_BASE  0x40010000
-#define UART5_BASE  0x40011000
-#define UART6_BASE  0x40012000
-#define UART7_BASE  0x40013000
-#define SSI0_BASE   0x40008000
-#define SSI1_BASE   0x40009000
-#define SSI2_BASE   0x4000A000
-#define SSI3_BASE   0x4000B000
-#define I2C0_BASE   0x40020000
-#define I2C1_BASE   0x40021000
-#define I2C2_BASE   0x40022000
-#define I2C3_BASE   0x40023000
-#define I2C4_BASE   0x400C0000
-#define I2C5_BASE   0x400C1000
-#define I2C6_BASE   0x400C2000
-#define I2C7_BASE   0x400C3000
-#define I2C8_BASE   0x400B8000
-#define I2C9_BASE   0x400B9000
-#define CAN0_BASE   0x40040000
-#define CAN1_BASE   0x40041000
-// usb
-#define ACMP_BASE   0x4003C000
-#define PWM0_BASE   0x40028000
-#define QEI0_BASE   0x4002C000
-#define QEI1_BASE   0x4002D000
-
-#define ETH_BASE    0x400EC000
-
-/**
- * @}
- */
-
-/** 
- * @addtogroup Peripheral_declaration
- * @{
- */
-
-#define SYSCTL  ((SYSCTL_TypeDef *) SYSCTL_BASE)
-#define HIB     ((HIB_TypeDef *)    HIB_BASE)
-#define FLASH   ((FLASH_TypeDef *)  FLASH_BASE)
-#define EEPROM  ((EEPROM_TypeDef *) EEPROM_BASE)
-#define UDMA    ((UDMA_TypeDef *)   UDMA_BASE)										
-#define GPIOA   ((GPIO_TypeDef *)   GPIOA_BASE)
-#define GPIOB   ((GPIO_TypeDef *)   GPIOB_BASE)
-#define GPIOC   ((GPIO_TypeDef *)   GPIOC_BASE)
-#define GPIOD   ((GPIO_TypeDef *)   GPIOD_BASE)
-#define GPIOE   ((GPIO_TypeDef *)   GPIOE_BASE)
-#define GPIOF   ((GPIO_TypeDef *)   GPIOF_BASE)
-#define GPIOG   ((GPIO_TypeDef *)   GPIOG_BASE)
-#define GPIOH   ((GPIO_TypeDef *)   GPIOH_BASE)
-#define GPIOJ   ((GPIO_TypeDef *)   GPIOJ_BASE)
-#define GPIOK   ((GPIO_TypeDef *)   GPIOK_BASE)
-#define GPIOL   ((GPIO_TypeDef *)   GPIOL_BASE)
-#define GPIOM   ((GPIO_TypeDef *)   GPIOM_BASE)
-#define GPION   ((GPIO_TypeDef *)   GPION_BASE)
-#define GPIOP   ((GPIO_TypeDef *)   GPIOP_BASE)
-#define GPIOQ   ((GPIO_TypeDef *)   GPIOQ_BASE)
-#define GPIOR   ((GPIO_TypeDef *)   GPIOR_BASE)
-#define GPIOS   ((GPIO_TypeDef *)   GPIOS_BASE)
-#define GPIOT   ((GPIO_TypeDef *)   GPIOT_BASE)
-#define GPT0    ((GPT_TypeDef *)    GPT0_BASE)
-#define GPT1    ((GPT_TypeDef *)    GPT1_BASE)
-#define GPT2    ((GPT_TypeDef *)    GPT2_BASE)
-#define GPT3    ((GPT_TypeDef *)    GPT3_BASE)
-#define GPT4    ((GPT_TypeDef *)    GPT4_BASE)
-#define GPT5    ((GPT_TypeDef *)    GPT5_BASE)
-#define GPT6    ((GPT_TypeDef *)    GPT6_BASE)
-#define GPT7    ((GPT_TypeDef *)    GPT7_BASE)
-#define WDT0    ((WDT_TypeDef *)    WDT0_BASE)
-#define WDT1    ((WDT_TypeDef *)    WDT1_BASE)
-#define ADC0    ((ADC_TypeDef*)     ADC0_BASE)
-#define ADC1    ((ADC_TypeDef*)     ADC1_BASE)
-#define UART0   ((UART_TypeDef *)   UART0_BASE)
-#define UART1   ((UART_TypeDef *)   UART1_BASE)
-#define UART2   ((UART_TypeDef *)   UART2_BASE)
-#define UART3   ((UART_TypeDef *)   UART3_BASE)
-#define UART4   ((UART_TypeDef *)   UART4_BASE)
-#define UART5   ((UART_TypeDef *)   UART5_BASE)
-#define UART6   ((UART_TypeDef *)   UART6_BASE)
-#define UART7   ((UART_TypeDef *)   UART7_BASE)
-#define SSI0    ((SSI_TypeDef *)    SSI0_BASE)
-#define SSI1    ((SSI_TypeDef *)    SSI1_BASE)
-#define SSI2    ((SSI_TypeDef *)    SSI2_BASE)
-#define SSI3    ((SSI_TypeDef *)    SSI3_BASE)
-#define I2C0    ((I2C_TypeDef *)    I2C0_BASE)
-#define I2C1    ((I2C_TypeDef *)    I2C1_BASE)
-#define I2C2    ((I2C_TypeDef *)    I2C2_BASE)
-#define I2C3    ((I2C_TypeDef *)    I2C3_BASE)
-#define I2C4    ((I2C_TypeDef *)    I2C4_BASE)
-#define I2C5    ((I2C_TypeDef *)    I2C5_BASE)
-#define I2C6    ((I2C_TypeDef *)    I2C6_BASE)
-#define I2C7    ((I2C_TypeDef *)    I2C7_BASE)
-#define I2C8    ((I2C_TypeDef *)    I2C8_BASE)
-#define I2C9    ((I2C_TypeDef *)    I2C9_BASE)
-#define CAN0    ((CAN_TypeDef *)    CAN0_BASE)
-#define CAN1    ((CAN_TypeDef *)    CAN1_BASE)
-// usb
-#define ACMP    ((ACMP_TypeDef *)   ACMP_BASE)
-#define PWM0    ((PWM_TypeDef *)    PWM0_BASE)
-#define QEI0    ((QEI_TypeDef *)    QEI0_BASE)
-#define QEI1    ((QEI_TypeDef *)    QEI1_BASE)
-
-#define ETH     ((ETH_TypeDef *)  ETH_BASE)
-
-/**
- * @}
- */
-
-#endif /* __TM4C129x_H */
-
-/**
- * @}
- */
- 
-/**
- * @}
- */
-- 
cgit v1.2.3


From f6f6bf3918d0534606d5b9ecb48f22624e9369c0 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Mon, 21 Nov 2016 22:25:54 +0100
Subject: Fixed incorrect type used for line field in led_config structures.

---
 demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c | 2 +-
 demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
index 6522049..5b7e12c 100644
--- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
+++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
@@ -20,7 +20,7 @@
 
 typedef struct led_config
 {
-  ioportid_t line;
+  ioline_t line;
   uint32_t sleep;
 } led_config_t;
 
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
index 968a8e5..ef3957f 100644
--- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
@@ -20,7 +20,7 @@
 
 typedef struct led_config
 {
-  ioportid_t line;
+  ioline_t line;
   uint32_t sleep;
 } led_config_t;
 
-- 
cgit v1.2.3