From ac8960f1a83ea19645ca969e6c525defd8f47ff7 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Tue, 22 Mar 2016 20:14:43 +0000 Subject: [KINETIS] Update demos (for HAL changes). --- demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h') diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h index 6189709..44d2e79 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h @@ -31,7 +31,7 @@ /* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */ #if 1 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE -#define KINETIS_XTAL_FREQUENCY 8000000UL +#define KINETIS_PLLCLK_FREQUENCY 96000000UL #define KINETIS_SYSCLK_FREQUENCY 48000000UL #endif @@ -41,28 +41,35 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */ +#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY +#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2 #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ -- cgit v1.2.3