From b67ecdfeca2d1d5289e4c9b577a1940cf8702ab3 Mon Sep 17 00:00:00 2001 From: Fabio Utzig Date: Mon, 7 Mar 2016 12:33:00 -0300 Subject: [KINETIS] Move from main repo to contrib --- demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h | 74 ++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h (limited to 'demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h') diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h new file mode 100644 index 0000000..6189709 --- /dev/null +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h @@ -0,0 +1,74 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +#define K20x_MCUCONF + +/* + * HAL driver system settings. + */ + +/* Select the MCU clocking mode below by enabling the appropriate block. */ + +/* Enable clock initialization by HAL */ +#define KINETIS_NO_INIT FALSE + +/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */ +#if 1 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE +#define KINETIS_XTAL_FREQUENCY 8000000UL +#define KINETIS_SYSCLK_FREQUENCY 48000000UL +#endif + +/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */ +#if 0 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ +#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#endif /* 0 */ + +/* FEE mode - 24 MHz with external 32.768 kHz crystal */ +#if 0 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ +#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ +#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ +#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#endif /* 0 */ + +/* FEE mode - 48 MHz */ +#if 0 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ +#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#endif /* 0 */ + +/* + * SERIAL driver system settings. + */ +#define KINETIS_SERIAL_USE_UART0 TRUE + +#endif /* _MCUCONF_H_ */ -- cgit v1.2.3