From ac8960f1a83ea19645ca969e6c525defd8f47ff7 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Tue, 22 Mar 2016 20:14:43 +0000 Subject: [KINETIS] Update demos (for HAL changes). --- demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h | 39 +++++++++++++++----------------- 1 file changed, 18 insertions(+), 21 deletions(-) (limited to 'demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h') diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h index 3b77632..d4aa072 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h @@ -17,20 +17,6 @@ #ifndef _MCUCONF_H_ #define _MCUCONF_H_ -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - #define KL2x_MCUCONF /* @@ -38,11 +24,23 @@ */ /* Select the MCU clocking mode below by enabling the appropriate block. */ +/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */ -/* FEI mode */ +/* PEE mode - 48MHz system clock driven by external crystal. */ +#if 1 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE +#define KINETIS_PLLCLK_FREQUENCY 96000000UL +#define KINETIS_SYSCLK_FREQUENCY 48000000UL +#endif + +/* FEI mode - ~24MHz */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI -#define KINETIS_SYSCLK_FREQUENCY 21000000UL +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ +#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */ #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ @@ -50,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ @@ -63,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ -- cgit v1.2.3