From ac8960f1a83ea19645ca969e6c525defd8f47ff7 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Tue, 22 Mar 2016 20:14:43 +0000 Subject: [KINETIS] Update demos (for HAL changes). --- demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile | 2 +- demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h | 23 +++++++++------ demos/KINETIS/RT-FREEDOM-K20D50M/Makefile | 2 +- demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h | 19 +++++++++---- demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile | 4 +-- demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h | 25 ++++++++++++----- demos/KINETIS/RT-FREEDOM-KL25Z/Makefile | 4 +-- demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h | 39 ++++++++++++-------------- demos/KINETIS/RT-MCHCK-K20-GPT/Makefile | 9 ++++-- demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h | 19 ++++++++----- demos/KINETIS/RT-MCHCK-K20-SPI/Makefile | 9 ++++-- demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h | 17 +++++++---- demos/KINETIS/RT-TEENSY3/Makefile | 2 +- demos/KINETIS/RT-TEENSY3/main.c | 2 +- demos/KINETIS/RT-TEENSY3/mcuconf.h | 30 +++++++++++++++----- 15 files changed, 131 insertions(+), 75 deletions(-) (limited to 'demos') diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile index be132f5..1453c5e 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile +++ b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h index 198a03d..4a1adfc 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h @@ -25,13 +25,13 @@ /* Select the MCU clocking mode below by enabling the appropriate block. */ -/* Disable all clock intialization */ +/* Enable clock initialization by HAL */ #define KINETIS_NO_INIT FALSE -/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */ +/* PEE mode - external (8 MHz) crystal with PLL for 48 MHz core/system clock. */ #if 1 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE -#define KINETIS_XTAL_FREQUENCY 8000000UL +#define KINETIS_PLLCLK_FREQUENCY 96000000UL #define KINETIS_SYSCLK_FREQUENCY 48000000UL #endif @@ -41,28 +41,35 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */ +#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY +#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2 #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile b/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile index be132f5..1453c5e 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h index 6189709..44d2e79 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h @@ -31,7 +31,7 @@ /* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */ #if 1 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE -#define KINETIS_XTAL_FREQUENCY 8000000UL +#define KINETIS_PLLCLK_FREQUENCY 96000000UL #define KINETIS_SYSCLK_FREQUENCY 48000000UL #endif @@ -41,28 +41,35 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */ +#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY +#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2 #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile index eb54d34..cb575fb 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile +++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile @@ -84,7 +84,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk @@ -97,7 +97,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/KL25Z128.ld +LDSCRIPT = $(STARTUPLD)/MKL2xZ128.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h index da7ba95..9118e7b 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h @@ -24,11 +24,23 @@ */ /* Select the MCU clocking mode below by enabling the appropriate block. */ +/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */ -/* FEI mode */ +/* PEE mode - 48MHz system clock driven by external crystal. */ +#if 1 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE +#define KINETIS_PLLCLK_FREQUENCY 96000000UL +#define KINETIS_SYSCLK_FREQUENCY 48000000UL +#endif + +/* FEI mode - ~24MHz */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI -#define KINETIS_SYSCLK_FREQUENCY 21000000UL +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ +#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */ #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ @@ -36,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ @@ -49,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile b/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile index eb54d34..cb575fb 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile +++ b/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile @@ -84,7 +84,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk @@ -97,7 +97,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/KL25Z128.ld +LDSCRIPT = $(STARTUPLD)/MKL2xZ128.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h index 3b77632..d4aa072 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h @@ -17,20 +17,6 @@ #ifndef _MCUCONF_H_ #define _MCUCONF_H_ -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - #define KL2x_MCUCONF /* @@ -38,11 +24,23 @@ */ /* Select the MCU clocking mode below by enabling the appropriate block. */ +/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */ -/* FEI mode */ +/* PEE mode - 48MHz system clock driven by external crystal. */ +#if 1 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE +#define KINETIS_PLLCLK_FREQUENCY 96000000UL +#define KINETIS_SYSCLK_FREQUENCY 48000000UL +#endif + +/* FEI mode - ~24MHz */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI -#define KINETIS_SYSCLK_FREQUENCY 21000000UL +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ +#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */ #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ @@ -50,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ @@ -63,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ diff --git a/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile b/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile index 34796ce..e38ba95 100644 --- a/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile +++ b/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk @@ -102,7 +102,8 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/MK20DX128.ld +# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader +LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -196,7 +197,9 @@ CPPWARN = -Wall -Wextra -Wundef # # List all user C define here, like -D_DEBUG=1 -UDEFS = +# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader, +# 0xc00 for a 3k bootloader +UDEFS = -DCORTEX_VTOR_INIT=0x00001000 # Define ASM defines here UADEFS = diff --git a/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h index cc4b581..eace87f 100644 --- a/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h +++ b/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h @@ -32,27 +32,34 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 +#define KINETIS_CLKDIV1_OUTDIV2 2 +#define KINETIS_CLKDIV1_OUTDIV4 2 +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV2) +#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV4) /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ @@ -72,7 +79,5 @@ */ #define KINETIS_GPT_USE_PIT0 TRUE #define KINETIS_GPT_PIT0_IRQ_PRIORITY 8 -/* TODO: Move this to a KINETIS registry */ -#define KINETIS_HAS_PIT0 TRUE #endif /* _MCUCONF_H_ */ diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile index 34796ce..e38ba95 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk @@ -102,7 +102,8 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/MK20DX128.ld +# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader +LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -196,7 +197,9 @@ CPPWARN = -Wall -Wextra -Wundef # # List all user C define here, like -D_DEBUG=1 -UDEFS = +# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader, +# 0xc00 for a 3k bootloader +UDEFS = -DCORTEX_VTOR_INIT=0x00001000 # Define ASM defines here UADEFS = diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h index 70b86cf..81cd6cc 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h @@ -32,27 +32,34 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 +#define KINETIS_CLKDIV1_OUTDIV2 2 +#define KINETIS_CLKDIV1_OUTDIV4 2 +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV2) +#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV4) /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ diff --git a/demos/KINETIS/RT-TEENSY3/Makefile b/demos/KINETIS/RT-TEENSY3/Makefile index 44ad3b4..36145ce 100644 --- a/demos/KINETIS/RT-TEENSY3/Makefile +++ b/demos/KINETIS/RT-TEENSY3/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk diff --git a/demos/KINETIS/RT-TEENSY3/main.c b/demos/KINETIS/RT-TEENSY3/main.c index 591bd0f..ebeb637 100644 --- a/demos/KINETIS/RT-TEENSY3/main.c +++ b/demos/KINETIS/RT-TEENSY3/main.c @@ -27,7 +27,7 @@ static THD_FUNCTION(Thread1, arg) { (void)arg; chRegSetThreadName("LEDBlinker"); while (true) { - palTogglePad(IOPORT3, PORTC_TEENSY_PIN13); + palTogglePad(TEENSY_PIN13_IOPORT, TEENSY_PIN13); chThdSleepMilliseconds(500); } } diff --git a/demos/KINETIS/RT-TEENSY3/mcuconf.h b/demos/KINETIS/RT-TEENSY3/mcuconf.h index ae35fe3..f4e1f8d 100644 --- a/demos/KINETIS/RT-TEENSY3/mcuconf.h +++ b/demos/KINETIS/RT-TEENSY3/mcuconf.h @@ -25,32 +25,48 @@ /* Select the MCU clocking mode below by enabling the appropriate block. */ -/* FEI mode */ +/* PEE mode - 48MHz system clock driven by external crystal. */ +#if 1 +#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE +#define KINETIS_PLLCLK_FREQUENCY 96000000UL +#define KINETIS_SYSCLK_FREQUENCY 48000000UL +#endif + +/* FEI mode (~48MHz) */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI -#define KINETIS_SYSCLK_FREQUENCY 21000000UL +#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ +#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ +#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */ +#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */ +#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY +#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2 #endif /* 0 */ /* FEE mode - 24 MHz with external 32.768 kHz crystal */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */ #define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */ #define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */ #define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */ -#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4) +#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4) #endif /* 0 */ /* FEE mode - 48 MHz */ +/* not implemented */ #if 0 #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */ #define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */ -#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ -#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ +#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */ +#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */ #define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */ #endif /* 0 */ -- cgit v1.2.3