From 6f67aa78c3061654bb50ed86dc5f104ca49e87b8 Mon Sep 17 00:00:00 2001 From: Nicolas Reinecke Date: Sat, 30 Apr 2016 16:03:33 +0200 Subject: add STM32 qei (quadrature encoder interface) driver Code from tinito in forum thread: http://forum.chibios.org/phpbb/viewtopic.php?f=14&t=685 Updated to chibios trunk. --- os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c | 293 ++++++++++++++++++++++++ os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h | 347 +++++++++++++++++++++++++++++ os/hal/ports/STM32/STM32F0xx/platform.mk | 1 + os/hal/ports/STM32/STM32F1xx/platform.mk | 1 + os/hal/ports/STM32/STM32F3xx/platform.mk | 3 +- os/hal/ports/STM32/STM32F4xx/platform.mk | 1 + 6 files changed, 645 insertions(+), 1 deletion(-) create mode 100644 os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c create mode 100644 os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h (limited to 'os/hal/ports/STM32') diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c new file mode 100644 index 0000000..c9f511b --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -0,0 +1,293 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIMv1/hal_qei_lld.c + * @brief STM32 QEI subsystem low level driver header. + * + * @addtogroup QEI + * @{ + */ + +#include "hal.h" + +#if HAL_USE_QEI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief QEID1 driver identifier. + * @note The driver QEID1 allocates the complex timer TIM1 when enabled. + */ +#if STM32_QEI_USE_TIM1 || defined(__DOXYGEN__) +QEIDriver QEID1; +#endif + +/** + * @brief QEID2 driver identifier. + * @note The driver QEID1 allocates the timer TIM2 when enabled. + */ +#if STM32_QEI_USE_TIM2 || defined(__DOXYGEN__) +QEIDriver QEID2; +#endif + +/** + * @brief QEID3 driver identifier. + * @note The driver QEID1 allocates the timer TIM3 when enabled. + */ +#if STM32_QEI_USE_TIM3 || defined(__DOXYGEN__) +QEIDriver QEID3; +#endif + +/** + * @brief QEID4 driver identifier. + * @note The driver QEID4 allocates the timer TIM4 when enabled. + */ +#if STM32_QEI_USE_TIM4 || defined(__DOXYGEN__) +QEIDriver QEID4; +#endif + +/** + * @brief QEID5 driver identifier. + * @note The driver QEID5 allocates the timer TIM5 when enabled. + */ +#if STM32_QEI_USE_TIM5 || defined(__DOXYGEN__) +QEIDriver QEID5; +#endif + +/** + * @brief QEID8 driver identifier. + * @note The driver QEID8 allocates the timer TIM8 when enabled. + */ +#if STM32_QEI_USE_TIM8 || defined(__DOXYGEN__) +QEIDriver QEID8; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level QEI driver initialization. + * + * @notapi + */ +void qei_lld_init(void) { + +#if STM32_QEI_USE_TIM1 + /* Driver initialization.*/ + qeiObjectInit(&QEID1); + QEID1.tim = STM32_TIM1; +#endif + +#if STM32_QEI_USE_TIM2 + /* Driver initialization.*/ + qeiObjectInit(&QEID2); + QEID2.tim = STM32_TIM2; +#endif + +#if STM32_QEI_USE_TIM3 + /* Driver initialization.*/ + qeiObjectInit(&QEID3); + QEID3.tim = STM32_TIM3; +#endif + +#if STM32_QEI_USE_TIM4 + /* Driver initialization.*/ + qeiObjectInit(&QEID4); + QEID4.tim = STM32_TIM4; +#endif + +#if STM32_QEI_USE_TIM5 + /* Driver initialization.*/ + qeiObjectInit(&QEID5); + QEID5.tim = STM32_TIM5; +#endif + +#if STM32_QEI_USE_TIM8 + /* Driver initialization.*/ + qeiObjectInit(&QEID8); + QEID8.tim = STM32_TIM8; +#endif +} + +/** + * @brief Configures and activates the QEI peripheral. + * + * @param[in] qeip pointer to the @p QEIDriver object + * + * @notapi + */ +void qei_lld_start(QEIDriver *qeip) { + + if (qeip->state == QEI_STOP) { + /* Clock activation and timer reset.*/ +#if STM32_QEI_USE_TIM1 + if (&QEID1 == qeip) { + rccEnableTIM1(FALSE); + rccResetTIM1(); + } +#endif +#if STM32_QEI_USE_TIM2 + if (&QEID2 == qeip) { + rccEnableTIM2(FALSE); + rccResetTIM2(); + } +#endif +#if STM32_QEI_USE_TIM3 + if (&QEID3 == qeip) { + rccEnableTIM3(FALSE); + rccResetTIM3(); + } +#endif +#if STM32_QEI_USE_TIM4 + if (&QEID4 == qeip) { + rccEnableTIM4(FALSE); + rccResetTIM4(); + } +#endif + +#if STM32_QEI_USE_TIM5 + if (&QEID5 == qeip) { + rccEnableTIM5(FALSE); + rccResetTIM5(); + } +#endif +#if STM32_QEI_USE_TIM8 + if (&QEID8 == qeip) { + rccEnableTIM8(FALSE); + rccResetTIM8(); + } +#endif + } + /* Timer configuration.*/ + qeip->tim->CR1 = 0; /* Initially stopped. */ + qeip->tim->CR2 = 0; + qeip->tim->PSC = 0; + qeip->tim->DIER = 0; + qeip->tim->ARR = 0xFFFF; + + /* Set Capture Compare 1 and Capture Compare 2 as input. */ + qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + if (qeip->config->mode == QEI_MODE_QUADRATURE) { + if (qeip->config->resolution == QEI_BOTH_EDGES) + qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; + else + qeip->tim->SMCR = TIM_SMCR_SMS_0; + } else { + /* Direction/Clock mode. + * Direction input on TI1, Clock input on TI2. */ + qeip->tim->SMCR = TIM_SMCR_SMS_0; + } + + if (qeip->config->dirinv == QEI_DIRINV_TRUE) + qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC2E; + else + qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E; +} + +/** + * @brief Deactivates the QEI peripheral. + * + * @param[in] qeip pointer to the @p QEIDriver object + * + * @notapi + */ +void qei_lld_stop(QEIDriver *qeip) { + + if (qeip->state == QEI_READY) { + qeip->tim->CR1 = 0; /* Timer disabled. */ + + /* Clock deactivation.*/ +#if STM32_QEI_USE_TIM1 + if (&QEID1 == qeip) { + rccDisableTIM1(FALSE); + } +#endif +#if STM32_QEI_USE_TIM2 + if (&QEID2 == qeip) { + rccDisableTIM2(FALSE); + } +#endif +#if STM32_QEI_USE_TIM3 + if (&QEID3 == qeip) { + rccDisableTIM3(FALSE); + } +#endif +#if STM32_QEI_USE_TIM4 + if (&QEID4 == qeip) { + rccDisableTIM4(FALSE); + } +#endif +#if STM32_QEI_USE_TIM5 + if (&QEID5 == qeip) { + rccDisableTIM5(FALSE); + } +#endif + } +#if STM32_QEI_USE_TIM8 + if (&QEID8 == qeip) { + rccDisableTIM8(FALSE); + } +#endif +} + +/** + * @brief Enables the input capture. + * + * @param[in] qeip pointer to the @p QEIDriver object + * + * @notapi + */ +void qei_lld_enable(QEIDriver *qeip) { + + qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */ +} + +/** + * @brief Disables the input capture. + * + * @param[in] qeip pointer to the @p QEIDriver object + * + * @notapi + */ +void qei_lld_disable(QEIDriver *qeip) { + + qeip->tim->CR1 = 0; /* Timer disabled. */ +} + +#endif /* HAL_USE_QEI */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h new file mode 100644 index 0000000..f098d7b --- /dev/null +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h @@ -0,0 +1,347 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIMv1/hal_qei_lld.h + * @brief STM32 QEI subsystem low level driver header. + * + * @addtogroup QEI + * @{ + */ + +#ifndef HAL_QEI_LLD_H +#define HAL_QEI_LLD_H + +#if HAL_USE_QEI || defined(__DOXYGEN__) + +#include "stm32_tim.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief QEID1 driver enable switch. + * @details If set to @p TRUE the support for QEID1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM1 FALSE +#endif + +/** + * @brief QEID2 driver enable switch. + * @details If set to @p TRUE the support for QEID2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM2 FALSE +#endif + +/** + * @brief QEID3 driver enable switch. + * @details If set to @p TRUE the support for QEID3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM3 FALSE +#endif + +/** + * @brief QEID4 driver enable switch. + * @details If set to @p TRUE the support for QEID4 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM4 FALSE +#endif + +/** + * @brief QEID5 driver enable switch. + * @details If set to @p TRUE the support for QEID5 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM5 FALSE +#endif + +/** + * @brief QEID8 driver enable switch. + * @details If set to @p TRUE the support for QEID8 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__) +#define STM32_QEI_USE_TIM8 FALSE +#endif + +/** + * @brief QEID1 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM1_IRQ_PRIORITY 7 +#endif + +/** + * @brief QEID2 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM2_IRQ_PRIORITY 7 +#endif + +/** + * @brief QEID3 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM3_IRQ_PRIORITY 7 +#endif + +/** + * @brief QEID4 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM4_IRQ_PRIORITY 7 +#endif + +/** + * @brief QEID5 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM5_IRQ_PRIORITY 7 +#endif + +/** + * @brief QEID8 interrupt priority level setting. + */ +#if !defined(STM32_QEI_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QEI_TIM8_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1 +#error "TIM1 not present in the selected device" +#endif + +#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2 +#error "TIM2 not present in the selected device" +#endif + +#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3 +#error "TIM3 not present in the selected device" +#endif + +#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4 +#error "TIM4 not present in the selected device" +#endif + +#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5 +#error "TIM5 not present in the selected device" +#endif + +#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8 +#error "TIM8 not present in the selected device" +#endif + +#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \ + !STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \ + !STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8 +#error "QEI driver activated but no TIM peripheral assigned" +#endif + +#if STM32_QEI_USE_TIM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM1" +#endif + +#if STM32_QEI_USE_TIM2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM2" +#endif + +#if STM32_QEI_USE_TIM3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM3" +#endif + +#if STM32_QEI_USE_TIM4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM4" +#endif + +#if STM32_QEI_USE_TIM5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM5" +#endif + +#if STM32_QEI_USE_TIM8 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM8_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM8" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief QEI count mode. + */ +typedef enum { + QEI_MODE_QUADRATURE = 0, /**< Quadrature encoder mode. */ + QEI_MODE_DIRCLOCK = 1, /**< Direction/Clock mode. */ +} qeimode_t; + +/** + * @brief QEI resolution. + */ +typedef enum { + QEI_SINGLE_EDGE = 0, /**< Count only on edges from first channel. */ + QEI_BOTH_EDGES = 1, /**< Count on both edges (resolution doubles).*/ +} qeiresolution_t; + +/** + * @brief QEI direction inversion. + */ +typedef enum { + QEI_DIRINV_FALSE = 0, /**< Do not invert counter direction. */ + QEI_DIRINV_TRUE = 1, /**< Invert counter direction. */ +} qeidirinv_t; + +/** + * @brief QEI counter type. + */ +typedef uint16_t qeicnt_t; + +/** + * @brief QEI delta type. + */ +typedef int16_t qeidelta_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Count mode. + */ + qeimode_t mode; + /** + * @brief Resolution. + */ + qeiresolution_t resolution; + /** + * @brief Direction inversion. + */ + qeidirinv_t dirinv; + /* End of the mandatory fields.*/ +} QEIConfig; + +/** + * @brief Structure representing an QEI driver. + */ +struct QEIDriver { + /** + * @brief Driver state. + */ + qeistate_t state; + /** + * @brief Last count value. + */ + qeicnt_t last; + /** + * @brief Current configuration data. + */ + const QEIConfig *config; +#if defined(QEI_DRIVER_EXT_FIELDS) + QEI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the counter value. + * + * @param[in] qeip pointer to the @p QEIDriver object + * @return The current counter value. + * + * @notapi + */ +#define qei_lld_get_count(qeip) ((qeip)->tim->CNT) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__) +extern QEIDriver QEID1; +#endif + +#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__) +extern QEIDriver QEID2; +#endif + +#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__) +extern QEIDriver QEID3; +#endif + +#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__) +extern QEIDriver QEID4; +#endif + +#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__) +extern QEIDriver QEID5; +#endif + +#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__) +extern QEIDriver QEID8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void qei_lld_init(void); + void qei_lld_start(QEIDriver *qeip); + void qei_lld_stop(QEIDriver *qeip); + void qei_lld_enable(QEIDriver *qeip); + void qei_lld_disable(QEIDriver *qeip); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_QEI */ + +#endif /* HAL_QEI_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index c796984..377acdf 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -2,6 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk index d2aeae0..a8f21bc 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform.mk @@ -6,6 +6,7 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index baa7578..92f033c 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -2,7 +2,8 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index bc18dc6..c312e72 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -8,6 +8,7 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c -- cgit v1.2.3