From 4aa00494c2716285e85246295fb2ed86aa99a4e4 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Sat, 10 Mar 2018 14:58:45 +0100 Subject: Added shared variables to startup, board and platform makefiles --- os/hal/ports/TIVA/TM4C123x/platform.mk | 4 ++++ os/hal/ports/TIVA/TM4C129x/platform.mk | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'os/hal/ports') diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 8372c25..8e447ec 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -27,3 +27,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 934a6c2..9702796 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -28,3 +28,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) -- cgit v1.2.3 From b143e38a6684624fce07cc991853e8d2b19c420d Mon Sep 17 00:00:00 2001 From: Romain Reignier Date: Sun, 11 Mar 2018 22:13:06 +0100 Subject: Keep track of STM32 RCC API RCC API changed in 01/2018 so apply the changes. Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing. So update the other modules too. --- os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c | 24 ++++++++++++------------ os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c | 12 ++++++------ os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c | 14 +++++++------- 3 files changed, 25 insertions(+), 25 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c index c04278e..ed4c5b8 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c @@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) { if (&EICUD1 == eicup) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_EICU_USE_TIM2 if (&EICUD2 == eicup) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_EICU_USE_TIM3 if (&EICUD3 == eicup) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_EICU_USE_TIM4 if (&EICUD4 == eicup) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_EICU_USE_TIM5 if (&EICUD5 == eicup) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_EICU_USE_TIM8 if (&EICUD8 == eicup) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_EICU_USE_TIM9 if (&EICUD9 == eicup) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif #if STM32_EICU_USE_TIM12 if (&EICUD12 == eicup) { nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); + rccDisableTIM12(); } #endif } #if STM32_EICU_USE_TIM10 if (&EICUD10 == eicup) { nvicDisableVector(STM32_TIM10_NUMBER); - rccDisableTIM10(FALSE); + rccDisableTIM10(); } #endif #if STM32_EICU_USE_TIM11 if (&EICUD11 == eicup) { nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); + rccDisableTIM11(); } #endif #if STM32_EICU_USE_TIM13 if (&EICUD13 == eicup) { nvicDisableVector(STM32_TIM13_NUMBER); - rccDisableTIM13(FALSE); + rccDisableTIM13(); } #endif #if STM32_EICU_USE_TIM14 if (&EICUD14 == eicup) { nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); + rccDisableTIM14(); } #endif } diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index cef015e..e07b946 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) { /* Clock activation and timer reset.*/ #if STM32_QEI_USE_TIM1 if (&QEID1 == qeip) { - rccEnableTIM1(); + rccEnableTIM1(FALSE); rccResetTIM1(); } #endif #if STM32_QEI_USE_TIM2 if (&QEID2 == qeip) { - rccEnableTIM2(); + rccEnableTIM2(FALSE); rccResetTIM2(); } #endif #if STM32_QEI_USE_TIM3 if (&QEID3 == qeip) { - rccEnableTIM3(); + rccEnableTIM3(FALSE); rccResetTIM3(); } #endif #if STM32_QEI_USE_TIM4 if (&QEID4 == qeip) { - rccEnableTIM4(); + rccEnableTIM4(FALSE); rccResetTIM4(); } #endif #if STM32_QEI_USE_TIM5 if (&QEID5 == qeip) { - rccEnableTIM5(); + rccEnableTIM5(FALSE); rccResetTIM5(); } #endif #if STM32_QEI_USE_TIM8 if (&QEID8 == qeip) { - rccEnableTIM8(); + rccEnableTIM8(FALSE); rccResetTIM8(); } #endif diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 37a48fd..d95c6a3 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) { if (&TIMCAPD1 == timcapp) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_TIMCAP_USE_TIM2 if (&TIMCAPD2 == timcapp) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_TIMCAP_USE_TIM3 if (&TIMCAPD3 == timcapp) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_TIMCAP_USE_TIM4 if (&TIMCAPD4 == timcapp) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_TIMCAP_USE_TIM5 if (&TIMCAPD5 == timcapp) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_TIMCAP_USE_TIM8 if (&TIMCAPD8 == timcapp) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_TIMCAP_USE_TIM9 if (&TIMCAPD9 == timcapp) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif } -- cgit v1.2.3 From 32cdf41174686c78d7978d0a4232b1ac8bc0f2f6 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Mon, 12 Mar 2018 19:04:54 +0100 Subject: Fixed warnings triggered by -Wundef compile option --- os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 32 ++++++++++++++++---------------- os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c | 2 +- os/hal/ports/TIVA/TM4C123x/hal_lld.h | 2 +- 3 files changed, 18 insertions(+), 18 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h index 993d5c3..e884a92 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -665,82 +665,82 @@ typedef uint32_t iopadid_t; #error "Invalid IRQ priority assigned to GPION" #endif -#if TIVA_HAS_GPIOP0 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP0" #endif -#if TIVA_HAS_GPIOP1 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP1" #endif -#if TIVA_HAS_GPIOP2 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP2" #endif -#if TIVA_HAS_GPIOP3 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP3" #endif -#if TIVA_HAS_GPIOP4 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP4" #endif -#if TIVA_HAS_GPIOP5 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP5" #endif -#if TIVA_HAS_GPIOP6 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP6" #endif -#if TIVA_HAS_GPIOP7 && \ +#if TIVA_HAS_GPIOP && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOP7" #endif -#if TIVA_HAS_GPIOQ0 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ0" #endif -#if TIVA_HAS_GPIOQ1 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ1" #endif -#if TIVA_HAS_GPIOQ2 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ2" #endif -#if TIVA_HAS_GPIOQ3 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ3" #endif -#if TIVA_HAS_GPIOQ4 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ4" #endif -#if TIVA_HAS_GPIOQ5 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ5" #endif -#if TIVA_HAS_GPIOQ6 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ6" #endif -#if TIVA_HAS_GPIOQ7 && \ +#if TIVA_HAS_GPIOQ && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPIOQ7" #endif diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index 7da95b8..0f9576a 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -74,7 +74,7 @@ #error "TIVA_ST_USE_TIMER specifies an unsupported timer" #endif -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF #error "the selected ST frequency is not obtainable because TIM timer prescaler limits" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index 5937b88..5d38a67 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -203,7 +203,7 @@ #error "Invalid value for TIVA_BYPASS_VALUE defined" #endif -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) +#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE) #error "Main Oscillator selected but not enabled" #endif -- cgit v1.2.3 From 6513490986e564fd944ec3e460eb5f91b5cd9c35 Mon Sep 17 00:00:00 2001 From: Romain Reignier Date: Mon, 12 Mar 2018 21:33:11 +0100 Subject: platform: add support for STM32L4 family --- os/hal/ports/STM32/STM32L4xx/platform.mk | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 os/hal/ports/STM32/STM32L4xx/platform.mk (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk new file mode 100644 index 0000000..b9bbfea --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -0,0 +1,21 @@ +include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk + +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c + +PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD -- cgit v1.2.3 From 424c7a2717fb6b2a847cec5c0060e3236f25e97f Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 14 Mar 2018 20:15:13 +0100 Subject: Fixed most testhal examples for STM32, updated configs using script. Fixed deprecated MS2ST calls. --- os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c | 2 +- os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c | 8 ++++---- os/hal/ports/STM32/STM32F0xx/platform.mk | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index c6b3d11..a005c32 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -442,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* wait until the bus is released */ /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT); + end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT); while(true) { osalSysLock(); diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index 500b2e7..71c6ada 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -159,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { #if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif - rccDisableFSMC(FALSE); + rccDisableFSMC(); } #endif /* STM32_FSMC_USE_FSMC1 */ diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c index 4723508..15d8853 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c @@ -1665,9 +1665,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy * despite reporting a successful por enable. */ uerr("Detected enabled port; resetting OTG core"); otg->GAHBCFG = 0; - osalThreadSleepS(MS2ST(20)); + osalThreadSleepS(TIME_MS2I(20)); _usbh_start(usbh); /* this effectively resets the core */ - osalThreadSleepS(MS2ST(100)); /* during this delay, the core generates connect ISR */ + osalThreadSleepS(TIME_MS2I(100)); /* during this delay, the core generates connect ISR */ uinfo("OTG reset ended"); if (otg->HPRT & HPRT_PCSTS) { /* if the device is still connected, don't report a C_CONNECTION flag, which would cause @@ -1680,9 +1680,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG); while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0); otg->HPRT = hprt | HPRT_PRST; - osalThreadSleepS(MS2ST(15)); + osalThreadSleepS(TIME_MS2I(15)); otg->HPRT = hprt; - osalThreadSleepS(MS2ST(10)); + osalThreadSleepS(TIME_MS2I(10)); usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET; osalSysUnlock(); } break; diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 377acdf..0102162 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -2,7 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ -- cgit v1.2.3