From 223f46589016f2dce6a29cbd00d9020f80d2a556 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 27 Oct 2016 22:55:17 +0200 Subject: Replaced custom register bitfield macros by TivaWare bitfield macros. --- os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c | 16 +-- os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c | 16 +-- os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h | 5 +- os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h | 135 ------------------------ os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c | 37 ++++++- os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h | 74 ------------- os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c | 19 ++-- os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c | 74 ++++++------- os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h | 84 +-------------- os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c | 28 ++--- os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h | 157 ---------------------------- os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c | 6 +- os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h | 17 --- os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c | 2 +- os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h | 45 +------- 15 files changed, 115 insertions(+), 600 deletions(-) delete mode 100644 os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h (limited to 'os') diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c index fdf7c17..60d2b82 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c @@ -594,7 +594,7 @@ void gpt_lld_start(GPTDriver *gptp) /* Timer configuration.*/ HWREG(gptp->gpt + TIMER_O_CTL) = 0; - HWREG(gptp->gpt + TIMER_O_CFG) = GPTM_CFG_CFG_SPLIT; + HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT; HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1); } @@ -710,9 +710,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff; - HWREG(gptp->gpt + TIMER_O_IMR) = GPTM_IMR_TATOIM; - HWREG(gptp->gpt + TIMER_O_TAMR) = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - HWREG(gptp->gpt + TIMER_O_CTL) = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; + HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM; + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; } /** @@ -726,7 +726,7 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { HWREG(gptp->gpt + TIMER_O_IMR) = 0; HWREG(gptp->gpt + TIMER_O_TAILR) = 0; - HWREG(gptp->gpt + TIMER_O_CTL) &= ~GPTM_CTL_TAEN; + HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN; } /** @@ -742,11 +742,11 @@ void gpt_lld_stop_timer(GPTDriver *gptp) */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - HWREG(gptp->gpt + TIMER_O_TAMR) = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; - HWREG(gptp->gpt + TIMER_O_CTL) = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(HWREG(gptp->gpt + TIMER_O_RIS) & GPTM_IMR_TATOIM)) + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; + while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM)) ; HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; } diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index c98a30f..d87652b 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -187,7 +187,7 @@ OSAL_IRQ_HANDLER(ST_HANDLER) mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS); HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis; - if (mis & GPTM_IMR_TAMIM) { + if (mis & TIMER_IMR_TAMIM) { osalSysLockFromISR(); osalOsTimerHandlerI(); osalSysUnlockFromISR(); @@ -219,14 +219,16 @@ void st_lld_init(void) /* Initializing the counter in free running down mode.*/ HWREG(TIVA_ST_TIM + TIMER_O_CTL) = 0; - HWREG(TIVA_ST_TIM + TIMER_O_CFG) = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ + HWREG(TIVA_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - HWREG(TIVA_ST_TIM + TIMER_O_CTL) = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ /* IRQ enabled.*/ nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h index c1c9494..cd076d6 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h @@ -29,7 +29,6 @@ #include "mcuconf.h" #include "tiva_registry.h" -#include "tiva_gpt.h" /*===========================================================================*/ /* Driver constants. */ @@ -213,7 +212,7 @@ static inline void st_lld_start_alarm(systime_t time) { HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS); - HWREG(TIVA_ST_TIM + TIMER_O_IMR) = GPTM_IMR_TAMIM; + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; } /** @@ -261,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void) */ static inline bool st_lld_is_alarm_active(void) { - return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & GPTM_IMR_TAMIM) !=0); + return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); } #endif /* HAL_ST_LLD_H */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h b/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index 3b49d6c..cf70dca 100644 --- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -30,6 +30,33 @@ /* Driver local definitions. */ /*===========================================================================*/ +// interrupt states +#define STATE_IDLE 0 +#define STATE_WRITE_NEXT 1 +#define STATE_WRITE_FINAL 2 +#define STATE_WAIT_ACK 3 +#define STATE_SEND_ACK 4 +#define STATE_READ_ONE 5 +#define STATE_READ_FIRST 6 +#define STATE_READ_NEXT 7 +#define STATE_READ_FINAL 8 +#define STATE_READ_WAIT 9 + +#define TIVA_I2C_SIGNLE_SEND (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_START (I2C_MCS_RUN | I2C_MCS_START) +#define TIVA_I2C_BURST_SEND_CONTINUE (I2C_MCS_RUN) +#define TIVA_I2C_BURST_SEND_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_STOP (I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_ERROR_STOP (I2C_MCS_STOP) + +#define TIVA_I2C_SINGLE_RECEIVE (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_START (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_CONTINUE (I2C_MCS_RUN | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (I2C_MCS_STOP) + +#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -134,10 +161,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) // read interrupt status status = HWREG(i2c + I2C_O_MCS); - if (status & TIVA_MCS_ERROR) { + if (status & I2C_MCS_ERROR) { i2cp->errors |= I2C_BUS_ERROR; } - if (status & TIVA_MCS_ARBLST) { + if (status & I2C_MCS_ARBLST) { i2cp->errors |= I2C_ARBITRATION_LOST; } @@ -760,7 +787,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -834,7 +861,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -852,7 +879,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, HWREG(i2c + I2C_O_MSA) = i2cp->addr; /* enable interrupts */ - HWREG(i2c + I2C_O_MIMR) = TIVA_MIMR_IM; + HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM; /* put data in register */ HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h index 09a062f..4eabda8 100644 --- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h @@ -31,80 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c index 6f132dd..964f45b 100644 --- a/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c @@ -30,13 +30,6 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -82,31 +75,31 @@ static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC); HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc; - if (((isc & PWM_INT_CMPAD) != 0) && + if (((isc & PWM_X_ISC_INTCMPAD) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPAU) != 0) && + if (((isc & PWM_X_ISC_INTCMPAU) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPBD) != 0) && + if (((isc & PWM_X_ISC_INTCMPBD) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CMPBU) != 0) && + if (((isc & PWM_X_ISC_INTCMPBU) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } } diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index f901512..42efca6 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -82,12 +82,12 @@ static void spi_serve_interrupt(SPIDriver *spip) uint32_t dmachis = HWREG(UDMA_CHIS); /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { + if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) { TIVA_SPI_SSI_ERROR_HOOK(spip); } - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { + if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) == + (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) { /* Clear DMA Channel interrupts.*/ HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); @@ -301,22 +301,22 @@ void spi_lld_start(SPIDriver *spip) HWREG(spip->ssi + SSI_O_CC) = 0; /* Clear pending interrupts.*/ - HWREG(spip->ssi + SSI_O_ICR) = TIVA_ICR_RTIC | TIVA_ICR_RORIC; + HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC; /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - HWREG(spip->ssi + SSI_O_IM) = TIVA_IM_RTIM | TIVA_IM_RORIM; + HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM; /* Configure the clock prescale divisor.*/ HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr; /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); + HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO; /* Enable SSI.*/ - HWREG(spip->ssi + SSI_O_CR1) |= TIVA_CR1_SSE; + HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE; /* Enable RX and TX DMA channels.*/ - HWREG(spip->ssi + SSI_O_DMACTL) = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); + HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE); } /** @@ -399,20 +399,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -421,16 +421,16 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -470,11 +470,11 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | @@ -483,7 +483,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -492,7 +492,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | @@ -501,7 +501,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -539,11 +539,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | @@ -551,8 +551,8 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -561,7 +561,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | @@ -569,8 +569,8 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -608,12 +608,12 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -621,7 +621,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -630,8 +630,8 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -639,7 +639,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -675,7 +675,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame; - while ((HWREG(spip->ssi + SSI_O_SR) & TIVA_SR_RNE) == 0) + while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0) ; return (uint16_t)HWREG(spip->ssi + SSI_O_DR); } diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 41ab70e..dd49e84 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -32,89 +32,9 @@ /*===========================================================================*/ /** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ - */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ + * @brief CR0 Serial Clock Rate helper. */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ +#define SSI_CR0_SCR(n) ((n) << 8) /*===========================================================================*/ /* Driver pre-compile time settings. */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c index 7203e74..2e3b213 100644 --- a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c @@ -143,7 +143,7 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; /* Enable interrupts.*/ - HWREG(u + UART_O_IM) = TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; + HWREG(u + UART_O_IM) = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM; } /** @@ -153,7 +153,7 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) */ static void uart_deinit(uint32_t u) { - HWREG(u + UART_O_CTL) &= ~TIVA_CTL_UARTEN; + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; } /** @@ -166,13 +166,13 @@ static void set_error(SerialDriver *sdp, uint16_t err) { eventflags_t sts = 0; - if (err & TIVA_MIS_FEMIS) + if (err & UART_MIS_FEMIS) sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) + if (err & UART_MIS_PEMIS) sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) + if (err & UART_MIS_BEMIS) sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) + if (err & UART_MIS_OEMIS) sts |= SD_OVERRUN_ERROR; osalSysLockFromISR(); chnAddFlagsI(sdp, sts); @@ -195,17 +195,17 @@ static void serial_serve_interrupt(SerialDriver *sdp) HWREG(u + UART_O_ICR) = mis; /* clear interrupts */ - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { + if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) { set_error(sdp, mis); } - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { + if ((mis & UART_MIS_RXMIS) || (mis & UART_MIS_RTMIS)) { osalSysLockFromISR(); if (iqIsEmptyI(&sdp->iqueue)) { chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); } osalSysUnlockFromISR(); - while ((HWREG(u + UART_O_FR) & TIVA_FR_RXFE) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) { osalSysLockFromISR(); if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) { chnAddFlagsI(sdp, SD_OVERRUN_ERROR); @@ -214,14 +214,14 @@ static void serial_serve_interrupt(SerialDriver *sdp) } } - if (mis & TIVA_MIS_TXMIS) { - while ((HWREG(u + UART_O_FR) & TIVA_FR_TXFF) == 0) { + if (mis & UART_MIS_TXMIS) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b; osalSysLockFromISR(); b = oqGetI(&sdp->oqueue); osalSysUnlockFromISR(); if (b < Q_OK) { - HWREG(u + UART_O_IM) &= ~TIVA_IM_TXIM; + HWREG(u + UART_O_IM) &= ~UART_IM_TXIM; osalSysLockFromISR(); chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); osalSysUnlockFromISR(); @@ -239,7 +239,7 @@ static void fifo_load(SerialDriver *sdp) { uint32_t u = sdp->uart; - while ((HWREG(u + UART_O_FR) & TIVA_FR_TXFF) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b = oqGetI(&sdp->oqueue); if (b < Q_OK) { chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); @@ -248,7 +248,7 @@ static void fifo_load(SerialDriver *sdp) HWREG(u + UART_O_DR) = b; } - HWREG(u + UART_O_IM) |= TIVA_IM_TXIM; /* transmit interrupt enable */ + HWREG(u + UART_O_IM) |= UART_IM_TXIM; /* transmit interrupt enable */ } /** diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h index 49239fb..d52828c 100644 --- a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h @@ -31,163 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} - */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) - -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c index 1fc86f2..ddd01e0 100644 --- a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c @@ -62,7 +62,7 @@ static void serve_interrupt(WDGDriver *wdgp) mis = HWREG(wdgp->wdt + WDT_O_MIS); - if (mis & MIS_WDTMIS) { + if (mis & WDT_MIS_WDTMIS) { /* Invoke callback, if any */ if (wdgp->config->callback) { if (wdgp->config->callback(wdgp)) { @@ -159,10 +159,10 @@ void wdg_lld_start(WDGDriver *wdgp) HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test; wdgTivaSyncWrite(wdgp); - HWREG(wdgp->wdt + WDT_O_CTL) |= CTL_RESEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN; wdgTivaSyncWrite(wdgp); - HWREG(wdgp->wdt + WDT_O_CTL) |= CTL_INTEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN; wdgTivaSyncWrite(wdgp); } diff --git a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h index 38bee25..77badb3 100644 --- a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h @@ -32,23 +32,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c index 4d212b7..bb379cb 100644 --- a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c @@ -104,7 +104,7 @@ void udmaInit(void) nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); /* Enable UDMA controller.*/ - HWREG(UDMA_CFG) = 1; + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; /* Set address of control table.*/ HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary; diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h index cba9090..0157277 100644 --- a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h @@ -22,52 +22,9 @@ /*===========================================================================*/ /** - * @name CHCTL register defines. - * @{ + * @brief CHCTL XFERSIZE helper. */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 #define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ -- cgit v1.2.3