From a5cd9d134b1be7e3a80451f4cd57684a04616b60 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Sat, 16 Apr 2016 19:40:24 +0100 Subject: [KINETIS] Rename I2Cx.S1 to I2Cx.S for KL26Z. For some strange reason Freescale refers to this I2C register as 'S1' on KL26Z and as 'S' on all other Kinetises (K20x, KL2xZ). To avoid horrible #ifs in the driver, use 'S' also on KL26Z. --- os/common/ext/CMSIS/KINETIS/kl26z.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'os') diff --git a/os/common/ext/CMSIS/KINETIS/kl26z.h b/os/common/ext/CMSIS/KINETIS/kl26z.h index 2c63f12..88caf38 100644 --- a/os/common/ext/CMSIS/KINETIS/kl26z.h +++ b/os/common/ext/CMSIS/KINETIS/kl26z.h @@ -152,7 +152,7 @@ typedef struct __IO uint8_t A1; __IO uint8_t F; __IO uint8_t C1; - __IO uint8_t S1; + __IO uint8_t S; /* Denoted 'S1' in datasheet. */ __IO uint8_t D; __IO uint8_t C2; __IO uint8_t FLT; @@ -876,14 +876,14 @@ typedef struct { #define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ /*********** Bits definition for I2Cx_S1 register *************/ -#define I2Cx_S1_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S1_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S1_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S1_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S1_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S1_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S1_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S1_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ /*********** Bits definition for I2Cx_D register **************/ #define I2Cx_D_DATA_SHIFT 0 /*!< Data */ -- cgit v1.2.3 From cee50b34e2a62d11913eddb47be5f9c271063203 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Sat, 16 Apr 2016 20:26:40 +0100 Subject: [KINETIS] Add FRDM-KL26Z/I2C demo. --- os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'os') diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h index e13debb..2ae42aa 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h +++ b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h @@ -49,11 +49,13 @@ #define GPIO_LIGHTSNS IOPORT5 #define PIN_LIGHTSNS 22 -#define I2C_INERIAL_SENSOR I2C0 - /* * Not configured: * - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10 + * - I2C inertial sensor on I2C0, routed to PTE25 and PTE25 + * Note: these pins are assigned to I2C0 by default; + * if I2C0 is wanted on other pins, these need to be + * assigned another function explicitly! */ #if !defined(_FROM_ASM_) -- cgit v1.2.3 From 7485ece089bd7fbf20ef57b81e73f41a20153981 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Sun, 17 Apr 2016 08:58:59 +0100 Subject: [KINETIS] Consolidate KL2x I2C CMSIS defs. --- os/common/ext/CMSIS/KINETIS/kl25z.h | 80 +-------------------------------- os/common/ext/CMSIS/KINETIS/kl26z.h | 80 +-------------------------------- os/common/ext/CMSIS/KINETIS/kl27zxx.h | 80 +-------------------------------- os/common/ext/CMSIS/KINETIS/kl27zxxx.h | 80 +-------------------------------- os/common/ext/CMSIS/KINETIS/kl2xz.h | 82 ++++++++++++++++++++++++++++++++-- 5 files changed, 83 insertions(+), 319 deletions(-) (limited to 'os') diff --git a/os/common/ext/CMSIS/KINETIS/kl25z.h b/os/common/ext/CMSIS/KINETIS/kl25z.h index bf519ab..2f907e1 100644 --- a/os/common/ext/CMSIS/KINETIS/kl25z.h +++ b/os/common/ext/CMSIS/KINETIS/kl25z.h @@ -777,57 +777,9 @@ typedef struct /****************************************************************/ /* */ -/* Inter-Integrated Circuit (I2C) */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ /* */ /****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ -#define I2Cx_A1_AD_SHIFT 1 -#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_MULT_SHIFT 6 -#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) -#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ -#define I2Cx_F_ICR_SHIFT 0 -#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S register **************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ -#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) -#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ -#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) -#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) - /*********** Bits definition for I2Cx_FLT register ************/ #define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ #define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ @@ -836,36 +788,6 @@ typedef struct #define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) #define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ -#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) -#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ -#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) -#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ -#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) -#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ -#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) -#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) - /****************************************************************/ /* */ /* Universal Asynchronous Receiver/Transmitter (UART) */ diff --git a/os/common/ext/CMSIS/KINETIS/kl26z.h b/os/common/ext/CMSIS/KINETIS/kl26z.h index 88caf38..eefcfd6 100644 --- a/os/common/ext/CMSIS/KINETIS/kl26z.h +++ b/os/common/ext/CMSIS/KINETIS/kl26z.h @@ -849,57 +849,9 @@ typedef struct { /****************************************************************/ /* */ -/* Inter-Integrated Circuit (I2C) */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ /* */ /****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ -#define I2Cx_A1_AD_SHIFT 1 -#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_MULT_SHIFT 6 -#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) -#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ -#define I2Cx_F_ICR_SHIFT 0 -#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S1 register *************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ -#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) -#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ -#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) -#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) - /*********** Bits definition for I2Cx_FLT register ************/ #define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ #define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ @@ -908,36 +860,6 @@ typedef struct { #define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) #define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ -#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) -#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ -#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) -#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ -#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) -#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ -#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) -#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) - /****************************************************************/ /* */ /* Universal Asynchronous Receiver/Transmitter (UART) */ diff --git a/os/common/ext/CMSIS/KINETIS/kl27zxx.h b/os/common/ext/CMSIS/KINETIS/kl27zxx.h index 2a64906..894e172 100644 --- a/os/common/ext/CMSIS/KINETIS/kl27zxx.h +++ b/os/common/ext/CMSIS/KINETIS/kl27zxx.h @@ -757,57 +757,9 @@ typedef struct /****************************************************************/ /* */ -/* Inter-Integrated Circuit (I2C) */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ /* */ /****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ -#define I2Cx_A1_AD_SHIFT 1 -#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_MULT_SHIFT 6 -#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) -#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ -#define I2Cx_F_ICR_SHIFT 0 -#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S register **************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ -#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) -#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ -#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) -#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) - /*********** Bits definition for I2Cx_FLT register ************/ #define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ #define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ @@ -817,36 +769,6 @@ typedef struct #define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) #define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ -#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) -#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ -#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) -#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ -#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) -#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ -#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) -#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) - /*********** Bits definition for I2Cx_S2 register *************/ #define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ #define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ diff --git a/os/common/ext/CMSIS/KINETIS/kl27zxxx.h b/os/common/ext/CMSIS/KINETIS/kl27zxxx.h index 76238c0..a4c966d 100644 --- a/os/common/ext/CMSIS/KINETIS/kl27zxxx.h +++ b/os/common/ext/CMSIS/KINETIS/kl27zxxx.h @@ -783,57 +783,9 @@ typedef struct { /****************************************************************/ /* */ -/* Inter-Integrated Circuit (I2C) */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ /* */ /****************************************************************/ -/*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ -#define I2Cx_A1_AD_SHIFT 1 -#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) - -/*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_MULT_SHIFT 6 -#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) -#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ -#define I2Cx_F_ICR_SHIFT 0 -#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) - -/*********** Bits definition for I2Cx_C1 register *************/ -#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ -#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ -#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ -#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ -#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ -#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ -#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ -#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ - -/*********** Bits definition for I2Cx_S register **************/ -#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ -#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ -#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ -#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ -#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ -#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ -#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ -#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ - -/*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ -#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) -#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) - -/*********** Bits definition for I2Cx_C2 register *************/ -#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ -#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ -#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ -#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ -#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ -#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) -#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) - /*********** Bits definition for I2Cx_FLT register ************/ #define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ #define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ @@ -843,36 +795,6 @@ typedef struct { #define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) #define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) -/*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ -#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) -#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) - -/*********** Bits definition for I2Cx_SMB register ************/ -#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ -#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ -#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ -#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ -#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ -#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ -#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ -#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ - -/*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ -#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) -#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) - -/*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ -#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) -#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) - -/*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ -#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) -#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) - /*********** Bits definition for I2Cx_S2 register *************/ #define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ #define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ diff --git a/os/common/ext/CMSIS/KINETIS/kl2xz.h b/os/common/ext/CMSIS/KINETIS/kl2xz.h index 1ff29b1..10dfecf 100644 --- a/os/common/ext/CMSIS/KINETIS/kl2xz.h +++ b/os/common/ext/CMSIS/KINETIS/kl2xz.h @@ -693,11 +693,87 @@ typedef struct /****************************************************************/ /* */ -/* Inter-Integrated Circuit (I2C) */ +/* Inter-Integrated Circuit (I2C): Device independent part */ /* */ /****************************************************************/ - -/* Device dependent */ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +/*** This register is referred to as 'S1' in KL26Z manual *******/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) /****************************************************************/ /* */ -- cgit v1.2.3 From fa9644e655ca8304a27a85a82a457bbc5785fdcc Mon Sep 17 00:00:00 2001 From: flabbergast Date: Mon, 18 Apr 2016 21:09:29 +0100 Subject: [KINETIS] Slightly rewrite and comment i2c driver. --- os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 199 +++++++++++++++++++++++---------- 1 file changed, 143 insertions(+), 56 deletions(-) (limited to 'os') diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index 1095737..0831eac 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -63,7 +63,7 @@ void config_frequency(I2CDriver *i2cp) { * divider used to generate the SCL clock from the main * system clock. */ - uint16_t icr_table[] = { + const uint16_t icr_table[] = { /* 0x00 - 0x0F */ 20,22,24,26,28,30,34,40,28,32,36,40,44,48,56,68, /* 0x10 - 0x1F */ @@ -117,53 +117,116 @@ static void serve_interrupt(I2CDriver *i2cp) { I2C_TypeDef *i2c = i2cp->i2c; intstate_t state = i2cp->intstate; - if (i2c->S & I2Cx_S_ARBL) { - - i2cp->errors |= I2C_ARBITRATION_LOST; - i2c->S |= I2Cx_S_ARBL; - - } else if (state == STATE_SEND) { - - if (i2c->S & I2Cx_S_RXAK) - i2cp->errors |= I2C_ACK_FAILURE; - else if (i2cp->txbuf != NULL && i2cp->txidx < i2cp->txbytes) - i2c->D = i2cp->txbuf[i2cp->txidx++]; - else - i2cp->intstate = STATE_STOP; - - } else if (state == STATE_DUMMY) { - - if (i2c->S & I2Cx_S_RXAK) - i2cp->errors |= I2C_ACK_FAILURE; - else { - i2c->C1 &= ~I2Cx_C1_TX; - - if (i2cp->rxbytes > 1) - i2c->C1 &= ~I2Cx_C1_TXAK; - else - i2c->C1 |= I2Cx_C1_TXAK; - (void) i2c->D; - i2cp->intstate = STATE_RECV; - } - - } else if (state == STATE_RECV) { - - if (i2cp->rxbytes > 1) { - if (i2cp->rxidx == (i2cp->rxbytes - 2)) - i2c->C1 |= I2Cx_C1_TXAK; - else - i2c->C1 &= ~I2Cx_C1_TXAK; - } + /* check if we're master or slave */ + if (i2c->C1 & I2Cx_C1_MST) { + /* master */ + + if (i2c->S & I2Cx_S_ARBL) { + /* check if we lost arbitration */ + i2cp->errors |= I2C_ARBITRATION_LOST; + i2c->S |= I2Cx_S_ARBL; + /* TODO: may need to do more here, reset bus? */ + /* Perhaps clear MST? */ + + } else if (i2c->S & I2Cx_S_TCF) { + /* just completed byte transfer */ + if (i2c->C1 & I2Cx_C1_TX) { + /* the byte was transmitted */ + + if (state == STATE_SEND) { + /* currently sending stuff */ + + if (i2c->S & I2Cx_S_RXAK) { + /* slave did not ACK */ + i2cp->errors |= I2C_ACK_FAILURE; + /* the thread will be woken up at the end of ISR and release the bus */ + + } else if (i2cp->txbuf != NULL && i2cp->txidx < i2cp->txbytes) { + /* slave ACK'd and we want to send more */ + i2c->D = i2cp->txbuf[i2cp->txidx++]; + } else { + /* slave ACK'd and we are done sending */ + i2cp->intstate = STATE_STOP; + /* this wakes up the waiting thread at the end of ISR */ + } + + } else if (state == STATE_RECV) { + /* should be receiving stuff, so we've just sent the address */ + + if (i2c->S & I2Cx_S_RXAK) { + /* slave did not ACK */ + i2cp->errors |= I2C_ACK_FAILURE; + /* the thread will be woken up and release the bus */ + + } else { + /* slave ACK'd, we should be receiving next */ + i2c->C1 &= ~I2Cx_C1_TX; + + if (i2cp->rxbytes > 1) { + /* multi-byte read, send ACK after next transfer */ + i2c->C1 &= ~I2Cx_C1_TXAK; + } else { + /* only 1 byte remaining, send NAK */ + i2c->C1 |= I2Cx_C1_TXAK; + } + + (void) i2c->D; /* dummy read; triggers next receive */ + } + + } /* possibly check other states here - should not happen! */ + + } else { + /* the byte was received */ + + if (state == STATE_RECV) { + /* currently receiving stuff */ + /* the received byte is now in D */ + + if (i2cp->rxbytes > 1) { + /* expecting at least one byte after this one */ + if (i2cp->rxidx == (i2cp->rxbytes - 2)) { + /* expecting exactly one byte after this one, NAK that one */ + i2c->C1 |= I2Cx_C1_TXAK; + } else { + /* expecting more than one after this one, respond with ACK */ + i2c->C1 &= ~I2Cx_C1_TXAK; + } + } + + if (i2cp->rxidx == i2cp->rxbytes - 1) { + /* D is the last byte we're expecting */ + /* release bus: switch to RX mode, send STOP */ + /* need to do it now otherwise the I2C module will wait for another byte */ + // delayMicroseconds(1); + i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST); + i2cp->intstate = STATE_STOP; + /* this wakes up the waiting thread at the end of ISR */ + } + + /* get the data from D; this triggers the next receive */ + i2cp->rxbuf[i2cp->rxidx++] = i2c->D; + + // if (i2cp->rxidx == i2cp->rxbytes) { + /* done receiving */ + // } + } /* possibly check other states here - should not happen! */ + } - if (i2cp->rxidx == i2cp->rxbytes - 1) - i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST); + } /* possibly check other interrupt flags here */ - i2cp->rxbuf[i2cp->rxidx++] = i2c->D; + } else { + /* slave */ - if (i2cp->rxidx == i2cp->rxbytes) - i2cp->intstate = STATE_STOP; + /* Not implemented yet */ } + /* Reset other interrupt sources */ +#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */ + i2cp->i2c->FLT |= I2Cx_FLT_STOPF; +#endif +#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */ + i2cp->i2c->FLT |= I2Cx_FLT_STARTF; +#endif /* Reset interrupt flag */ i2c->S |= I2Cx_S_IICIF; @@ -260,8 +323,9 @@ void i2c_lld_start(I2CDriver *i2cp) { } config_frequency(i2cp); - i2cp->i2c->C1 |= I2Cx_C1_IICEN | I2Cx_C1_IICIE; - i2cp->intstate = STATE_STOP; + i2cp->i2c->C1 = I2Cx_C1_IICEN | I2Cx_C1_IICIE; // reset I2C, enable interrupts + i2cp->i2c->S = I2Cx_S_IICIF | I2Cx_S_ARBL; // clear status flags just in case + i2cp->intstate = STATE_STOP; // internal state } /** @@ -315,35 +379,58 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->rxbytes = rxbytes; i2cp->rxidx = 0; - /* send START */ - i2cp->i2c->C1 |= I2Cx_C1_MST; - i2cp->i2c->C1 |= I2Cx_C1_TX; - - /* FIXME: should not use busy waiting! */ - while (!(i2cp->i2c->S & I2Cx_S_BUSY)); + /* clear status flags */ +#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */ + i2cp->i2c->FLT |= I2Cx_FLT_STOPF; +#endif +#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */ + i2cp->i2c->FLT |= I2Cx_FLT_STARTF; +#endif + i2cp->i2c->S = I2Cx_S_IICIF|I2Cx_S_ARBL; + + /* acquire the bus */ + /* check to see if we already have the bus */ + if(i2cp->i2c->C1 & I2Cx_C1_MST) { + /* send repeated start */ + i2cp->i2c->C1 |= I2Cx_C1_RSTA | I2Cx_C1_TX; + } else { + /* wait until the bus is released */ + /* TODO: implement timeout here */ + /* FIXME: should not use busy waiting! */ + while (i2cp->i2c->S & I2Cx_S_BUSY); + /* send START */ + i2cp->i2c->C1 |= I2Cx_C1_MST|I2Cx_C1_TX; + } + /* send slave address */ i2cp->i2c->D = addr << 1 | op; + /* wait for the ISR to signal that the transmission (or receive if no transmission) phase is complete */ msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE); /* FIXME */ //if (i2cp->i2c->S & I2Cx_S_RXAK) // i2cp->errors |= I2C_ACK_FAILURE; - if (msg == MSG_OK && txbuf != NULL && rxbuf != NULL && rxbytes > 0) { + /* the transmitting (or receiving if no transmission) phase has finished, + * do we expect to receive something? */ + if (msg == MSG_OK && rxbuf != NULL && rxbytes > 0 && i2cp->rxidx < rxbytes) { + /* send repeated start */ i2cp->i2c->C1 |= I2Cx_C1_RSTA; /* FIXME */ - while (!(i2cp->i2c->S & I2Cx_S_BUSY)); + // while (!(i2cp->i2c->S & I2Cx_S_BUSY)); - i2cp->intstate = STATE_DUMMY; + i2cp->intstate = STATE_RECV; i2cp->i2c->D = i2cp->addr << 1 | 1; msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE); } + /* release bus - RX mode, send STOP */ + // other kinetis I2C drivers wait here for 1us. is this needed? i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST); /* FIXME */ - while (i2cp->i2c->S & I2Cx_S_BUSY); + // while (i2cp->i2c->S & I2Cx_S_BUSY); return msg; } @@ -373,7 +460,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - i2cp->intstate = STATE_DUMMY; + i2cp->intstate = STATE_RECV; return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout); } -- cgit v1.2.3 From 0a37322265bb0e109d8f4a840ccc1ccbb19ffdfa Mon Sep 17 00:00:00 2001 From: flabbergast Date: Mon, 18 Apr 2016 22:53:11 +0100 Subject: [KINETIS] I2C driver: implement timeout. --- os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 31 +++++++++++++++++++++++++------ os/hal/ports/KINETIS/LLD/hal_i2c_lld.h | 7 +++++++ 2 files changed, 32 insertions(+), 6 deletions(-) (limited to 'os') diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index 0831eac..6085941 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -363,8 +363,8 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - (void)timeout; msg_t msg; + systime_t start, end; uint8_t op = (i2cp->intstate == STATE_SEND) ? 0 : 1; @@ -394,10 +394,29 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* send repeated start */ i2cp->i2c->C1 |= I2Cx_C1_RSTA | I2Cx_C1_TX; } else { + /* unlock during the wait, so that tasks with + * higher priority can get attention */ + osalSysUnlock(); + /* wait until the bus is released */ - /* TODO: implement timeout here */ - /* FIXME: should not use busy waiting! */ - while (i2cp->i2c->S & I2Cx_S_BUSY); + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT); + + while(true) { + osalSysLock(); + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if(!(i2cp->i2c->S & I2Cx_S_BUSY)) + break; + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) { + return MSG_TIMEOUT; + } + osalSysUnlock(); + } + /* send START */ i2cp->i2c->C1 |= I2Cx_C1_MST|I2Cx_C1_TX; } @@ -406,7 +425,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->i2c->D = addr << 1 | op; /* wait for the ISR to signal that the transmission (or receive if no transmission) phase is complete */ - msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE); + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); /* FIXME */ //if (i2cp->i2c->S & I2Cx_S_RXAK) @@ -423,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_RECV; i2cp->i2c->D = i2cp->addr << 1 | 1; - msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE); + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); } /* release bus - RX mode, send STOP */ diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h index a7214c5..2b25df2 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h @@ -77,6 +77,13 @@ #define KINETIS_I2C_I2C1_PRIORITY 12 #endif +/** + * @brief Timeout for external clearing BUSY bus (in ms). + */ +#if !defined(KINETIS_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) +#define KINETIS_I2C_BUSY_TIMEOUT 50 +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -- cgit v1.2.3 From 2897589bf3b8fbbc2bfbda787bd42aa6b71b7bff Mon Sep 17 00:00:00 2001 From: flabbergast Date: Tue, 19 Apr 2016 09:57:00 +0100 Subject: [KINETIS] Fix I2C clock divisor computation. --- os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'os') diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index 6085941..ce59627 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -80,9 +80,9 @@ void config_frequency(I2CDriver *i2cp) { uint16_t best, diff; if (i2cp->config != NULL) - divisor = KINETIS_SYSCLK_FREQUENCY / i2cp->config->clock; + divisor = KINETIS_BUSCLK_FREQUENCY / i2cp->config->clock; else - divisor = KINETIS_SYSCLK_FREQUENCY / 100000; + divisor = KINETIS_BUSCLK_FREQUENCY / 100000; best = ~0; index = 0; -- cgit v1.2.3 From 9107b150b0d1fd5a2bdcc080b3493aefd8c56b46 Mon Sep 17 00:00:00 2001 From: flabbergast Date: Tue, 19 Apr 2016 21:51:34 +0100 Subject: [KINETIS] Add I2C workaround for KL27Z. --- os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 67 +++++++++++++++++++++++++++++++++- os/hal/ports/KINETIS/LLD/hal_i2c_lld.h | 10 ++++- 2 files changed, 74 insertions(+), 3 deletions(-) (limited to 'os') diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index ce59627..c6b3d11 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -127,8 +127,20 @@ static void serve_interrupt(I2CDriver *i2cp) { i2c->S |= I2Cx_S_ARBL; /* TODO: may need to do more here, reset bus? */ /* Perhaps clear MST? */ + } + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + else if ((i2cp->rsta_workaround == RSTA_WORKAROUND_ON) && (i2cp->i2c->FLT & I2Cx_FLT_STARTF)) { + i2cp->rsta_workaround = RSTA_WORKAROUND_OFF; + /* clear+disable STARTF/STOPF interrupts and wake up the thread */ + i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF; + i2cp->i2c->FLT &= ~I2Cx_FLT_SSIE; + i2c->S |= I2Cx_S_IICIF; + _i2c_wakeup_isr(i2cp); + } +#endif /* KL27Z RST workaround */ - } else if (i2c->S & I2Cx_S_TCF) { + else if (i2c->S & I2Cx_S_TCF) { /* just completed byte transfer */ if (i2c->C1 & I2Cx_C1_TX) { /* the byte was transmitted */ @@ -213,7 +225,6 @@ static void serve_interrupt(I2CDriver *i2cp) { } } /* possibly check other interrupt flags here */ - } else { /* slave */ @@ -379,6 +390,10 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->rxbytes = rxbytes; i2cp->rxidx = 0; +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + i2cp->rsta_workaround = RSTA_WORKAROUND_OFF; +#endif /* KL27Z RST workaround */ + /* clear status flags */ #if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */ i2cp->i2c->FLT |= I2Cx_FLT_STOPF; @@ -391,8 +406,34 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* acquire the bus */ /* check to see if we already have the bus */ if(i2cp->i2c->C1 & I2Cx_C1_MST) { + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + /* need to wait for STARTF interrupt after issuing repeated start, + * otherwise the double buffering mechanism sends the last sent byte + * instead of the slave address. + * https://community.freescale.com/thread/377611 + */ + i2cp->rsta_workaround = RSTA_WORKAROUND_ON; + /* clear any interrupt bits and enable STARTF/STOPF interrupts */ + i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF; + i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL; + i2cp->i2c->FLT |= I2Cx_FLT_SSIE; +#endif /* KL27Z RST workaround */ + /* send repeated start */ i2cp->i2c->C1 |= I2Cx_C1_RSTA | I2Cx_C1_TX; + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + /* wait for the STARTF interrupt */ + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); + /* abort if this didn't go well (timed out) */ + if (msg != MSG_OK) { + /* release bus - RX mode, send STOP */ + i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST); + return msg; + } +#endif /* KL27Z RST workaround */ + } else { /* unlock during the wait, so that tasks with * higher priority can get attention */ @@ -434,8 +475,30 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* the transmitting (or receiving if no transmission) phase has finished, * do we expect to receive something? */ if (msg == MSG_OK && rxbuf != NULL && rxbytes > 0 && i2cp->rxidx < rxbytes) { + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + /* the same KL27Z RST workaround as above */ + i2cp->rsta_workaround = RSTA_WORKAROUND_ON; + /* clear any interrupt bits and enable STARTF/STOPF interrupts */ + i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF; + i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL; + i2cp->i2c->FLT |= I2Cx_FLT_SSIE; +#endif /* KL27Z RST workaround */ + /* send repeated start */ i2cp->i2c->C1 |= I2Cx_C1_RSTA; + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + /* wait for the STARTF interrupt */ + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); + /* abort if this didn't go well (timed out) */ + if (msg != MSG_OK) { + /* release bus - RX mode, send STOP */ + i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST); + return msg; + } +#endif /* KL27Z RST workaround */ + /* FIXME */ // while (!(i2cp->i2c->S & I2Cx_S_BUSY)); diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h index 2b25df2..3576b60 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h @@ -34,7 +34,11 @@ #define STATE_STOP 0x00 #define STATE_SEND 0x01 #define STATE_RECV 0x02 -#define STATE_DUMMY 0x03 + +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ +#define RSTA_WORKAROUND_OFF 0x00 +#define RSTA_WORKAROUND_ON 0x01 +#endif /* KL27Z RST workaround */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -188,6 +192,10 @@ struct I2CDriver { intstate_t intstate; /* @brief Low-level register access. */ I2C_TypeDef *i2c; +#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */ + /* @brief Auxiliary variable for KL27Z repeated start workaround. */ + intstate_t rsta_workaround; +#endif /* KL27Z RST workaround */ }; /*===========================================================================*/ -- cgit v1.2.3