From 424c7a2717fb6b2a847cec5c0060e3236f25e97f Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Wed, 14 Mar 2018 20:15:13 +0100
Subject: Fixed most testhal examples for STM32, updated configs using script.
Fixed deprecated MS2ST calls.
---
testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile | 25 ++--
testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf.h | 48 ++++++--
.../STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h | 77 ++++++++++++-
testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h | 63 +++++-----
.../STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h | 127 +++++++++++++++++++--
5 files changed, 274 insertions(+), 66 deletions(-)
(limited to 'testhal/STM32/STM32F4xx/FSMC_SDRAM')
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile
index c786de6..c1eae62 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile
@@ -15,7 +15,7 @@ endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
- USE_CPPOPT = -fno-rtti -std=c++11
+ USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
@@ -30,7 +30,7 @@ endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
- USE_LTO = no
+ USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
@@ -46,7 +46,7 @@ endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
- USE_SMART_BUILD = no
+ USE_SMART_BUILD = yes
endif
#
@@ -93,16 +93,18 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.m
# HAL-OSAL files (optional).
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/STM32/STM32F4xx/platform.mk
-include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Other files (optional).
-include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk
+#include $(CHIBIOS)/test/lib/test.mk
+#include $(CHIBIOS)/test/rt/rt_test.mk
+#include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here
-LDSCRIPT = $(STARTUPLD)/STM32F429xI.ld
+LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -114,14 +116,11 @@ CSRC = $(STARTUPSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(TESTSRC) \
- main.c \
- memcpy_dma.c \
- membench.c
+ main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
-CPPSRC = $(CHCPPSRC) \
- $(CHIBIOS_CONTRIB)/os/various/memtest.cpp
+CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
@@ -150,8 +149,6 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
- $(CHIBIOS)/os/various/cpp_wrappers \
- $(CHIBIOS)/os/various \
$(CHIBIOS_CONTRIB)/os/various
#
@@ -191,7 +188,7 @@ TOPT = -mthumb -DTHUMB
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here
-CPPWARN = -Wall -Wextra
+CPPWARN = -Wall -Wextra -Wundef
#
# Compiler settings
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf.h
index e690d15..95e89c1 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf.h
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -51,6 +51,13 @@
#define HAL_USE_CAN FALSE
#endif
+/**
+ * @brief Enables the cryptographic subsystem.
+ */
+#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
+#define HAL_USE_CRY FALSE
+#endif
+
/**
* @brief Enables the DAC subsystem.
*/
@@ -62,7 +69,7 @@
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
-#define HAL_USE_EXT TRUE
+#define HAL_USE_EXT FALSE
#endif
/**
@@ -114,6 +121,13 @@
#define HAL_USE_PWM FALSE
#endif
+/**
+ * @brief Enables the QSPI subsystem.
+ */
+#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
+#define HAL_USE_QSPI FALSE
+#endif
+
/**
* @brief Enables the RTC subsystem.
*/
@@ -146,14 +160,14 @@
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_SPI TRUE
+#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
-#define HAL_USE_UART TRUE
+#define HAL_USE_UART FALSE
#endif
/**
@@ -201,6 +215,28 @@
#define CAN_USE_SLEEP_MODE TRUE
#endif
+/*===========================================================================*/
+/* CRY driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the SW fall-back of the cryptographic driver.
+ * @details When enabled, this option, activates a fall-back software
+ * implementation for algorithms not supported by the underlying
+ * hardware.
+ * @note Fall-back implementations may not be present for all algorithms.
+ */
+#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
+#define HAL_CRY_USE_FALLBACK FALSE
+#endif
+
+/**
+ * @brief Makes the driver forcibly use the fall-back implementations.
+ */
+#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
+#define HAL_CRY_ENFORCE_FALLBACK FALSE
+#endif
+
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
@@ -376,10 +412,6 @@
#define USB_USE_WAIT FALSE
#endif
-/*===========================================================================*/
-/* Community drivers's includes */
-/*===========================================================================*/
-
#include "halconf_community.h"
#endif /* HALCONF_H */
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h
index 060481a..631bb9f 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h
@@ -28,7 +28,7 @@
* @brief Enables the FSMC subsystem.
*/
#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
-#define HAL_USE_FSMC TRUE
+#define HAL_USE_FSMC FALSE
#endif
/**
@@ -66,6 +66,48 @@
#define HAL_USE_RNG FALSE
#endif
+/**
+ * @brief Enables the EEPROM subsystem.
+ */
+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
+#define HAL_USE_EEPROM FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
+#define HAL_USE_TIMCAP FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
+#define HAL_USE_COMP FALSE
+#endif
+
+/**
+ * @brief Enables the QEI subsystem.
+ */
+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
+#define HAL_USE_QEI FALSE
+#endif
+
+/**
+ * @brief Enables the USBH subsystem.
+ */
+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
+#define HAL_USE_USBH FALSE
+#endif
+
+/**
+ * @brief Enables the USB_MSD subsystem.
+ */
+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
@@ -93,6 +135,39 @@
*/
#define ONEWIRE_USE_SEARCH_ROM TRUE
+/*===========================================================================*/
+/* QEI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables discard of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_DISCARD FALSE
+#endif
+
+/**
+ * @brief Enables min max of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_MINMAX FALSE
+#endif
+
+/*===========================================================================*/
+/* EEProm driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables 24xx series I2C eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE24XX FALSE
+ /**
+ * @brief Enables 25xx series SPI eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE25XX FALSE
+
#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h
index 4737002..25c1357 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -64,17 +64,35 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI16_PRIORITY 6
+#define STM32_IRQ_EXTI17_PRIORITY 15
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_PRIORITY 6
+#define STM32_IRQ_EXTI21_PRIORITY 15
+#define STM32_IRQ_EXTI22_PRIORITY 15
+
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
-#define STM32_ADC_USE_ADC2 FALSE
-#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_USE_ADC2 TRUE
+#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_ADC_ADC1_DMA_PRIORITY 3
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
@@ -103,24 +121,6 @@
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-/*
- * EXT driver system settings.
- */
-#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
-#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
-#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
-
/*
* GPT driver system settings.
*/
@@ -238,8 +238,8 @@
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
-#define STM32_SDC_WRITE_TIMEOUT_MS 250
-#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_WRITE_TIMEOUT_MS 1000
+#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
@@ -263,7 +263,7 @@
/*
* SPI driver system settings.
*/
-#define STM32_SPI_USE_SPI1 TRUE
+#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
@@ -294,7 +294,7 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USE_USART6 TRUE
+#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
@@ -305,20 +305,20 @@
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
-#define STM32_UART_USART6_IRQ_PRIORITY 6
+#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
-#define STM32_UART_USART6_DMA_PRIORITY 2
+#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
@@ -339,9 +339,6 @@
*/
#define STM32_WDG_USE_IWDG FALSE
-/*
- * header for community drivers.
- */
#include "mcuconf_community.h"
#endif /* MCUCONF_H */
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
index f60cbee..cf6a1ce 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
@@ -17,7 +17,7 @@
/*
* FSMC driver system settings.
*/
-#define STM32_FSMC_USE_FSMC1 TRUE
+#define STM32_FSMC_USE_FSMC1 FALSE
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
/*
@@ -25,13 +25,10 @@
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
-
-/*
- * FSMC SDRAM driver system settings.
- */
-#define STM32_USE_FSMC_SDRAM TRUE
-#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
-#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
+#define STM32_NAND_USE_EXT_INT FALSE
+#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_NAND_DMA_PRIORITY 0
+#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
/*
* FSMC SRAM driver system settings.
@@ -43,6 +40,116 @@
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
/*
- * FSMC PC card driver system settings.
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM FALSE
+
+/*
+ * TIMCAP driver system settings.
+ */
+#define STM32_TIMCAP_USE_TIM1 TRUE
+#define STM32_TIMCAP_USE_TIM2 FALSE
+#define STM32_TIMCAP_USE_TIM3 TRUE
+#define STM32_TIMCAP_USE_TIM4 TRUE
+#define STM32_TIMCAP_USE_TIM5 TRUE
+#define STM32_TIMCAP_USE_TIM8 TRUE
+#define STM32_TIMCAP_USE_TIM9 TRUE
+#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
+
+/*
+ * COMP driver system settings.
+ */
+#define STM32_COMP_USE_COMP1 TRUE
+#define STM32_COMP_USE_COMP2 TRUE
+#define STM32_COMP_USE_COMP3 TRUE
+#define STM32_COMP_USE_COMP4 TRUE
+#define STM32_COMP_USE_COMP5 TRUE
+#define STM32_COMP_USE_COMP6 TRUE
+#define STM32_COMP_USE_COMP7 TRUE
+
+#define STM32_COMP_USE_INTERRUPTS TRUE
+#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
+#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
+#define STM32_COMP_7_IRQ_PRIORITY 5
+
+#if STM32_COMP_USE_INTERRUPTS
+#define STM32_DISABLE_EXTI21_22_29_HANDLER
+#define STM32_DISABLE_EXTI30_32_HANDLER
+#define STM32_DISABLE_EXTI33_HANDLER
+#endif
+
+/*
+ * USBH driver system settings.
+ */
+#define STM32_OTG1_CHANNELS_NUMBER 8
+#define STM32_OTG2_CHANNELS_NUMBER 12
+
+#define STM32_USBH_USE_OTG1 1
+#define STM32_OTG1_RXFIFO_SIZE 1024
+#define STM32_OTG1_PTXFIFO_SIZE 128
+#define STM32_OTG1_NPTXFIFO_SIZE 128
+
+#define STM32_USBH_USE_OTG2 0
+#define STM32_OTG2_RXFIFO_SIZE 2048
+#define STM32_OTG2_PTXFIFO_SIZE 1024
+#define STM32_OTG2_NPTXFIFO_SIZE 1024
+
+#define STM32_USBH_MIN_QSPACE 4
+#define STM32_USBH_CHANNELS_NP 4
+
+/*
+ * CRC driver system settings.
+ */
+#define STM32_CRC_USE_CRC1 TRUE
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
+#define STM32_CRC_CRC1_DMA_PRIORITY 2
+#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
+
+#define CRCSW_USE_CRC1 FALSE
+#define CRCSW_CRC32_TABLE TRUE
+#define CRCSW_CRC16_TABLE TRUE
+#define CRCSW_PROGRAMMABLE TRUE
+
+/*
+ * EICU driver system settings.
+ */
+#define STM32_EICU_USE_TIM1 TRUE
+#define STM32_EICU_USE_TIM2 FALSE
+#define STM32_EICU_USE_TIM3 TRUE
+#define STM32_EICU_USE_TIM4 TRUE
+#define STM32_EICU_USE_TIM5 TRUE
+#define STM32_EICU_USE_TIM8 TRUE
+#define STM32_EICU_USE_TIM9 TRUE
+#define STM32_EICU_USE_TIM10 TRUE
+#define STM32_EICU_USE_TIM11 TRUE
+#define STM32_EICU_USE_TIM12 TRUE
+#define STM32_EICU_USE_TIM13 TRUE
+#define STM32_EICU_USE_TIM14 TRUE
+#define STM32_EICU_TIM1_IRQ_PRIORITY 7
+#define STM32_EICU_TIM2_IRQ_PRIORITY 7
+#define STM32_EICU_TIM3_IRQ_PRIORITY 7
+#define STM32_EICU_TIM4_IRQ_PRIORITY 7
+#define STM32_EICU_TIM5_IRQ_PRIORITY 7
+#define STM32_EICU_TIM8_IRQ_PRIORITY 7
+#define STM32_EICU_TIM9_IRQ_PRIORITY 7
+#define STM32_EICU_TIM10_IRQ_PRIORITY 7
+#define STM32_EICU_TIM11_IRQ_PRIORITY 7
+#define STM32_EICU_TIM12_IRQ_PRIORITY 7
+#define STM32_EICU_TIM13_IRQ_PRIORITY 7
+#define STM32_EICU_TIM14_IRQ_PRIORITY 7
+
+/*
+ * QEI driver system settings.
*/
-#define STM32_USE_FSMC_PCCARD FALSE
+#define STM32_QEI_USE_TIM1 TRUE
+#define STM32_QEI_USE_TIM2 FALSE
+#define STM32_QEI_USE_TIM3 TRUE
+#define STM32_QEI_TIM1_IRQ_PRIORITY 3
+#define STM32_QEI_TIM2_IRQ_PRIORITY 3
+#define STM32_QEI_TIM3_IRQ_PRIORITY 3
--
cgit v1.2.3