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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-12-15 21:22:31 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-12-15 21:22:31 +0000
commit188bf5766fe5faa425b1f66d7bd2cccb6ef52632 (patch)
treecb8c80e96de88d9d871062ad02aa2c75cbfcb05b
parentc6b288f985bd8ea78fca5828a1bc4c7041e0b577 (diff)
downloadChibiOS-188bf5766fe5faa425b1f66d7bd2cccb6ef52632.tar.gz
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2482 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--docs/reports/STM32F103-72-IAR.txt8
-rw-r--r--os/ports/IAR/ARMCMx/chcore_v7m.h6
-rw-r--r--readme.txt3
3 files changed, 10 insertions, 7 deletions
diff --git a/docs/reports/STM32F103-72-IAR.txt b/docs/reports/STM32F103-72-IAR.txt
index 858d63567..850ad2fd9 100644
--- a/docs/reports/STM32F103-72-IAR.txt
+++ b/docs/reports/STM32F103-72-IAR.txt
@@ -97,15 +97,15 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 216398 msgs/S, 432796 ctxswc/S
+--- Score : 215747 msgs/S, 431494 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 193652 msgs/S, 387304 ctxswc/S
+--- Score : 193653 msgs/S, 387306 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 193652 msgs/S, 387304 ctxswc/S
+--- Score : 193653 msgs/S, 387306 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
@@ -145,7 +145,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
---- System: 324 bytes
+--- System: 360 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h
index e43ebbd76..7f7112d45 100644
--- a/os/ports/IAR/ARMCMx/chcore_v7m.h
+++ b/os/ports/IAR/ARMCMx/chcore_v7m.h
@@ -60,7 +60,7 @@ struct intctx {
#endif
/**
- * @brief Platform dependent part of the @p chThdInit() API.
+ * @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
@@ -68,9 +68,9 @@ struct intctx {
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = pf; \
+ tp->p_ctx.r13->r4 = (void *)pf; \
tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = _port_thread_start; \
+ tp->p_ctx.r13->lr = (void *)_port_thread_start; \
}
/**
diff --git a/readme.txt b/readme.txt
index e94d15881..9ae3b49f8 100644
--- a/readme.txt
+++ b/readme.txt
@@ -64,6 +64,9 @@
*** Releases ***
*****************************************************************************
+*** 2.3.0 ***
+- NEW: ARM Cortex-Mx port for IAR compiler.
+
*** 2.1.6 ***
- NEW: Now the STM32 CAN driver puts the lower half word of the ESR
register in the upper half word of the can status word for easier