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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-22 12:38:21 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-22 12:38:21 +0000
commitda9678f49a11241924c18902f7169c818a3cf995 (patch)
tree9968624e8c93b3f9bd5cd869c16c719ed1eda8b0 /os/hal/platforms/STM32F4xx/hal_lld.c
parent3d37f49059ee718a3d71e164883373a8cb30d6d8 (diff)
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Provisional STM32F2xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3649 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index fa87998c5..6d78c32df 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -94,6 +94,11 @@ void stm32_clock_init(void) {
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
+ /* PWR initialization.*/
+ PWR->CR = STM32_VOS;
+ while (PWR->CSR & PWR_CSR_VOSRDY)
+ ; /* Waits until power regulator is stable. */
+
/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.*/
RCC->CR |= RCC_CR_HSION;