diff options
6 files changed, 104 insertions, 128 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile index fd027130d..1a4112fba 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -111,9 +111,9 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
-#include $(CHIBIOS)/test/lib/test.mk
-#include $(CHIBIOS)/test/rt/rt_test.mk
-#include $(CHIBIOS)/test/oslib/oslib_test.mk
+include $(CHIBIOS)/test/lib/test.mk
+include $(CHIBIOS)/test/rt/rt_test.mk
+include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32H743xI.ld
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch index c69b25933..9c728ae73 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch @@ -33,7 +33,7 @@ <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="RESERVED10-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED9-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RSR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED8-rcc-stm32_clock_init-(format)" val="4"/><content id="D3AMR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED7-rcc-stm32_clock_init-(format)" val="4"/><content id="GCR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED6-rcc-stm32_clock_init-(format)" val="4"/><content id="CSR-rcc-stm32_clock_init-(format)" val="4"/><content id="BDCR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED5-rcc-stm32_clock_init-(format)" val="4"/><content id="CICR-rcc-stm32_clock_init-(format)" val="4"/><content id="CIFR-rcc-stm32_clock_init-(format)" val="4"/><content id="CIER-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED4-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP2R-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP1R-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED3-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCKSELR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED2-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED1-rcc-stm32_clock_init-(format)" val="4"/><content id="CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED0-rcc-stm32_clock_init-(format)" val="4"/><content id="CRRCR-rcc-stm32_clock_init-(format)" val="4"/><content id="ICSCR-rcc-stm32_clock_init-(format)" val="4"/><content id="CR-rcc-stm32_clock_init-(format)" val="4"/><content id="rcc-stm32_clock_init-(format)" val="4"/><content id="r3-(format)" val="4"/><content id="r2-(format)" val="4"/><content id="delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)" val="4"/><content id="CR1-pwr-init_pwr-(format)" val="4"/><content id="CSR1-pwr-init_pwr-(format)" val="4"/><content id="CR2-pwr-init_pwr-(format)" val="4"/><content id="CR3-pwr-init_pwr-(format)" val="4"/><content id="MODER-null-stm32_gpio_init-(format)" val="4"/><content id="OTYPER-null-stm32_gpio_init-(format)" val="4"/><content id="OSPEEDR-null-stm32_gpio_init-(format)" val="4"/><content id="PUPDR-null-stm32_gpio_init-(format)" val="4"/><content id="IDR-null-stm32_gpio_init-(format)" val="4"/><content id="ODR-null-stm32_gpio_init-(format)" val="4"/><content id="BSRR-null-stm32_gpio_init-(format)" val="4"/><content id="LOCKR-null-stm32_gpio_init-(format)" val="4"/><content id="AFRL-null-stm32_gpio_init-(format)" val="4"/><content id="AFRH-null-stm32_gpio_init-(format)" val="4"/><content id="MODER-null-Thread1-(format)" val="4"/><content id="OTYPER-null-Thread1-(format)" val="4"/><content id="OSPEEDR-null-Thread1-(format)" val="4"/><content id="PUPDR-null-Thread1-(format)" val="4"/><content id="IDR-null-Thread1-(format)" val="4"/><content id="ODR-null-Thread1-(format)" val="4"/><content id="BSRR-null-Thread1-(format)" val="4"/><content id="LOCKR-null-Thread1-(format)" val="4"/><content id="AFRL-null-Thread1-(format)" val="4"/><content id="AFRH-null-Thread1-(format)" val="4"/></contentList>"/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="AFRH-null-Thread1-(format)" val="4"/><content id="AFRL-null-Thread1-(format)" val="4"/><content id="LOCKR-null-Thread1-(format)" val="4"/><content id="BSRR-null-Thread1-(format)" val="4"/><content id="ODR-null-Thread1-(format)" val="4"/><content id="IDR-null-Thread1-(format)" val="4"/><content id="PUPDR-null-Thread1-(format)" val="4"/><content id="OSPEEDR-null-Thread1-(format)" val="4"/><content id="OTYPER-null-Thread1-(format)" val="4"/><content id="MODER-null-Thread1-(format)" val="4"/><content id="AFRH-null-stm32_gpio_init-(format)" val="4"/><content id="AFRL-null-stm32_gpio_init-(format)" val="4"/><content id="LOCKR-null-stm32_gpio_init-(format)" val="4"/><content id="BSRR-null-stm32_gpio_init-(format)" val="4"/><content id="ODR-null-stm32_gpio_init-(format)" val="4"/><content id="IDR-null-stm32_gpio_init-(format)" val="4"/><content id="PUPDR-null-stm32_gpio_init-(format)" val="4"/><content id="OSPEEDR-null-stm32_gpio_init-(format)" val="4"/><content id="OTYPER-null-stm32_gpio_init-(format)" val="4"/><content id="MODER-null-stm32_gpio_init-(format)" val="4"/><content id="CR3-pwr-init_pwr-(format)" val="4"/><content id="CR2-pwr-init_pwr-(format)" val="4"/><content id="CSR1-pwr-init_pwr-(format)" val="4"/><content id="CR1-pwr-init_pwr-(format)" val="4"/><content id="delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)" val="4"/><content id="r2-(format)" val="4"/><content id="r3-(format)" val="4"/><content id="rcc-stm32_clock_init-(format)" val="4"/><content id="CR-rcc-stm32_clock_init-(format)" val="4"/><content id="ICSCR-rcc-stm32_clock_init-(format)" val="4"/><content id="CRRCR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED0-rcc-stm32_clock_init-(format)" val="4"/><content id="CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED1-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED2-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCKSELR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED3-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP1R-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP2R-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED4-rcc-stm32_clock_init-(format)" val="4"/><content id="CIER-rcc-stm32_clock_init-(format)" val="4"/><content id="CIFR-rcc-stm32_clock_init-(format)" val="4"/><content id="CICR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED5-rcc-stm32_clock_init-(format)" val="4"/><content id="BDCR-rcc-stm32_clock_init-(format)" val="4"/><content id="CSR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED6-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="GCR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED7-rcc-stm32_clock_init-(format)" val="4"/><content id="D3AMR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED8-rcc-stm32_clock_init-(format)" val="4"/><content id="RSR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED9-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED10-rcc-stm32_clock_init-(format)" val="4"/></contentList>"/> <stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> <stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="0x0"/> </memoryBlockExpressionItem> <memoryBlockExpressionItem> <expression text="0x11087000"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/> <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h index 5aec384f3..d7793e22c 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h @@ -146,7 +146,7 @@ * @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL FALSE
+#define HAL_USE_SERIAL TRUE
#endif
/**
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c index 13849bd2b..71ade98e0 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c @@ -16,8 +16,8 @@ #include "ch.h"
#include "hal.h"
-//#include "rt_test_root.h"
-//#include "oslib_test_root.h"
+#include "rt_test_root.h"
+#include "oslib_test_root.h"
/*
* This is a periodic thread that does absolutely nothing except flashing
@@ -54,7 +54,7 @@ int main(void) { /*
* Activates the serial driver 1 using the driver default configuration.
*/
-// sdStart(&SD1, NULL);
+ sdStart(&SD3, NULL);
/*
* Creates the example thread.
@@ -66,12 +66,10 @@ int main(void) { * sleeping in a loop and check the button state.
*/
while (1) {
-#if 0
- if (palReadLine(LINE_BUTTON_USER)) {
- test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);
- test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);
+ if (palReadLine(LINE_BUTTON)) {
+ test_execute((BaseSequentialStream *)&SD3, &rt_test_suite);
+ test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite);
}
-#endif
chThdSleepMilliseconds(500);
}
}
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index b347e8c83..4a1b10dcf 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -332,9 +332,9 @@ /*
* SERIAL driver system settings.
*/
-#define STM32_SERIAL_USE_USART1 TRUE
+#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
-#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_USART3 TRUE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 489030d3e..6d7ce589d 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -2280,149 +2280,127 @@ #endif
#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#if 0
+#if (STM32_USART16SEL == STM32_USART16SEL_PCLK2) || defined(__DOXYGEN__)
/**
- * @brief USART1 frequency.
+ * @brief USART1 clock.
*/
-#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
#define STM32_USART1CLK STM32_PCLK2
-#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
-#define STM32_USART1CLK STM32_SYSCLK
-#elif STM32_USART1SEL == STM32_USART1SEL_HSI
+
+/**
+ * @brief USART6 clock.
+ */
+#define STM32_USART6CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART16SEL_PLL2_Q_CK
+#define STM32_USART1CLK STM32_PLL2_Q_CK
+#define STM32_USART6CLK STM32_PLL2_Q_CK
+#elif STM32_USART16SEL == STM32_USART16SEL_PLL3_Q_CK
+#define STM32_USART1CLK STM32_PLL3_Q_CK
+#define STM32_USART6CLK STM32_PLL3_Q_CK
+#elif STM32_USART16SEL == STM32_USART16SEL_HSI_KER_CK
#define STM32_USART1CLK STM32_HSICLK
-#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART6CLK STM32_HSICLK
+#elif STM32_USART16SEL == STM32_USART16SEL_CSI_KER_CK
+#define STM32_USART1CLK STM32_CSICLK
+#define STM32_USART6CLK STM32_CSICLK
+#elif STM32_USART16SEL == STM32_USART16SEL_LSE_CK
#define STM32_USART1CLK STM32_LSECLK
+#define STM32_USART6CLK STM32_LSECLK
#else
-#error "invalid source selected for USART1 clock"
+#error "invalid source selected for STM32_USART16SEL clock"
#endif
+#if (STM32_USART234578SEL == STM32_USART234578SEL_PCLK1) || defined(__DOXYGEN__)
/**
- * @brief USART2 frequency.
+ * @brief USART2 clock.
*/
-#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART2CLK STM32_PCLK1
-#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
-#define STM32_USART2CLK STM32_SYSCLK
-#elif STM32_USART2SEL == STM32_USART2SEL_HSI
-#define STM32_USART2CLK STM32_HSICLK
-#elif STM32_USART2SEL == STM32_USART2SEL_LSE
-#define STM32_USART2CLK STM32_LSECLK
-#else
-#error "invalid source selected for USART2 clock"
-#endif
/**
- * @brief USART3 frequency.
+ * @brief USART3 clock.
*/
-#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART3CLK STM32_PCLK1
-#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
-#define STM32_USART3CLK STM32_SYSCLK
-#elif STM32_USART3SEL == STM32_USART3SEL_HSI
-#define STM32_USART3CLK STM32_HSICLK
-#elif STM32_USART3SEL == STM32_USART3SEL_LSE
-#define STM32_USART3CLK STM32_LSECLK
-#else
-#error "invalid source selected for USART3 clock"
-#endif
/**
- * @brief UART4 frequency.
+ * @brief USART4 clock.
*/
-#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_UART4CLK STM32_PCLK1
-#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
-#define STM32_UART4CLK STM32_SYSCLK
-#elif STM32_UART4SEL == STM32_UART4SEL_HSI
-#define STM32_UART4CLK STM32_HSICLK
-#elif STM32_UART4SEL == STM32_UART4SEL_LSE
-#define STM32_UART4CLK STM32_LSECLK
-#else
-#error "invalid source selected for UART4 clock"
-#endif
+#define STM32_USART4CLK STM32_PCLK1
/**
- * @brief UART5 frequency.
+ * @brief USART5 clock.
*/
-#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_UART5CLK STM32_PCLK1
-#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
-#define STM32_UART5CLK STM32_SYSCLK
-#elif STM32_UART5SEL == STM32_UART5SEL_HSI
-#define STM32_UART5CLK STM32_HSICLK
-#elif STM32_UART5SEL == STM32_UART5SEL_LSE
-#define STM32_UART5CLK STM32_LSECLK
-#else
-#error "invalid source selected for UART5 clock"
-#endif
+#define STM32_USART5CLK STM32_PCLK1
/**
- * @brief USART6 frequency.
+ * @brief USART7 clock.
*/
-#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__)
-#define STM32_USART6CLK STM32_PCLK2
-#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK
-#define STM32_USART6CLK STM32_SYSCLK
-#elif STM32_USART6SEL == STM32_USART6SEL_HSI
-#define STM32_USART6CLK STM32_HSICLK
-#elif STM32_USART6SEL == STM32_USART6SEL_LSE
-#define STM32_USART6CLK STM32_LSECLK
-#else
-#error "invalid source selected for USART6 clock"
-#endif
+#define STM32_USART7CLK STM32_PCLK1
/**
- * @brief UART7 frequency.
+ * @brief USART8 clock.
*/
-#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_UART7CLK STM32_PCLK1
-#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK
-#define STM32_UART7CLK STM32_SYSCLK
-#elif STM32_UART7SEL == STM32_UART7SEL_HSI
-#define STM32_UART7CLK STM32_HSICLK
-#elif STM32_UART7SEL == STM32_UART7SEL_LSE
-#define STM32_UART7CLK STM32_LSECLK
+#define STM32_USART8CLK STM32_PCLK2
+#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK
+#define STM32_USART2CLK STM32_PLL2_Q_CK
+#define STM32_USART3CLK STM32_PLL2_Q_CK
+#define STM32_USART4CLK STM32_PLL2_Q_CK
+#define STM32_USART5CLK STM32_PLL2_Q_CK
+#define STM32_USART7CLK STM32_PLL2_Q_CK
+#define STM32_USART8CLK STM32_PLL2_Q_CK
+#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL3_Q_CK
+#define STM32_USART2CLK STM32_PLL3_Q_CK
+#define STM32_USART3CLK STM32_PLL3_Q_CK
+#define STM32_USART4CLK STM32_PLL3_Q_CK
+#define STM32_USART5CLK STM32_PLL3_Q_CK
+#define STM32_USART7CLK STM32_PLL3_Q_CK
+#define STM32_USART8CLK STM32_PLL3_Q_CK
+#elif STM32_USART234578SEL == STM32_USART234578SEL_HSI_KER_CK
+#define STM32_USART2CLK STM32_HSICLK
+#define STM32_USART3CLK STM32_HSICLK
+#define STM32_USART4CLK STM32_HSICLK
+#define STM32_USART5CLK STM32_HSICLK
+#define STM32_USART7CLK STM32_HSICLK
+#define STM32_USART8CLK STM32_HSICLK
+#elif STM32_USART234578SEL == STM32_USART234578SEL_CSI_KER_CK
+#define STM32_USART2CLK STM32_CSICLK
+#define STM32_USART3CLK STM32_CSICLK
+#define STM32_USART4CLK STM32_CSICLK
+#define STM32_USART5CLK STM32_CSICLK
+#define STM32_USART7CLK STM32_CSICLK
+#define STM32_USART8CLK STM32_CSICLK
+#elif STM32_USART234578SEL == STM32_USART234578SEL_LSE_CK
+#define STM32_USART2CLK STM32_LSECLK
+#define STM32_USART3CLK STM32_LSECLK
+#define STM32_USART4CLK STM32_LSECLK
+#define STM32_USART6CLK STM32_LSECLK
+#define STM32_USART7CLK STM32_LSECLK
+#define STM32_USART8CLK STM32_LSECLK
#else
-#error "invalid source selected for UART7 clock"
+#error "invalid source selected for STM32_USART234578SEL clock"
#endif
-/**
- * @brief UART8 frequency.
- */
-#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_UART8CLK STM32_PCLK1
-#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK
-#define STM32_UART8CLK STM32_SYSCLK
-#elif STM32_UART8SEL == STM32_UART8SEL_HSI
-#define STM32_UART8CLK STM32_HSICLK
-#elif STM32_UART8SEL == STM32_UART8SEL_LSE
-#define STM32_UART8CLK STM32_LSECLK
-#else
-#error "invalid source selected for UART8 clock"
-#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#if 0
/**
* @brief I2C1 frequency.
*/
|