diff options
28 files changed, 5629 insertions, 131 deletions
diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 5f8c971fd..f5465985b 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -34,7 +34,24 @@ /*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
-
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+#define I2CD_NO_ERROR 0
+/** @brief Bus Error.*/
+#define I2CD_BUS_ERROR 0x01
+/** @brief Arbitration Lost (master mode).*/
+#define I2CD_ARBITRATION_LOST 0x02
+/** @brief Acknowledge Failure.*/
+#define I2CD_ACK_FAILURE 0x04
+/** @brief Overrun/Underrun.*/
+#define I2CD_OVERRUN 0x08
+/** @brief PEC Error in reception.*/
+#define I2CD_PEC_ERROR 0x10
+/** @brief Timeout or Tlow Error.*/
+#define I2CD_TIMEOUT 0x20
+/** @brief SMBus Alert.*/
+#define I2CD_SMB_ALERT 0x40
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -49,6 +66,9 @@ /*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
+#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
+#endif
/*===========================================================================*/
/* Driver data structures and types. */
@@ -58,78 +78,175 @@ * @brief Driver state machine possible states.
*/
typedef enum {
- I2C_UNINIT = 0, /**< Not initialized. */
- I2C_STOP = 1, /**< Stopped. */
- I2C_READY = 2, /**< Ready. */
- I2C_MREADY = 3, /**< START and address sent. */
- I2C_MTRANSMIT = 4, /**< Master transmitting. */
- I2C_MRECEIVE = 5, /**< Master receiving. */
- I2C_MERROR = 6 /**< Error condition. */
+ I2C_UNINIT = 0, /**< @brief Not initialized. */
+ I2C_STOP = 1, /**< @brief Stopped. */
+ I2C_READY = 2, /**< @brief Ready. */
+ I2C_ACTIVE = 3, /**< @brief In communication. */
+ I2C_COMPLETE = 4, /**< @brief Asynchronous operation complete. */
+
+ // slave part
+ I2C_SACTIVE = 10,
+ I2C_STRANSMIT = 11,
+ I2C_SRECEIVE = 12,
} i2cstate_t;
+
#include "i2c_lld.h"
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
+/**
+ * @brief I2C notification callback type.
+ * @details This callback invoked when byte transfer finish event occurs,
+ * No matter sending or reading. This function designed
+ * for sending (re)start or stop events to I2C bus from user level.
+ *
+ * If callback function is set to NULL - driver atomaticcaly
+ * generate stop condition after the transfer finish.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object triggering the
+ * callback
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the
+ * callback
+ */
+typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+
/**
- * @brief Read mode.
+ * @brief I2C error notification callback type.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object triggering the
+ * callback
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the
+ * callback
*/
-#define I2C_READ 1
+typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+
/**
- * @brief Write mode.
+ * @brief I2C transmission data block size.
*/
-#define I2C_WRITE 0
+typedef uint8_t i2cblock_t;
+
/**
- * @brief Seven bits addresses header builder.
+ * @brief Structure representing an I2C slave configuration.
+ * @details Each slave device has its own config structure with input and
+ * output buffers for temporally storing data.
+ */
+struct I2CSlaveConfig{
+ /**
+ * @brief Callback pointer.
+ * @note Transfer finished callback. Invoke when all data transferred, or
+ * by DMA buffer events
+ * If set to @p NULL then the callback is disabled.
+ */
+ i2ccallback_t id_callback;
+
+ /**
+ * @brief Callback pointer.
+ * @note This callback will be invoked when error condition occur.
+ * If set to @p NULL then the callback is disabled.
+ */
+ i2cerrorcallback_t id_err_callback;
+
+ /**
+ * @brief Receive and transmit buffers.
+ */
+ size_t txbytes;
+ size_t rxbytes;
+ i2cblock_t *rxbuf; /*!< Pointer to receive buffer. */
+ i2cblock_t *txbuf; /*!< Pointer to transmit buffer.*/
+ uint16_t slave_addr;
+ uint8_t nbit_address; /*!< Length of address (must be 7 or 10).*/
+ i2cflags_t errors;
+ i2cflags_t flags;
+ /* Status Change @p EventSource.*/
+ EventSource sevent;
+};
+
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+#if I2C_USE_WAIT || defined(__DOXYGEN__)
+/**
+ * @brief Waits for operation completion.
+ * @details This function waits for the driver to complete the current
+ * operation.
+ * @pre An operation must be running while the function is invoked.
+ * @note No more than one thread can wait on a I2C driver using
+ * this function.
*
- * @param[in] addr seven bits address value
- * @param[in] rw read/write flag
+ * @param[in] i2cp pointer to the @p I2CDriver object
*
- * @return A 16 bit value representing the header, the most
- * significant byte is always zero.
+ * @notapi
*/
-#define I2C_ADDR7(addr, rw) (uint16_t)((addr) << 1 | (rw))
+#define _i2c_wait_s(i2cp) { \
+ chDbgAssert((i2cp)->thread == NULL, \
+ "_i2c_wait(), #1", "already waiting"); \
+ (i2cp)->thread = chThdSelf(); \
+ chSchGoSleepS(THD_STATE_SUSPENDED); \
+}
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_isr(i2cp) { \
+ if ((i2cp)->thread != NULL) { \
+ Thread *tp = (i2cp)->thread; \
+ (i2cp)->thread = NULL; \
+ chSysLockFromIsr(); \
+ chSchReadyI(tp); \
+ chSysUnlockFromIsr(); \
+ } \
+}
+#else /* !I2C_USE_WAIT */
+#define _i2c_wait_s(i2cp)
+#define _i2c_wakeup_isr(i2cp)
+#endif /* !I2C_USE_WAIT */
/**
- * @brief Ten bits addresses header builder.
+ * @brief Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
*
- * @param[in] addr ten bits address value
- * @param[in] rw read/write flag
+ * @param[in] i2cp pointer to the @p I2CDriver object
*
- * @return A 16 bit value representing the header, the most
- * significant byte is the first one to be transmitted.
+ * @notapi
*/
-#define I2C_ADDR10(addr, rw) \
- (uint16_t)(0xF000 | \
- (((addr) & 0x0300) << 1) | \
- (((rw) << 8)) | \
- ((addr) & 0x00FF))
+#define _i2c_isr_code(i2cp, i2cscfg) { \
+ (i2cp)->id_state = I2C_COMPLETE; \
+ if(((i2cp)->id_slave_config)->id_callback) { \
+ ((i2cp)->id_slave_config)->id_callback(i2cp, i2cscfg); \
+ } \
+ _i2c_wakeup_isr(i2cp); \
+}
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-
#ifdef __cplusplus
extern "C" {
#endif
void i2cInit(void);
void i2cObjectInit(I2CDriver *i2cp);
- void i2cStart(I2CDriver *i2cp, const I2CConfig *config);
+ void i2cStart(I2CDriver *i2cp, I2CConfig *config);
void i2cStop(I2CDriver *i2cp);
- void i2cMasterStartI(I2CDriver *i2cp,
- uint16_t header,
- i2ccallback_t callback);
- void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback);
- void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback);
- void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
- i2ccallback_t callback);
- void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf,
- i2ccallback_t callback);
+ void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+ void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+ void i2cMasterStart(I2CDriver *i2cp);
+ void i2cMasterStop(I2CDriver *i2cp);
+ void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask);
+
#if I2C_USE_MUTUAL_EXCLUSION
void i2cAcquireBus(I2CDriver *i2cp);
void i2cReleaseBus(I2CDriver *i2cp);
diff --git a/os/hal/include/i2c_albi.h b/os/hal/include/i2c_albi.h new file mode 100644 index 000000000..30ec38548 --- /dev/null +++ b/os/hal/include/i2c_albi.h @@ -0,0 +1,185 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file i2c.h
+ * @brief I2C Driver macros and structures.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef I2C_H_
+#define I2C_H_
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+#define I2CD_NO_ERROR 0
+/** @brief Bus Error.*/
+#define I2CD_BUS_ERROR 0x01
+/** @brief Arbitration Lost (master mode).*/
+#define I2CD_ARBITRATION_LOST 0x02
+/** @brief Acknowledge Failure.*/
+#define I2CD_ACK_FAILURE 0x04
+/** @brief Overrun/Underrun.*/
+#define I2CD_OVERRUN 0x08
+/** @brief PEC Error in reception.*/
+#define I2CD_PEC_ERROR 0x10
+/** @brief Timeout or Tlow Error.*/
+#define I2CD_TIMEOUT 0x20
+/** @brief SMBus Alert.*/
+#define I2CD_SMB_ALERT 0x40
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(I2C_USE_WAIT) || defined(__DOXYGEN__)
+#define I2C_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
+#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
+#endif
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ I2C_UNINIT = 0, /**< @brief Not initialized. */
+ I2C_STOP = 1, /**< @brief Stopped. */
+ I2C_READY = 2, /**< @brief Ready. */
+ I2C_ACTIVE = 3, /**< @brief In communication. */
+ I2C_COMPLETE = 4 /**< @brief Asynchronous operation complete. */
+} i2cstate_t;
+
+#include "i2c_lld.h"
+
+#if I2C_USE_WAIT || defined(__DOXYGEN__)
+/**
+ * @brief Waits for operation completion.
+ * @details This function waits for the driver to complete the current
+ * operation.
+ * @pre An operation must be running while the function is invoked.
+ * @note No more than one thread can wait on a I2C driver using
+ * this function.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wait_s(i2cp) { \
+ chDbgAssert((i2cp)->thread == NULL, \
+ "_i2c_wait(), #1", "already waiting"); \
+ (i2cp)->thread = chThdSelf(); \
+ chSchGoSleepS(THD_STATE_SUSPENDED); \
+}
+
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_isr(i2cp) { \
+ if ((i2cp)->thread != NULL) { \
+ Thread *tp = (i2cp)->thread; \
+ (i2cp)->thread = NULL; \
+ chSysLockFromIsr(); \
+ chSchReadyI(tp); \
+ chSysUnlockFromIsr(); \
+ } \
+}
+#else /* !I2C_USE_WAIT */
+#define _i2c_wait_s(i2cp)
+#define _i2c_wakeup_isr(i2cp)
+#endif /* !I2C_USE_WAIT */
+
+/**
+ * @brief Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_isr_code(i2cp) { \
+ (i2cp)->state = I2C_COMPLETE; \
+ if((i2cp)->endcb) { \
+ (i2cp)->endcb(i2cp); \
+ } \
+ _i2c_wakeup_isr(i2cp); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2cInit(void);
+ void i2cObjectInit(I2CDriver *i2cp);
+ void i2cStart(I2CDriver *i2cp, const I2CConfig *config);
+ void i2cStop(I2CDriver *i2cp);
+ void i2cMasterTransmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf);
+ void i2cMasterReceive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf);
+ void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask);
+ i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp);
+ uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp);
+
+#if I2C_USE_MUTUAL_EXCLUSION
+ void i2cAcquireBus(I2CDriver *i2cp);
+ void i2cReleaseBus(I2CDriver *i2cp);
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* CH_HAL_USE_I2C */
+
+#endif /* I2C_H_ */
diff --git a/os/hal/include/i2c_brts.h b/os/hal/include/i2c_brts.h new file mode 100644 index 000000000..a01606a18 --- /dev/null +++ b/os/hal/include/i2c_brts.h @@ -0,0 +1,248 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file i2c.h
+ * @brief I2C Driver macros and structures.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ I2C_UNINIT = 0, /**< Not initialized. */
+ I2C_STOP = 1, /**< Stopped. */
+ I2C_READY = 2, /**< Ready. Start condition generated. */
+ I2C_MACTIVE = 3, /**< I2C configured and waiting start cond. */
+ I2C_10BIT_HANDSHAKE = 4, /**< 10-bit address sending */
+ I2C_MWAIT_ADDR_ACK = 5, /**< Waiting ACK on address sending. */
+ I2C_MTRANSMIT = 6, /**< Master transmitting. */
+ I2C_MRECEIVE = 7, /**< Master receiving. */
+ I2C_MWAIT_TF = 8, /**< Master wait Transmission Finished */
+ I2C_MERROR = 9, /**< Error condition. */
+
+ // slave part
+ I2C_SACTIVE = 10,
+ I2C_STRANSMIT = 11,
+ I2C_SRECEIVE = 12,
+} i2cstate_t;
+
+
+#include "i2c_lld.h"
+
+/**
+ * @brief I2C notification callback type.
+ * @details This callback invoked when byte transfer finish event occurs,
+ * No matter sending or reading. This function designed
+ * for sending (re)start or stop events to I2C bus from user level.
+ *
+ * If callback function is set to NULL - driver atomaticcaly
+ * generate stop condition after the transfer finish.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object triggering the
+ * callback
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the
+ * callback
+ */
+typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+
+
+/**
+ * @brief I2C error notification callback type.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object triggering the
+ * callback
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the
+ * callback
+ */
+typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+
+
+/**
+ * @brief I2C transmission data block size.
+ */
+typedef uint8_t i2cblock_t;
+
+
+/**
+ * @brief Structure representing an I2C slave configuration.
+ * @details Each slave device has its own config structure with input and
+ * output buffers for temporally storing data.
+ */
+struct I2CSlaveConfig{
+ /**
+ * @brief Callback pointer.
+ * @note Transfer finished callback. Invoke when all data transferred, or
+ * by DMA buffer events
+ * If set to @p NULL then the callback is disabled.
+ */
+ i2ccallback_t id_callback;
+
+ /**
+ * @brief Callback pointer.
+ * @note This callback will be invoked when error condition occur.
+ * If set to @p NULL then the callback is disabled.
+ */
+ i2cerrorcallback_t id_err_callback;
+
+ /**
+ * @brief Receive and transmit buffers.
+ */
+ i2cblock_t *rxbuf; /*!< Pointer to receive buffer. */
+ size_t rxdepth; /*!< Depth of buffer. */
+ size_t rxbytes; /*!< Number of bytes to be receive in one transmission. */
+ size_t rxbufhead; /*!< Pointer to current data byte. */
+
+ i2cblock_t *txbuf; /*!< Pointer to transmit buffer.*/
+ size_t txdepth; /*!< Depth of buffer. */
+ size_t txbytes; /*!< Number of bytes to be transmit in one transmission. */
+ size_t txbufhead; /*!< Pointer to current data byte. */
+
+ /**
+ * @brief Contain slave address and some flags.
+ * @details Bits 0..9 contain slave address in 10-bit mode.
+ *
+ * Bits 0..6 contain slave address in 7-bit mode.
+ *
+ * Bits 10..14 are not used in 10-bit mode.
+ * Bits 7..14 are not used in 7-bit mode.
+ *
+ * Bit 15 is used to switch between 10-bit and 7-bit modes
+ * (0 denotes 7-bit mode).
+ */
+ uint16_t address;
+
+ /**
+ * @brief Boolean flag for dealing with start/stop conditions.
+ * @note This flag destined to use in callback functions. It place here
+ * for convenience and flexibility reasons, but you can use your
+ * own variable from user level code.
+ */
+ bool_t restart;
+
+
+#if I2C_USE_WAIT
+ /**
+ * @brief Thread waiting for I/O completion.
+ */
+ Thread *thread;
+#endif /* I2C_USE_WAIT */
+};
+
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Read mode.
+ */
+#define I2C_READ 1
+
+/**
+ * @brief Write mode.
+ */
+#define I2C_WRITE 0
+
+/**
+ * @brief Seven bits addresses header builder.
+ *
+ * @param[in] addr seven bits address value
+ * @param[in] rw read/write flag
+ *
+ * @return A 16 bit value representing the header, the most
+ * significant byte is always zero.
+ */
+#define I2C_ADDR7(addr, rw) (uint16_t)((addr) << 1 | (rw))
+
+
+/**
+ * @brief Ten bits addresses header builder.
+ *
+ * @param[in] addr ten bits address value
+ * @param[in] rw read/write flag
+ *
+ * @return A 16 bit value representing the header, the most
+ * significant byte is the first one to be transmitted.
+ */
+#define I2C_ADDR10(addr, rw) \
+ (uint16_t)(0xF000 | \
+ (((addr) & 0x0300) << 1) | \
+ (((rw) << 8)) | \
+ ((addr) & 0x00FF))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2cInit(void);
+ void i2cObjectInit(I2CDriver *i2cp);
+ void i2cStart(I2CDriver *i2cp, I2CConfig *config);
+ void i2cStop(I2CDriver *i2cp);
+ void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+ void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+ void i2cMasterStart(I2CDriver *i2cp);
+ void i2cMasterStop(I2CDriver *i2cp);
+
+#if I2C_USE_MUTUAL_EXCLUSION
+ void i2cAcquireBus(I2CDriver *i2cp);
+ void i2cReleaseBus(I2CDriver *i2cp);
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C */
+
+#endif /* _I2C_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c new file mode 100644 index 000000000..2c535b930 --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -0,0 +1,645 @@ +/** + * @file STM32/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented. + * @addtogroup STM32_I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "i2c_lld.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +static uint32_t i2c_get_event(I2CDriver *i2cp){ + uint32_t regSR1 = i2cp->id_i2c->SR1; + uint32_t regSR2 = i2cp->id_i2c->SR2; + /* return the last event value from I2C status registers */ + return (I2C_EV_MASK & (regSR1 | (regSR2 << 16))); +} + +static void i2c_serve_event_interrupt(I2CDriver *i2cp) { + static __IO uint8_t *txBuffp, *rxBuffp, *datap; + + I2C_TypeDef *dp = i2cp->id_i2c; + + switch(i2c_get_event(i2cp)) { + case I2C_EV5_MASTER_MODE_SELECT: + i2cp->id_slave_config->flags &= ~I2C_FLG_HEADER_SENT; + dp->DR = i2cp->slave_addr1; + break; + case I2C_EV9_MASTER_ADDR_10BIT: + if(i2cp->id_slave_config->flags & I2C_FLG_MASTER_RECEIVER) { + i2cp->slave_addr1 |= 0x01; + i2cp->id_slave_config->flags |= I2C_FLG_HEADER_SENT; +// i2cp->id_i2c->CR1 = (i2cp->id_i2c->CR1 & (~I2C_CR1_ACK)) | I2C_CR1_STOP; + } + dp->DR = i2cp->slave_addr2; + break; + + + //------------------------------------------------------------------------ + // Master Transmitter ---------------------------------------------------- + //------------------------------------------------------------------------ + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + if(i2cp->id_slave_config->flags & I2C_FLG_HEADER_SENT){ + dp->CR1 |= I2C_CR1_START; // re-send the start in 10-Bit address mode + break; + } + //Initialize the transmit buffer pointer + txBuffp = (uint8_t*)i2cp->id_slave_config->txbuf; + datap = txBuffp; + txBuffp++; + i2cp->id_slave_config->txbytes--; + /* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */ + if(i2cp->id_slave_config->txbytes == 0) { + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + } + //EV8_1 write the first data + dp->DR = *datap; + break; + case I2C_EV8_MASTER_BYTE_TRANSMITTING: + if(i2cp->id_slave_config->txbytes > 0) { + datap = txBuffp; + txBuffp++; + i2cp->id_slave_config->txbytes--; + if(i2cp->id_slave_config->txbytes == 0) { + /* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + } + dp->DR = *datap; + } + break; + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + /* if nothing to read then generate stop */ + if (i2cp->id_slave_config->rxbytes == 0){ + dp->CR1 |= I2C_CR1_STOP; // stop generation + /* Disable ITEVT In order to not have again a BTF IT */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; + /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/ + _i2c_isr_code(i2cp, i2cp->id_slave_config); + } + else{ + /* Disable ITEVT In order to not have again a BTF IT */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; + /* send restart and begin reading operations */ + i2c_lld_master_transceive(i2cp); + } + break; + + + //------------------------------------------------------------------------ + // Master Receiver ------------------------------------------------------- + //------------------------------------------------------------------------ + case I2C_EV6_MASTER_REC_MODE_SELECTED: + chSysLockFromIsr(); + switch(i2cp->id_slave_config->flags & EV6_SUBEV_MASK) { + case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: // only an single byte to receive + /* Clear ACK */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; + /* Program the STOP */ + dp->CR1 |= I2C_CR1_STOP; + break; + case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: // only two bytes to receive + /* Clear ACK */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; + /* Disable the ITBUF in order to have only the BTF interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + break; + } + chSysUnlockFromIsr(); + /* Initialize receive buffer pointer */ + rxBuffp = i2cp->id_slave_config->rxbuf; + break; + case I2C_EV7_MASTER_REC_BYTE_RECEIVED: + if(i2cp->id_slave_config->rxbytes != 3) { + /* Read the data register */ + *rxBuffp = dp->DR; + rxBuffp++; + i2cp->id_slave_config->rxbytes--; + switch(i2cp->id_slave_config->rxbytes){ + case 3: + /* Disable the ITBUF in order to have only the BTF interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + i2cp->id_slave_config->flags |= I2C_FLG_3BTR; + break; + case 0: + /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/ + _i2c_isr_code(i2cp, i2cp->id_slave_config); + break; + } + } + // when remaining 3 bytes do nothing, wait until RXNE and BTF are set (until 2 bytes are received) + break; + case I2C_EV7_MASTER_REC_BYTE_QUEUED: + switch(i2cp->id_slave_config->flags & EV7_SUBEV_MASK) { + case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS: + // DataN-2 and DataN-1 are received + chSysLockFromIsr(); + dp->CR2 |= I2C_CR2_ITBUFEN; + /* Clear ACK */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; + /* Read the DataN-2*/ + *rxBuffp = dp->DR; //This clear the RXE & BFT flags and launch the DataN reception in the shift register (ending the SCL stretch) + rxBuffp++; + /* Program the STOP */ + dp->CR1 |= I2C_CR1_STOP; + /* Read the DataN-1 */ + *rxBuffp = dp->DR; + chSysUnlockFromIsr(); + rxBuffp++; + /* Decrement the number of readed bytes */ + i2cp->id_slave_config->rxbytes -= 2; + i2cp->id_slave_config->flags = 0; + // ready for read DataN on the next EV7 + break; + case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: // only for case of two bytes to be received + // DataN-1 and DataN are received + chSysLockFromIsr(); + /* Program the STOP */ + dp->CR1 |= I2C_CR1_STOP; + /* Read the DataN-1*/ + *rxBuffp = dp->DR; + chSysUnlockFromIsr(); + rxBuffp++; + /* Read the DataN*/ + *rxBuffp = dp->DR; + i2cp->id_slave_config->rxbytes = 0; + i2cp->id_slave_config->flags = 0; + /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/ + _i2c_isr_code(i2cp, i2cp->id_slave_config); + break; + } + break; + } +} + +static void i2c_serve_error_interrupt(I2CDriver *i2cp) { + i2cflags_t flags; + I2C_TypeDef *reg; + + reg = i2cp->id_i2c; + flags = I2CD_NO_ERROR; + + if(reg->SR1 & I2C_SR1_BERR) { // Bus error + reg->SR1 &= ~I2C_SR1_BERR; + flags |= I2CD_BUS_ERROR; + } + if(reg->SR1 & I2C_SR1_ARLO) { // Arbitration lost + reg->SR1 &= ~I2C_SR1_ARLO; + flags |= I2CD_ARBITRATION_LOST; + } + if(reg->SR1 & I2C_SR1_AF) { // Acknowledge fail + reg->SR1 &= ~I2C_SR1_AF; + reg->CR1 |= I2C_CR1_STOP; // setting stop bit + flags |= I2CD_ACK_FAILURE; + } + if(reg->SR1 & I2C_SR1_OVR) { // Overrun + reg->SR1 &= ~I2C_SR1_OVR; + flags |= I2CD_OVERRUN; + } + if(reg->SR1 & I2C_SR1_PECERR) { // PEC error + reg->SR1 &= ~I2C_SR1_PECERR; + flags |= I2CD_PEC_ERROR; + } + if(reg->SR1 & I2C_SR1_TIMEOUT) { // SMBus Timeout + reg->SR1 &= ~I2C_SR1_TIMEOUT; + flags |= I2CD_TIMEOUT; + } + if(reg->SR1 & I2C_SR1_SMBALERT) { // SMBus alert + reg->SR1 &= ~I2C_SR1_SMBALERT; + flags |= I2CD_SMB_ALERT; + } + + if(flags != I2CD_NO_ERROR) { + // send communication end signal + _i2c_isr_code(i2cp, i2cp->id_slave_config); + chSysLockFromIsr(); + i2cAddFlagsI(i2cp, flags); + chSysUnlockFromIsr(); + } +} + + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + */ +CH_IRQ_HANDLER(VectorBC) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC0) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + */ +CH_IRQ_HANDLER(VectorC4) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC8) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief Low level I2C driver initialization. + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1 + RCC->APB1RSTR = 0; + i2cObjectInit(&I2CD1); + I2CD1.id_i2c = I2C1; +#endif + +#if STM32_I2C_USE_I2C2 + RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2 + RCC->APB1RSTR = 0; + i2cObjectInit(&I2CD2); + I2CD2.id_i2c = I2C2; +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_start(I2CDriver *i2cp) { + + /* If in stopped state then enables the I2C clock.*/ + if (i2cp->id_state == I2C_STOP) { +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); + NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); + RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + NVICEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); + NVICEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable + } +#endif + } + + /* I2C setup.*/ + i2cp->id_i2c->CR1 = I2C_CR1_SWRST; // reset i2c peripherial + i2cp->id_i2c->CR1 = 0; + + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN;// enable interrupts + i2cp->id_i2c->CR1 |= 1; // enable interface +} + +void i2c_lld_reset(I2CDriver *i2cp){ + chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), + "i2c_lld_reset: invalid state"); + + RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1 + RCC->APB1RSTR = 0; +} + + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_clock(I2CDriver *i2cp) { + volatile uint16_t regCCR, regCR2, freq, clock_div; + volatile uint16_t pe_bit_saved; + int32_t clock_speed = i2cp->id_config->ClockSpeed; + I2C_DutyCycle_t duty = i2cp->id_config->FastModeDutyCycle; + + chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), + "i2c_lld_set_clock"); + + /*---------------------------- CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + regCR2 = i2cp->id_i2c->CR2; + + /* Clear frequency FREQ[5:0] bits */ + regCR2 &= (uint16_t)~I2C_CR2_FREQ; + /* Set frequency bits depending on pclk1 value */ + freq = (uint16_t)(STM32_PCLK1 / 1000000); + chDbgCheck((freq >= 2) && (freq <= 36), + "i2c_lld_set_clock() : Peripheral clock freq. out of range"); + regCR2 |= freq; + i2cp->id_i2c->CR2 = regCR2; + + /*---------------------------- CCR Configuration ------------------------*/ + pe_bit_saved = (i2cp->id_i2c->CR1 & I2C_CR1_PE); + /* Disable the selected I2C peripheral to configure TRISE */ + i2cp->id_i2c->CR1 &= (uint16_t)~I2C_CR1_PE; + + /* Clear F/S, DUTY and CCR[11:0] bits */ + regCCR = 0; + clock_div = I2C_CCR_CCR; + /* Configure clock_div in standard mode */ + if (clock_speed <= 100000) { + chDbgAssert(duty == stdDutyCycle, + "i2c_lld_set_clock(), #1", "Invalid standard mode duty cycle"); + /* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); + /* Test if CCR value is under 0x4, and set the minimum allowed value */ + if (clock_div < 0x04) clock_div = 0x04; + /* Set clock_div value for standard mode */ + regCCR |= (clock_div & I2C_CCR_CCR); + /* Set Maximum Rise Time for standard mode */ + i2cp->id_i2c->TRISE = freq + 1; + } + /* Configure clock_div in fast mode */ + else if(clock_speed <= 400000) { + chDbgAssert((duty == fastDutyCycle_2) || (duty == fastDutyCycle_16_9), + "i2c_lld_set_clock(), #2", "Invalid fast mode duty cycle"); + if(duty == fastDutyCycle_2) { + /* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); + } + else if(duty == fastDutyCycle_16_9) { + /* Fast mode clock_div calculate: Tlow/Thigh = 16/9 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); + /* Set DUTY bit */ + regCCR |= I2C_CCR_DUTY; + } + /* Test if CCR value is under 0x1, and set the minimum allowed value */ + if(clock_div < 0x01) clock_div = 0x01; + /* Set clock_div value and F/S bit for fast mode*/ + regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); + /* Set Maximum Rise Time for fast mode */ + i2cp->id_i2c->TRISE = (freq * 300 / 1000) + 1; + } + chDbgAssert((clock_div <= I2C_CCR_CCR), + "i2c_lld_set_clock(), #3", "Too low clock clock speed selected"); + + /* Write to I2Cx CCR */ + i2cp->id_i2c->CCR = regCCR; + + /* restore the I2C peripheral enabled state */ + i2cp->id_i2c->CR1 |= pe_bit_saved; +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_opmode(I2CDriver *i2cp) { + I2C_opMode_t opmode = i2cp->id_config->opMode; + uint16_t regCR1; + + /*---------------------------- CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + regCR1 = i2cp->id_i2c->CR1; + switch(opmode){ + case opmodeI2C: + regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + case opmodeSMBusDevice: + regCR1 |= I2C_CR1_SMBUS; + regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); + break; + case opmodeSMBusHost: + regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + } + /* Write to I2Cx CR1 */ + i2cp->id_i2c->CR1 = regCR1; +} + +/** + * @brief Set own address. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_own_address(I2CDriver *i2cp) { + //TODO: dual address mode + + /*---------------------------- OAR1 Configuration -----------------------*/ + i2cp->id_i2c->OAR1 |= 1 << 14; + + if (&(i2cp->id_config->OwnAddress10) == NULL){// only 7-bit address + i2cp->id_i2c->OAR1 &= (~I2C_OAR1_ADDMODE); + i2cp->id_i2c->OAR1 |= i2cp->id_config->OwnAddress7 << 1; + } + else { + chDbgAssert((i2cp->id_config->OwnAddress10 < 1024), + "i2c_lld_set_own_address(), #1", "10-bit address longer then 10 bit") + i2cp->id_i2c->OAR1 |= I2C_OAR1_ADDMODE; + i2cp->id_i2c->OAR1 |= i2cp->id_config->OwnAddress10; + } +} + + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If in ready state then disables the I2C clock.*/ + if (i2cp->id_state == I2C_READY) { +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + NVICDisableVector(I2C1_EV_IRQn); + NVICDisableVector(I2C1_ER_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + NVICDisableVector(I2C2_EV_IRQn); + NVICDisableVector(I2C2_ER_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN; + } +#endif + } + i2cp->id_state = I2C_STOP; +} + +/** + * @brief Transmits data ever the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + */ +void i2c_lld_master_transmit(I2CDriver *i2cp) { + + // enable ERR, EVT & BUF ITs + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + + switch(i2cp->id_slave_config->nbit_address){ + case 7: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr <<1) & 0x00FE); // LSB = 0 -> write + break; + case 10: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header + i2cp->slave_addr1 |= 0xF0; // add the header bits with LSB = 0 -> write + i2cp->slave_addr2 = i2cp->id_slave_config->slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address + break; + } + + i2cp->id_slave_config->flags = 0; + i2cp->id_slave_config->errors = 0; + + i2cp->id_i2c->CR1 |= I2C_CR1_START; // send start bit + +#if !I2C_USE_WAIT + /* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */ + uint32_t timeout = 0xfffff; + while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout--) + ; +#endif /* I2C_USE_WAIT */ +} + + +/** + * @brief Receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + */ +void i2c_lld_master_receive(I2CDriver *i2cp){ + // enable ERR, EVT & BUF ITs + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // acknowledge returned + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + + switch(i2cp->id_slave_config->nbit_address){ + case 7: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr <<1) | 0x01); // LSB = 1 -> receive + break; + case 10: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header + i2cp->slave_addr1 |= 0xF0; // add the header bits (the LSB -> 1 will be add to second + i2cp->slave_addr2 = i2cp->id_slave_config->slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address + break; + } + + i2cp->id_slave_config->flags = I2C_FLG_MASTER_RECEIVER; + i2cp->id_slave_config->errors = 0; + + // Only one byte to be received + if(i2cp->id_slave_config->rxbytes == 1) { + i2cp->id_slave_config->flags |= I2C_FLG_1BTR; + } + // Only two bytes to be received + else if(i2cp->id_slave_config->rxbytes == 2) { + i2cp->id_slave_config->flags |= I2C_FLG_2BTR; + i2cp->id_i2c->CR1 |= I2C_CR1_POS; // Acknowledge Position + } + + i2cp->id_i2c->CR1 |= I2C_CR1_START; // send start bit + +#if !I2C_USE_WAIT + /* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */ + uint32_t timeout = 0xfffff; + while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout--) + ; +#endif /* I2C_USE_WAIT */ +} + + + +/** + * @brief + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + */ +void i2c_lld_master_transceive(I2CDriver *i2cp){ + // enable ERR, EVT & BUF ITs + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // acknowledge returned + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + + switch(i2cp->id_slave_config->nbit_address){ + case 7: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr <<1) | 0x01); // LSB = 1 -> receive + break; + case 10: + i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header + i2cp->slave_addr1 |= 0xF0; // add the header bits (the LSB -> 1 will be add to second + i2cp->slave_addr2 = i2cp->id_slave_config->slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address + break; + } + + i2cp->id_slave_config->flags = I2C_FLG_MASTER_RECEIVER; + i2cp->id_slave_config->errors = 0; + + // Only one byte to be received + if(i2cp->id_slave_config->rxbytes == 1) { + i2cp->id_slave_config->flags |= I2C_FLG_1BTR; + } + // Only two bytes to be received + else if(i2cp->id_slave_config->rxbytes == 2) { + i2cp->id_slave_config->flags |= I2C_FLG_2BTR; + i2cp->id_i2c->CR1 |= I2C_CR1_POS; // Acknowledge Position + } + + i2cp->id_i2c->CR1 |= I2C_CR1_START; // send start bit + +#if !I2C_USE_WAIT + /* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */ + uint32_t timeout = 0xfffff; + while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout--) + ; +#endif /* I2C_USE_WAIT */ +} + + +#endif // HAL_USE_I2C diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h new file mode 100644 index 000000000..00c6410fa --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -0,0 +1,236 @@ +/** + * @file STM32/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * @addtogroup STM32_I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 TRUE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 TRUE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 0xA0 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief EV5 */ +#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */ +/** @brief EV6 */ +#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */ +/** @brief EV7 */ +#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */ +#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/ +/** @brief EV8 */ +#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */ +/** @brief EV8_2 */ +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ +/** @brief EV9 */ +#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */ +#define I2C_EV_MASK 0x00FFFFFF + +#define I2C_FLG_1BTR 0x01 // Single byte to be received and processed +#define I2C_FLG_2BTR 0x02 // Two bytes to be received and processed +#define I2C_FLG_3BTR 0x04 // Last three received bytes to be processed +#define I2C_FLG_MASTER_RECEIVER 0x10 +#define I2C_FLG_HEADER_SENT 0x80 + +#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) +#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) + +#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +typedef enum { + opmodeI2C, + opmodeSMBusDevice, + opmodeSMBusHost, +} I2C_opMode_t; + +typedef enum { + stdDutyCycle, + fastDutyCycle_2, + fastDutyCycle_16_9, +} I2C_DutyCycle_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + I2C_opMode_t opMode; /*!< Specifies the I2C mode.*/ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. Must be set to a value lower than 400kHz */ + I2C_DutyCycle_t FastModeDutyCycle;/*!< Specifies the I2C fast mode duty cycle */ + uint8_t OwnAddress7; /*!< Specifies the first device 7-bit own address. */ + uint16_t OwnAddress10; /*!< Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */ + uint16_t Ack; /*!< Enables or disables the acknowledgement. */ + uint8_t nBitAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged */ +} I2CConfig; + + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Type of a structure representing an I2C slave config. + */ +typedef struct I2CSlaveConfig I2CSlaveConfig; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t id_state; +#if I2C_USE_WAIT + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; +#endif /* I2C_USE_WAIT */ +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex id_mutex; +#elif CH_USE_SEMAPHORES + Semaphore id_semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + /** + * @brief Current configuration data. + */ + I2CConfig *id_config; + /** + * @brief Current slave configuration data. + */ + I2CSlaveConfig *id_slave_config; + /** + * @brief RW-bit sent to slave. + */ + uint8_t rw_bit; + + uint8_t slave_addr1; // 7-bit address of the slave + uint8_t slave_addr2; // used in 10-bit address mode + uint8_t nbit_address; + + + /*********** End of the mandatory fields. **********************************/ + + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *id_i2c; +} ; + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#define i2c_lld_bus_is_busy(i2cp) \ + (i2cp->id_i2c->SR2 & I2C_SR2_BUSY) + + +/* Wait until BUSY flag is reset: a STOP has been generated on the bus + * signaling the end of transmission + */ +#define i2c_lld_wait_bus_free(i2cp) { \ + uint32_t tmo = 0xffff; \ + while((i2cp->id_i2c->SR2 & I2C_SR2_BUSY) && tmo--) \ + ; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** @cond never*/ +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void i2c_lld_init(void); +void i2c_lld_reset(I2CDriver *i2cp); +void i2c_lld_set_clock(I2CDriver *i2cp); +void i2c_lld_set_opmode(I2CDriver *i2cp); +void i2c_lld_set_own_address(I2CDriver *i2cp); +void i2c_lld_start(I2CDriver *i2cp); +void i2c_lld_stop(I2CDriver *i2cp); +void i2c_lld_master_transmit(I2CDriver *i2cp); +void i2c_lld_master_receive(I2CDriver *i2cp); +void i2c_lld_master_transceive(I2CDriver *i2cp); + +#ifdef __cplusplus +} +#endif +/** @endcond*/ + +#endif // CH_HAL_USE_I2C + +#endif // _I2C_LLD_H_ diff --git a/os/hal/platforms/STM32/i2c_lld_albi.c b/os/hal/platforms/STM32/i2c_lld_albi.c new file mode 100644 index 000000000..cd6a851db --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld_albi.c @@ -0,0 +1,574 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32/i2c_lld.c
+ * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented.
+ * @addtogroup STM32_I2C
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+
+static uint32_t i2c_get_event(I2CDriver *i2cp){
+ uint32_t regSR1 = i2cp->i2c_register->SR1;
+ uint32_t regSR2 = i2cp->i2c_register->SR2;
+ /* return the last event value from I2C status registers */
+ return (I2C_EV_MASK & (regSR1 | (regSR2 << 16)));
+}
+
+static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
+ static __IO uint8_t *txBuffp, *rxBuffp, *datap;
+
+ I2C_TypeDef *dp = i2cp->i2c_register;
+
+ switch(i2c_get_event(i2cp)) {
+ case I2C_EV5_MASTER_MODE_SELECT:
+ i2cp->flags &= ~I2C_FLG_HEADER_SENT;
+ dp->DR = i2cp->slave_addr1;
+ break;
+ case I2C_EV9_MASTER_ADDR_10BIT:
+ if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) {
+ i2cp->slave_addr1 |= 0x01;
+ i2cp->flags |= I2C_FLG_HEADER_SENT;
+ }
+ dp->DR = i2cp->slave_addr2;
+ break;
+ //------------------------------------------------------------------------
+ // Master Transmitter ----------------------------------------------------
+ //------------------------------------------------------------------------
+ case I2C_EV6_MASTER_TRA_MODE_SELECTED:
+ if(i2cp->flags & I2C_FLG_HEADER_SENT){
+ dp->CR1 |= I2C_CR1_START; // re-send the start in 10-Bit address mode
+ break;
+ }
+ //Initialize the transmit buffer pointer
+ txBuffp = (uint8_t*)i2cp->txbuf;
+ datap = txBuffp;
+ txBuffp++;
+ i2cp->remaining_bytes--;
+ /* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */
+ if(i2cp->remaining_bytes == 0) {
+ dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
+ }
+ //EV8_1 write the first data
+ dp->DR = *datap;
+ break;
+ case I2C_EV8_MASTER_BYTE_TRANSMITTING:
+ if(i2cp->remaining_bytes > 0) {
+ datap = txBuffp;
+ txBuffp++;
+ i2cp->remaining_bytes--;
+ if(i2cp->remaining_bytes == 0) {
+ /* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */
+ dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
+ }
+ dp->DR = *datap;
+ }
+ break;
+ case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
+ dp->CR1 |= I2C_CR1_STOP; // stop generation
+ /* Disable ITEVT In order to not have again a BTF IT */
+ dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
+ /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
+ _i2c_isr_code(i2cp);
+ break;
+ //------------------------------------------------------------------------
+ // Master Receiver -------------------------------------------------------
+ //------------------------------------------------------------------------
+ case I2C_EV6_MASTER_REC_MODE_SELECTED:
+ chSysLockFromIsr();
+ switch(i2cp->flags & EV6_SUBEV_MASK) {
+ case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: // only an single byte to receive
+ /* Clear ACK */
+ dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
+ /* Program the STOP */
+ dp->CR1 |= I2C_CR1_STOP;
+ break;
+ case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: // only two bytes to receive
+ /* Clear ACK */
+ dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
+ /* Disable the ITBUF in order to have only the BTF interrupt */
+ dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
+ break;
+ }
+ chSysUnlockFromIsr();
+ /* Initialize receive buffer pointer */
+ rxBuffp = i2cp->rxbuf;
+ break;
+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
+ if(i2cp->remaining_bytes != 3) {
+ /* Read the data register */
+ *rxBuffp = dp->DR;
+ rxBuffp++;
+ i2cp->remaining_bytes--;
+ switch(i2cp->remaining_bytes){
+ case 3:
+ /* Disable the ITBUF in order to have only the BTF interrupt */
+ dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
+ i2cp->flags |= I2C_FLG_3BTR;
+ break;
+ case 0:
+ /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
+ _i2c_isr_code(i2cp);
+ break;
+ }
+ }
+ // when remaining 3 bytes do nothing, wait until RXNE and BTF are set (until 2 bytes are received)
+ break;
+ case I2C_EV7_MASTER_REC_BYTE_QUEUED:
+ switch(i2cp->flags & EV7_SUBEV_MASK) {
+ case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
+ // DataN-2 and DataN-1 are received
+ chSysLockFromIsr();
+ dp->CR2 |= I2C_CR2_ITBUFEN;
+ /* Clear ACK */
+ dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
+ /* Read the DataN-2*/
+ *rxBuffp = dp->DR; //This clear the RXE & BFT flags and launch the DataN reception in the shift register (ending the SCL stretch)
+ rxBuffp++;
+ /* Program the STOP */
+ dp->CR1 |= I2C_CR1_STOP;
+ /* Read the DataN-1 */
+ *rxBuffp = dp->DR;
+ chSysUnlockFromIsr();
+ rxBuffp++;
+ /* Decrement the number of readed bytes */
+ i2cp->remaining_bytes -= 2;
+ i2cp->flags = 0;
+ // ready for read DataN on the next EV7
+ break;
+ case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: // only for case of two bytes to be received
+ // DataN-1 and DataN are received
+ chSysLockFromIsr();
+ /* Program the STOP */
+ dp->CR1 |= I2C_CR1_STOP;
+ /* Read the DataN-1*/
+ *rxBuffp = dp->DR;
+ chSysUnlockFromIsr();
+ rxBuffp++;
+ /* Read the DataN*/
+ *rxBuffp = dp->DR;
+ i2cp->remaining_bytes = 0;
+ i2cp->flags = 0;
+ /* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
+ _i2c_isr_code(i2cp);
+ break;
+ }
+ break;
+ }
+}
+
+static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
+ i2cflags_t flags;
+ I2C_TypeDef *reg;
+
+ reg = i2cp->i2c_register;
+ flags = I2CD_NO_ERROR;
+
+ if(reg->SR1 & I2C_SR1_BERR) { // Bus error
+ reg->SR1 &= ~I2C_SR1_BERR;
+ flags |= I2CD_BUS_ERROR;
+ }
+ if(reg->SR1 & I2C_SR1_ARLO) { // Arbitration lost
+ reg->SR1 &= ~I2C_SR1_ARLO;
+ flags |= I2CD_ARBITRATION_LOST;
+ }
+ if(reg->SR1 & I2C_SR1_AF) { // Acknowledge fail
+ reg->SR1 &= ~I2C_SR1_AF;
+ reg->CR1 |= I2C_CR1_STOP; // setting stop bit
+ flags |= I2CD_ACK_FAILURE;
+ }
+ if(reg->SR1 & I2C_SR1_OVR) { // Overrun
+ reg->SR1 &= ~I2C_SR1_OVR;
+ flags |= I2CD_OVERRUN;
+ }
+ if(reg->SR1 & I2C_SR1_PECERR) { // PEC error
+ reg->SR1 &= ~I2C_SR1_PECERR;
+ flags |= I2CD_PEC_ERROR;
+ }
+ if(reg->SR1 & I2C_SR1_TIMEOUT) { // SMBus Timeout
+ reg->SR1 &= ~I2C_SR1_TIMEOUT;
+ flags |= I2CD_TIMEOUT;
+ }
+ if(reg->SR1 & I2C_SR1_SMBALERT) { // SMBus alert
+ reg->SR1 &= ~I2C_SR1_SMBALERT;
+ flags |= I2CD_SMB_ALERT;
+ }
+
+ if(flags != I2CD_NO_ERROR) {
+ // send communication end signal
+ _i2c_isr_code(i2cp);
+ chSysLockFromIsr();
+ i2cAddFlagsI(i2cp, flags);
+ chSysUnlockFromIsr();
+ }
+}
+
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+/**
+ * @brief I2C1 event interrupt handler.
+ */
+CH_IRQ_HANDLER(I2C1_EV_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+ i2c_serve_event_interrupt(&I2CD1);
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief I2C1 error interrupt handler.
+ */
+CH_IRQ_HANDLER(I2C1_ER_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+ i2c_serve_error_interrupt(&I2CD1);
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+/**
+ * @brief I2C2 event interrupt handler.
+ */
+CH_IRQ_HANDLER(I2C2_EV_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+ i2c_serve_event_interrupt(&I2CD2);
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief I2C2 error interrupt handler.
+ */
+CH_IRQ_HANDLER(I2C2_ER_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+ i2c_serve_error_interrupt(&I2CD2);
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+void i2c_lld_reset(I2CDriver *i2cp){
+ chDbgCheck((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
+ "i2c_lld_reset: invalid state");
+
+ RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
+ RCC->APB1RSTR = 0;
+}
+
+void i2c_lld_set_clock(I2CDriver *i2cp, int32_t clock_speed, I2C_DutyCycle_t duty) {
+ volatile uint16_t regCCR, regCR2, freq, clock_div;
+ volatile uint16_t pe_bit_saved;
+
+ chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000),
+ "i2c_lld_set_clock");
+
+ /*---------------------------- CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ regCR2 = i2cp->i2c_register->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ regCR2 &= (uint16_t)~I2C_CR2_FREQ;
+ /* Set frequency bits depending on pclk1 value */
+ freq = (uint16_t)(STM32_PCLK1 / 1000000);
+ chDbgCheck((freq >= 2) && (freq <= 36),
+ "i2c_lld_set_clock() : Peripheral clock freq. out of range");
+ regCR2 |= freq;
+ i2cp->i2c_register->CR2 = regCR2;
+
+ /*---------------------------- CCR Configuration ------------------------*/
+ pe_bit_saved = (i2cp->i2c_register->CR1 & I2C_CR1_PE);
+ /* Disable the selected I2C peripheral to configure TRISE */
+ i2cp->i2c_register->CR1 &= (uint16_t)~I2C_CR1_PE;
+
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ regCCR = 0;
+ clock_div = I2C_CCR_CCR;
+ /* Configure clock_div in standard mode */
+ if (clock_speed <= 100000) {
+ chDbgAssert(duty == stdDutyCycle,
+ "i2c_lld_set_clock(), #3", "Invalid standard mode duty cycle");
+ /* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */
+ clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
+ /* Test if CCR value is under 0x4, and set the minimum allowed value */
+ if (clock_div < 0x04) clock_div = 0x04;
+ /* Set clock_div value for standard mode */
+ regCCR |= (clock_div & I2C_CCR_CCR);
+ /* Set Maximum Rise Time for standard mode */
+ i2cp->i2c_register->TRISE = freq + 1;
+ }
+ /* Configure clock_div in fast mode */
+ else if(clock_speed <= 400000) {
+ chDbgAssert((duty == fastDutyCycle_2) || (duty == fastDutyCycle_16_9),
+ "i2c_lld_set_clock(), #3", "Invalid fast mode duty cycle");
+ if(duty == fastDutyCycle_2) {
+ /* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */
+ clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
+ }
+ else if(duty == fastDutyCycle_16_9) {
+ /* Fast mode clock_div calculate: Tlow/Thigh = 16/9 */
+ clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
+ /* Set DUTY bit */
+ regCCR |= I2C_CCR_DUTY;
+ }
+ /* Test if CCR value is under 0x1, and set the minimum allowed value */
+ if(clock_div < 0x01) clock_div = 0x01;
+ /* Set clock_div value and F/S bit for fast mode*/
+ regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
+ /* Set Maximum Rise Time for fast mode */
+ i2cp->i2c_register->TRISE = (freq * 300 / 1000) + 1;
+ }
+ chDbgAssert((clock_div <= I2C_CCR_CCR),
+ "i2c_lld_set_clock(), #2", "Too low clock clock speed selected");
+
+ /* Write to I2Cx CCR */
+ i2cp->i2c_register->CCR = regCCR;
+
+ /* restore the I2C peripheral enabled state */
+ i2cp->i2c_register->CR1 |= pe_bit_saved;
+}
+
+void i2c_lld_set_opmode(I2CDriver *i2cp, I2C_opMode_t opmode) {
+ uint16_t regCR1;
+
+ /*---------------------------- CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ regCR1 = i2cp->i2c_register->CR1;
+ switch(opmode){
+ case opmodeI2C:
+ regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
+ break;
+ case opmodeSMBusDevice:
+ regCR1 |= I2C_CR1_SMBUS;
+ regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE);
+ break;
+ case opmodeSMBusHost:
+ regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
+ break;
+ }
+ /* Write to I2Cx CR1 */
+ i2cp->i2c_register->CR1 = regCR1;
+}
+
+void i2c_lld_set_own_address(I2CDriver *i2cp, int16_t address, int8_t nbit_addr) {
+ /*---------------------------- OAR1 Configuration -----------------------*/
+ /* Set the Own Address1 and bit number address acknowledged */
+ i2cp->i2c_register->OAR1 = address & I2C_OAR1_ADD0_9;
+ switch(nbit_addr) {
+ case 10:
+ i2cp->i2c_register->OAR1 |= I2C_OAR1_ADDMODE; // set ADDMODE bit and bit 14.
+ case 7:
+ i2cp->i2c_register->OAR1 |= I2C_OAR1_BIT14; // set only bit 14.
+ }
+}
+
+/**
+ * @brief Low level I2C driver initialization.
+ */
+void i2c_lld_init(void) {
+
+#if STM32_I2C_USE_I2C1
+ RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
+ RCC->APB1RSTR = 0;
+ i2cObjectInit(&I2CD1);
+ I2CD1.i2c_register = I2C1;
+#endif
+#if STM32_I2C_USE_I2C2
+ RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2
+ RCC->APB1RSTR = 0;
+ i2cObjectInit(&I2CD2);
+ I2CD2.i2c_register = I2C2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+ chDbgCheck((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
+ "i2c_lld_start: invalid state");
+
+ /* If in stopped state then enables the I2C clock.*/
+ if (i2cp->state == I2C_STOP) {
+#if STM32_I2C_USE_I2C1
+ if (&I2CD1 == i2cp) {
+ NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+ NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+ RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable
+ }
+#endif
+#if STM32_I2C_USE_I2C2
+ if (&I2CD2 == i2cp) {
+ NVICEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
+ NVICEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
+ RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable
+ }
+#endif
+ i2cp->i2c_register->CR1 |= I2C_CR1_PE; // enable I2C peripheral
+ }
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+ chDbgCheck((i2cp->state == I2C_READY),
+ "i2c_lld_stop: invalid state");
+
+ /* I2C disable.*/
+ i2cp->i2c_register->CR1 = 0;
+
+ /* If in ready state then disables the I2C clock.*/
+ if (i2cp->state == I2C_READY) {
+#if STM32_I2C_USE_I2C1
+ if (&I2CD1 == i2cp) {
+ NVICDisableVector(I2C1_EV_IRQn);
+ NVICDisableVector(I2C1_ER_IRQn);
+ RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
+ }
+#endif
+#if STM32_I2C_USE_I2C2
+ if (&I2CD2 == i2cp) {
+ NVICDisableVector(I2C2_EV_IRQn);
+ NVICDisableVector(I2C2_ER_IRQn);
+ RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Transmits data ever the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] n number of words to send
+ * @param[in] slave_addr1 the 7-bit address of the slave (should be aligned to left)
+ * @param[in] slave_addr2 used in 10 bit address mode
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ */
+void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf) {
+
+ // enable ERR, EVT & BUF ITs
+ i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
+ i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
+
+ switch(i2cp->nbit_address){
+ case 7:
+ i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); // LSB = 0 -> write
+ break;
+ case 10:
+ i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
+ i2cp->slave_addr1 |= 0xF0; // add the header bits with LSB = 0 -> write
+ i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
+ break;
+ }
+
+ i2cp->txbuf = txbuf;
+ i2cp->remaining_bytes = n;
+ i2cp->flags = 0;
+ i2cp->errors = 0;
+
+ i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
+
+#if !I2C_USE_WAIT
+ /* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
+ uint32_t tmo = 0xfffff;
+ while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
+ ;
+#endif /* I2C_USE_WAIT */
+}
+
+/**
+ * @brief Receives data from the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] slave_addr1 7-bit address of he slave
+ * @param[in] slave_addr2 used in 10-bit address mode
+ * @param[in] n number of words to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ */
+void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf) {
+ // enable ERR, EVT & BUF ITs
+ i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
+ i2cp->i2c_register->CR1 |= I2C_CR1_ACK; // acknowledge returned
+ i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
+
+ switch(i2cp->nbit_address){
+ case 7:
+ i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); // LSB = 1 -> receive
+ break;
+ case 10:
+ i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
+ i2cp->slave_addr1 |= 0xF0; // add the header bits (the LSB -> 1 will be add to second
+ i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
+ break;
+ }
+
+ i2cp->rxbuf = rxbuf;
+ i2cp->remaining_bytes = n;
+ i2cp->flags = I2C_FLG_MASTER_RECEIVER;
+ i2cp->errors = 0;
+
+ // Only one byte to be received
+ if(i2cp->remaining_bytes == 1) {
+ i2cp->flags |= I2C_FLG_1BTR;
+ }
+ // Only two bytes to be received
+ else if(i2cp->remaining_bytes == 2) {
+ i2cp->flags |= I2C_FLG_2BTR;
+ i2cp->i2c_register->CR1 |= I2C_CR1_POS; // Acknowledge Position
+ }
+
+ i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
+
+#if !I2C_USE_WAIT
+ /* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
+ uint32_t tmo = 0xfffff;
+ while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
+ ;
+#endif /* I2C_USE_WAIT */
+}
+
+#endif // HAL_USE_I2C
+
diff --git a/os/hal/platforms/STM32/i2c_lld_albi.h b/os/hal/platforms/STM32/i2c_lld_albi.h new file mode 100644 index 000000000..2b63afec9 --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld_albi.h @@ -0,0 +1,263 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+
+/**
+ * @file STM32/i2c_lld.h
+ * @brief STM32 I2C subsystem low level driver header.
+ * @addtogroup STM32_I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+#define I2C_OAR1_ADD0_9 ((uint16_t)0x03FF) /*!<Interface Address */
+#define I2C_OAR1_BIT14 ((uint16_t)0x4000) /*!<bit 14 should always be kept at 1. */
+
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C1 TRUE
+#endif
+
+/**
+ * @brief I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C2 TRUE
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ * @note @p BASEPRI_KERNEL >= @p STM32_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ */
+#if !defined(STM32_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C1_IRQ_PRIORITY 0xA0
+#endif
+
+/**
+ * @brief I2C2 interrupt priority level setting.
+ * @note @p BASEPRI_KERNEL >= @p STM32_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ */
+#if !defined(STM32_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C2_IRQ_PRIORITY 0xA0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/** @brief EV5 */
+#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */
+/** @brief EV6 */
+#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */
+/** @brief EV7 */
+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */
+#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/
+/** @brief EV8 */
+#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */
+/** @brief EV8_2 */
+#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
+/** @brief EV9 */
+#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */
+#define I2C_EV_MASK 0x00FFFFFF
+
+#define I2C_FLG_1BTR 0x01 // Single byte to be received and processed
+#define I2C_FLG_2BTR 0x02 // Two bytes to be received and processed
+#define I2C_FLG_3BTR 0x04 // Last three received bytes to be processed
+#define I2C_FLG_MASTER_RECEIVER 0x10
+#define I2C_FLG_HEADER_SENT 0x80
+
+#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
+#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
+
+#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
+#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER)
+#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
+#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Serial Driver condition flags type.
+ */
+typedef uint32_t i2cflags_t;
+
+typedef enum {
+ opmodeI2C,
+ opmodeSMBusDevice,
+ opmodeSMBusHost,
+} I2C_opMode_t;
+
+typedef enum {
+ stdDutyCycle,
+ fastDutyCycle_2,
+ fastDutyCycle_16_9,
+} I2C_DutyCycle_t;
+
+/**
+ * @brief Type of a structure representing an SPI driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief I2C notification callback type.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object triggering the
+ * callback
+ */
+typedef void (*i2ccallback_t)(I2CDriver *i2cp);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ I2C_opMode_t opMode; /*!< Specifies the I2C mode.*/
+
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency. Must be set to a value lower than 400kHz */
+
+ I2C_DutyCycle_t FastModeDutyCycle; /*!< Specifies the I2C fast mode duty cycle */
+
+ uint16_t OwnAddress1; /*!< Specifies the first device own address. Can be a 7-bit or 10-bit address. */
+
+ uint16_t Ack; /*!< Enables or disables the acknowledgement. */
+
+ uint8_t nBitAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged */
+
+} I2CConfig;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2cstate_t state;
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ i2ccallback_t endcb;
+#if I2C_USE_WAIT
+ /**
+ * @brief Thread waiting for I/O completion.
+ */
+ Thread *thread;
+#endif /* I2C_USE_WAIT */
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ Mutex mutex;
+#elif CH_USE_SEMAPHORES
+ Semaphore semaphore;
+#endif
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the I2Cx registers block.
+ */
+ I2C_TypeDef *i2c_register;
+ size_t remaining_bytes;
+ uint8_t *rxbuf;
+ uint8_t *txbuf;
+ uint8_t slave_addr1; // 7-bit address of the slave
+ uint8_t slave_addr2; // used in 10-bit address mode
+ uint8_t nbit_address;
+ i2cflags_t errors;
+ i2cflags_t flags;
+ /* Status Change @p EventSource.*/
+ EventSource sevent;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+#define i2c_lld_bus_is_busy(i2cp) \
+ (i2cp->i2c_register->SR2 & I2C_SR2_BUSY)
+
+
+/* Wait until BUSY flag is reset: a STOP has been generated on the bus
+ * signaling the end of transmission
+ */
+#define i2c_lld_wait_bus_free(i2cp) { \
+ uint32_t tmo = 0xffff; \
+ while((i2cp->i2c_register->SR2 & I2C_SR2_BUSY) && tmo--) \
+ ; \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/** @cond never*/
+#if STM32_I2C_USE_I2C1
+extern I2CDriver I2CD1;
+#endif
+
+#if STM32_I2C_USE_I2C2
+extern I2CDriver I2CD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void i2c_lld_init(void);
+void i2c_lld_reset(I2CDriver *i2cp);
+void i2c_lld_set_clock(I2CDriver *i2cp, int32_t clock_speed, I2C_DutyCycle_t duty);
+void i2c_lld_set_opmode(I2CDriver *i2cp, I2C_opMode_t opmode);
+void i2c_lld_set_own_address(I2CDriver *i2cp, int16_t address, int8_t nr_bit);
+void i2c_lld_start(I2CDriver *i2cp);
+void i2c_lld_stop(I2CDriver *i2cp);
+void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf);
+void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf);
+
+#ifdef __cplusplus
+}
+#endif
+/** @endcond*/
+
+#endif // CH_HAL_USE_I2C
+
+#endif // _I2C_LLD_H_
diff --git a/os/hal/platforms/STM32/i2c_lld_brts.c b/os/hal/platforms/STM32/i2c_lld_brts.c new file mode 100644 index 000000000..1ac7e4309 --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld_brts.c @@ -0,0 +1,626 @@ +/** + * @file STM32/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented. + * @addtogroup STM32_I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "i2c_lld.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Interrupt service routine. + * @details This function handle all ERROR interrupt conditions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +static void i2c_serve_error_interrupt(I2CDriver *i2cp) { + //TODO: more robust error handling + chSysLockFromIsr(); + i2cp->id_slave_config->id_err_callback(i2cp, i2cp->id_slave_config); + chSysUnlockFromIsr(); +} + +/* helper function, not API + * write bytes in DR register + * return TRUE if last byte written + */ +inline bool_t i2c_lld_txbyte(I2CDriver *i2cp) { +#define _txbufhead (i2cp->id_slave_config->txbufhead) +#define _txbytes (i2cp->id_slave_config->txbytes) +#define _txbuf (i2cp->id_slave_config->txbuf) + + if (_txbufhead < _txbytes){ + /* disable interrupt to avoid jumping to ISR */ + if ( _txbytes - _txbufhead == 1) + i2cp->id_i2c->CR2 &= (~I2C_CR2_ITBUFEN); + i2cp->id_i2c->DR = _txbuf[_txbufhead]; + (_txbufhead)++; + return(FALSE); + } + _txbufhead = 0; + return(TRUE); // last byte written +#undef _txbufhead +#undef _txbytes +#undef _txbuf +} + + +/* helper function, not API + * read bytes from DR register + * return TRUE if last byte read + */ +inline bool_t i2c_lld_rxbyte(I2CDriver *i2cp) { + // temporal variables +#define _rxbuf (i2cp->id_slave_config->rxbuf) +#define _rxbufhead (i2cp->id_slave_config->rxbufhead) +#define _rxbytes (i2cp->id_slave_config->rxbytes) + + /* In order to generate the non-acknowledge pulse after the last received + * data byte, the ACK bit must be cleared just after reading the second + * last data byte (after second last RxNE event). + */ + if (_rxbufhead < (_rxbytes - 1)){ + _rxbuf[_rxbufhead] = i2cp->id_i2c->DR; + if ((_rxbytes - _rxbufhead) <= 2){ + // clear ACK bit for automatically send NACK + i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK); + } + (_rxbufhead)++; + return(FALSE); + } + /* disable interrupt to avoid jumping to ISR */ + i2cp->id_i2c->CR2 &= (~I2C_CR2_ITBUFEN); + + _rxbuf[_rxbufhead] = i2cp->id_i2c->DR; // read last byte + _rxbufhead = 0; + return(TRUE); // last byte read + +#undef _rxbuf +#undef _rxbufhead +#undef _rxbytes +} + + +/** + * @brief Interrupt service routine. + * @details This function handle all regular interrupt conditions. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +static void i2c_serve_event_interrupt(I2CDriver *i2cp) { + +#if CH_DBG_ENABLE_CHECKS + // debug variables + int i = 0; + int n = 0; + int m = 0; +#endif + + /* In 10-bit addressing mode, + – To enter Transmitter mode, a master sends the header (11110xx0) and then the + slave address, (where xx denotes the two most significant bits of the address). + – To enter Receiver mode, a master sends the header (11110xx0) and then the + slave address. Then it should send a repeated Start condition followed by the + header (11110xx1), (where xx denotes the two most significant bits of the + address). + The TRA bit indicates whether the master is in Receiver or Transmitter mode.*/ + + if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent + i2cp->id_state = I2C_MACTIVE; + + if(!(i2cp->id_slave_config->address & 0x8000)){ // slave address is 7-bit + i2cp->id_i2c->DR = ((i2cp->id_slave_config->address & 0x7F) << 1) | + i2cp->rw_bit; + i2cp->id_state = I2C_MWAIT_ADDR_ACK; + return; + } + else{ // slave address is 10-bit + i2cp->id_state = I2C_10BIT_HANDSHAKE; + // send MSB with header. LSB = 0. + i2cp->id_i2c->DR = ((i2cp->id_slave_config->address >> 7) & 0x6) | 0xF0; + return; + } + } + + // "wait" interrupt with ADD10 flag + if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADD10)){ + i2cp->id_i2c->DR = i2cp->id_slave_config->address & 0x00FF; // send remaining bits of address + if (!(i2cp->rw_bit)) + // in transmit mode there is nothing to do with 10-bit handshaking + i2cp->id_state = I2C_MWAIT_ADDR_ACK; + return; + } + + // "wait" interrupt with ADDR flag + if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address ACKed + i2cp->id_i2c->CR1 |= I2C_CR1_START; + return; + } + + if ((i2cp->id_state == I2C_10BIT_HANDSHAKE) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// restart generated + // send MSB with header. LSB = 1 + i2cp->id_i2c->DR = ((i2cp->id_slave_config->address >> 7) & 0x6) | 0xF1; + i2cp->id_state = I2C_MWAIT_ADDR_ACK; + return; + } + + // "wait" interrupt with ADDR (ADD10 in 10-bit receiver mode) flag + if ((i2cp->id_state == I2C_MWAIT_ADDR_ACK) && (i2cp->id_i2c->SR1 & (I2C_SR1_ADDR | I2C_SR1_ADD10))){// address ACKed + if(i2cp->id_i2c->SR2 & I2C_SR2_TRA){// I2C is transmitting data + i2cp->id_state = I2C_MTRANSMIT; // change state + i2c_lld_txbyte(i2cp); // send first byte + return; + } + else {// I2C is receiving data + /* In order to generate the non-acknowledge pulse after the last received + * data byte, the ACK bit must be cleared just after reading the second + * last data byte (after second last RxNE event). + */ + if (i2cp->id_slave_config->rxbytes > 1) + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // set ACK bit + i2cp->id_state = I2C_MRECEIVE; // change state + return; + } + } + + // transmitting bytes one by one + if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){ + if (i2c_lld_txbyte(i2cp)) + i2cp->id_state = I2C_MWAIT_TF; // last byte written + return; + } + + //receiving bytes one by one + if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){ + if (i2c_lld_rxbyte(i2cp)) + i2cp->id_state = I2C_MWAIT_TF; // last byte read + return; + } + + // "wait" BTF bit in status register + if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){ + chSysLockFromIsr(); + i2cp->id_i2c->CR2 &= (~I2C_CR2_ITEVTEN); // disable BTF interrupt + chSysUnlockFromIsr(); + /* now driver is ready to generate (re)start/stop condition. + * Callback function is good place to do that. If not callback was + * set - driver only generate stop condition. */ + i2cp->id_state = I2C_READY; + + if (i2cp->id_slave_config->id_callback != NULL) + i2cp->id_slave_config->id_callback(i2cp, i2cp->id_slave_config); + else /* No callback function set. Generate stop */ + i2c_lld_master_stop(i2cp); + + return; + } +#if CH_DBG_ENABLE_CHECKS + else{ // debugging trap + i = i2cp->id_i2c->SR1; + n = i2cp->id_i2c->SR2; + m = i2cp->id_i2c->CR1; + while(TRUE); + } +#endif /* CH_DBG_ENABLE_CHECKS */ +} + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + */ +CH_IRQ_HANDLER(VectorBC) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC0) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} +#endif + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + */ +CH_IRQ_HANDLER(VectorC4) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC8) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief Low level I2C driver initialization. + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1 + RCC->APB1RSTR = 0; + i2cObjectInit(&I2CD1); + I2CD1.id_i2c = I2C1; +#endif + +#if STM32_I2C_USE_I2C2 + RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2 + RCC->APB1RSTR = 0; + i2cObjectInit(&I2CD2); + I2CD2.id_i2c = I2C2; +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_start(I2CDriver *i2cp) { + + /* If in stopped state then enables the I2C clock.*/ + if (i2cp->id_state == I2C_STOP) { +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); + NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); + RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + NVICEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); + NVICEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable + } +#endif + } + + /* I2C setup.*/ + i2cp->id_i2c->CR1 = I2C_CR1_SWRST; // reset i2c peripherial + i2cp->id_i2c->CR1 = 0; + + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN;// enable interrupts + i2cp->id_i2c->CR1 |= 1; // enable interface +} + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_clock(I2CDriver *i2cp) { + volatile uint16_t regCCR, regCR2, freq, clock_div; + volatile uint16_t pe_bit_saved; + int32_t clock_speed = i2cp->id_config->ClockSpeed; + I2C_DutyCycle_t duty = i2cp->id_config->FastModeDutyCycle; + + chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), + "i2c_lld_set_clock"); + + /*---------------------------- CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + regCR2 = i2cp->id_i2c->CR2; + + /* Clear frequency FREQ[5:0] bits */ + regCR2 &= (uint16_t)~I2C_CR2_FREQ; + /* Set frequency bits depending on pclk1 value */ + freq = (uint16_t)(STM32_PCLK1 / 1000000); + chDbgCheck((freq >= 2) && (freq <= 36), + "i2c_lld_set_clock() : Peripheral clock freq. out of range"); + regCR2 |= freq; + i2cp->id_i2c->CR2 = regCR2; + + /*---------------------------- CCR Configuration ------------------------*/ + pe_bit_saved = (i2cp->id_i2c->CR1 & I2C_CR1_PE); + /* Disable the selected I2C peripheral to configure TRISE */ + i2cp->id_i2c->CR1 &= (uint16_t)~I2C_CR1_PE; + + /* Clear F/S, DUTY and CCR[11:0] bits */ + regCCR = 0; + clock_div = I2C_CCR_CCR; + /* Configure clock_div in standard mode */ + if (clock_speed <= 100000) { + chDbgAssert(duty == stdDutyCycle, + "i2c_lld_set_clock(), #1", "Invalid standard mode duty cycle"); + /* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); + /* Test if CCR value is under 0x4, and set the minimum allowed value */ + if (clock_div < 0x04) clock_div = 0x04; + /* Set clock_div value for standard mode */ + regCCR |= (clock_div & I2C_CCR_CCR); + /* Set Maximum Rise Time for standard mode */ + i2cp->id_i2c->TRISE = freq + 1; + } + /* Configure clock_div in fast mode */ + else if(clock_speed <= 400000) { + chDbgAssert((duty == fastDutyCycle_2) || (duty == fastDutyCycle_16_9), + "i2c_lld_set_clock(), #2", "Invalid fast mode duty cycle"); + if(duty == fastDutyCycle_2) { + /* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); + } + else if(duty == fastDutyCycle_16_9) { + /* Fast mode clock_div calculate: Tlow/Thigh = 16/9 */ + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); + /* Set DUTY bit */ + regCCR |= I2C_CCR_DUTY; + } + /* Test if CCR value is under 0x1, and set the minimum allowed value */ + if(clock_div < 0x01) clock_div = 0x01; + /* Set clock_div value and F/S bit for fast mode*/ + regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); + /* Set Maximum Rise Time for fast mode */ + i2cp->id_i2c->TRISE = (freq * 300 / 1000) + 1; + } + chDbgAssert((clock_div <= I2C_CCR_CCR), + "i2c_lld_set_clock(), #3", "Too low clock clock speed selected"); + + /* Write to I2Cx CCR */ + i2cp->id_i2c->CCR = regCCR; + + /* restore the I2C peripheral enabled state */ + i2cp->id_i2c->CR1 |= pe_bit_saved; +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_opmode(I2CDriver *i2cp) { + I2C_opMode_t opmode = i2cp->id_config->opMode; + uint16_t regCR1; + + /*---------------------------- CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + regCR1 = i2cp->id_i2c->CR1; + switch(opmode){ + case opmodeI2C: + regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + case opmodeSMBusDevice: + regCR1 |= I2C_CR1_SMBUS; + regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); + break; + case opmodeSMBusHost: + regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + } + /* Write to I2Cx CR1 */ + i2cp->id_i2c->CR1 = regCR1; +} + +/** + * @brief Set own address. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_own_address(I2CDriver *i2cp) { + //TODO: dual address mode + + /*---------------------------- OAR1 Configuration -----------------------*/ + i2cp->id_i2c->OAR1 |= 1 << 14; + + if (&(i2cp->id_config->OwnAddress10) == NULL){// only 7-bit address + i2cp->id_i2c->OAR1 &= (~I2C_OAR1_ADDMODE); + i2cp->id_i2c->OAR1 |= i2cp->id_config->OwnAddress7 << 1; + } + else { + chDbgAssert((i2cp->id_config->OwnAddress10 < 1024), + "i2c_lld_set_own_address(), #1", "10-bit address longer then 10 bit") + i2cp->id_i2c->OAR1 |= I2C_OAR1_ADDMODE; + i2cp->id_i2c->OAR1 |= i2cp->id_config->OwnAddress10; + } +} + + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If in ready state then disables the I2C clock.*/ + if (i2cp->id_state == I2C_READY) { +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + NVICDisableVector(I2C1_EV_IRQn); + NVICDisableVector(I2C1_ER_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + NVICDisableVector(I2C2_EV_IRQn); + NVICDisableVector(I2C2_ER_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN; + } +#endif + } + i2cp->id_state = I2C_STOP; +} + +/** + * @brief Generate start condition. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_master_start(I2CDriver *i2cp){ + i2cp->id_i2c->CR1 |= I2C_CR1_START; + while (i2cp->id_i2c->CR1 & I2C_CR1_START); + + /* enable interrupts from I2C hardware. They will disable in driver state + machine after the transfer finish.*/ + i2cp->id_i2c->CR2 |= I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN; +} + +/** + * @brief Generate stop condition. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_master_stop(I2CDriver *i2cp){ + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP); +} + +/** + * @brief Begin data transmitting. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + + i2cp->id_slave_config = i2cscfg; + i2cp->rw_bit = I2C_WRITE; + + // generate start condition. Later transmission goes in background + i2c_lld_master_start(i2cp); +} + +/** + * @brief Begin data receiving. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object + */ +void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + + i2cp->id_slave_config = i2cscfg; + i2cp->rw_bit = I2C_READ; + + // generate (re)start condition. Later connection goes asynchronously + i2c_lld_master_start(i2cp); +} + + + +/** + * @brief Transmits data via I2C bus. + * + * @note This function does not use interrupts + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object + * @param[in] restart bool. If TRUE then generate restart condition instead of stop + */ +void i2c_lld_master_transmit_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart) { + + int i = 0; + + i2cp->id_slave_config = i2cscfg; + i2cp->rw_bit = I2C_WRITE; + + + i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)); // wait Address sent + + i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_WRITE; // write slave addres in DR + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent + i = i2cp->id_i2c->SR2; + i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit + + // now write data byte by byte in DR register + uint32_t n = 0; + for (n = 0; n < i2cp->id_slave_config->txbytes; n++){ + i2cp->id_i2c->DR = i2cscfg->txbuf[n]; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE)); + } + + while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)); + + if (restart){ + i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)); // wait start bit + } + else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // generate stop condition +} + + +/** + * @brief Receives data from the I2C bus. + * @note This function does not use interrupts + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object + */ +void i2c_lld_master_receive_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) { + + i2cp->id_slave_config = i2cscfg; + + uint16_t i = 0; + + // send slave addres with read-bit + i2cp->id_i2c->DR = (i2cp->id_slave_config->address << 1) | I2C_READ; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)); // wait Address sent + + i = i2cp->id_i2c->SR2; + i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit + + // set ACK bit + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + + // collect data from slave + for (i = 0; i < i2cp->id_slave_config->rxbytes; i++){ + if ((i2cp->id_slave_config->rxbytes - i) == 1){ + // clear ACK bit for automatically send NACK + i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);} + while (!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)); + + i2cp->id_slave_config->rxbuf[i] = i2cp->id_i2c->DR; + } + // generate STOP + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; +} + + + +#endif // HAL_USE_I2C diff --git a/os/hal/platforms/STM32/i2c_lld_btrts.h b/os/hal/platforms/STM32/i2c_lld_btrts.h new file mode 100644 index 000000000..76f7068e2 --- /dev/null +++ b/os/hal/platforms/STM32/i2c_lld_btrts.h @@ -0,0 +1,201 @@ +/** + * @file STM32/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * @addtogroup STM32_I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 TRUE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 TRUE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 0xA0 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#define I2CD_NO_ERROR 0 +/** @brief Bus Error.*/ +#define I2CD_BUS_ERROR 0x01 +/** @brief Arbitration Lost (master mode).*/ +#define I2CD_ARBITRATION_LOST 0x02 +/** @brief Acknowledge Failure.*/ +#define I2CD_ACK_FAILURE 0x04 +/** @brief Overrun/Underrun.*/ +#define I2CD_OVERRUN 0x08 +/** @brief PEC Error in reception.*/ +#define I2CD_PEC_ERROR 0x10 +/** @brief Timeout or Tlow Error.*/ +#define I2CD_TIMEOUT 0x20 +/** @brief SMBus Alert.*/ +#define I2CD_SMB_ALERT 0x40 +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef enum { + opmodeI2C, + opmodeSMBusDevice, + opmodeSMBusHost, +} I2C_opMode_t; + +typedef enum { + stdDutyCycle, + fastDutyCycle_2, + fastDutyCycle_16_9, +} I2C_DutyCycle_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + I2C_opMode_t opMode; /*!< Specifies the I2C mode.*/ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. Must be set to a value lower than 400kHz */ + I2C_DutyCycle_t FastModeDutyCycle;/*!< Specifies the I2C fast mode duty cycle */ + uint8_t OwnAddress7; /*!< Specifies the first device 7-bit own address. */ + uint16_t OwnAddress10; /*!< Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */ +} I2CConfig; + + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Type of a structure representing an I2C slave config. + */ +typedef struct I2CSlaveConfig I2CSlaveConfig; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t id_state; +#if I2C_USE_WAIT + /** + * @brief Thread waiting for I/O completion. + */ + Thread *thread; +#endif /* I2C_USE_WAIT */ +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex id_mutex; +#elif CH_USE_SEMAPHORES + Semaphore id_semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + /** + * @brief Current configuration data. + */ + I2CConfig *id_config; + /** + * @brief Current slave configuration data. + */ + I2CSlaveConfig *id_slave_config; + /** + * @brief RW-bit sent to slave. + */ + uint8_t rw_bit; + + /*********** End of the mandatory fields. **********************************/ + + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *id_i2c; +} ; + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** @cond never*/ +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void i2c_lld_init(void); +void i2c_lld_start(I2CDriver *i2cp); +void i2c_lld_stop(I2CDriver *i2cp); +void i2c_lld_set_clock(I2CDriver *i2cp); +void i2c_lld_set_opmode(I2CDriver *i2cp); +void i2c_lld_set_own_address(I2CDriver *i2cp); + +void i2c_lld_master_start(I2CDriver *i2cp); +void i2c_lld_master_stop(I2CDriver *i2cp); + +void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); +void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); + +void i2c_lld_master_transmit_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart); +void i2c_lld_master_receive_NI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); + +#ifdef __cplusplus +} +#endif +/** @endcond*/ + +#endif // CH_HAL_USE_I2C + +#endif // _I2C_LLD_H_ diff --git a/os/hal/platforms/STM32/platform.mk b/os/hal/platforms/STM32/platform.mk index f0aec9de6..02f090e5e 100644 --- a/os/hal/platforms/STM32/platform.mk +++ b/os/hal/platforms/STM32/platform.mk @@ -10,8 +10,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/usb_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/stm32_dma.c
+ ${CHIBIOS}/os/hal/platforms/STM32/stm32_dma.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32
diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 86bfc16f6..6f99a1afb 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -55,7 +55,6 @@ * @init
*/
void i2cInit(void) {
-
i2c_lld_init();
}
@@ -68,8 +67,22 @@ void i2cInit(void) { */
void i2cObjectInit(I2CDriver *i2cp) {
- i2cp->i2c_state = I2C_STOP;
- i2cp->i2c_config = NULL;
+ i2cp->id_state = I2C_STOP;
+ i2cp->id_config = NULL;
+ i2cp->id_slave_config = NULL;
+
+#if I2C_USE_WAIT
+ i2cp->id_thread = NULL;
+#endif /* I2C_USE_WAIT */
+
+#if I2C_USE_MUTUAL_EXCLUSION
+#if CH_USE_MUTEXES
+ chMtxInit(&i2cp->id_mutex);
+#else
+ chSemInit(&i2cp->id_semaphore, 1);
+#endif /* CH_USE_MUTEXES */
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+
#if defined(I2C_DRIVER_EXT_INIT_HOOK)
I2C_DRIVER_EXT_INIT_HOOK(i2cp);
#endif
@@ -83,17 +96,17 @@ void i2cObjectInit(I2CDriver *i2cp) { *
* @api
*/
-void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
+void i2cStart(I2CDriver *i2cp, I2CConfig *config) {
chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
chSysLock();
- chDbgAssert((i2cp->i2c_state == I2C_STOP) || (i2cp->i2c_state == I2C_READY),
+ chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStart(), #1",
"invalid state");
- i2cp->i2c_config = config;
+ i2cp->id_config = config;
i2c_lld_start(i2cp);
- i2cp->i2c_state = I2C_READY;
+ i2cp->id_state = I2C_READY;
chSysUnlock();
}
@@ -109,151 +122,190 @@ void i2cStop(I2CDriver *i2cp) { chDbgCheck(i2cp != NULL, "i2cStop");
chSysLock();
- chDbgAssert((i2cp->i2c_state == I2C_STOP) || (i2cp->i2c_state == I2C_READY),
+ chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStop(), #1",
"invalid state");
i2c_lld_stop(i2cp);
- i2cp->i2c_state = I2C_STOP;
+ i2cp->id_state = I2C_STOP;
chSysUnlock();
}
/**
- * @brief Initiates a master bus transaction.
- * @details This function sends a start bit followed by an one or two bytes
- * header.
+ * @brief Sends data ever the I2C bus.
*
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] header transaction header
- * @param[in] callback operation complete callback
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] i2cscfg pointer to the @p I2C slave config
*
- * @iclass
*/
-void i2cMasterStartI(I2CDriver *i2cp,
- uint16_t header,
- i2ccallback_t callback) {
+void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
+
+ size_t n;
+ i2cblock_t *txbuf;
+ uint8_t nbit_addr;
+
+ txbuf = i2cscfg->txbuf;
+ nbit_addr = i2cscfg->nbit_address;
+ n = i2cscfg->txbytes;
+
+ chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) && \
+ ((nbit_addr == 7) || (nbit_addr == 10)) && (n > 0) && (txbuf != NULL),
+ "i2cMasterTransmit");
+
+ // init slave config field in driver
+ i2cp->id_slave_config = i2cscfg;
- chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStartI");
- chDbgAssert(i2cp->i2c_state == I2C_READY,
- "i2cMasterStartI(), #1", "invalid state");
+#if I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+ if(i2c_lld_bus_is_busy(i2cp)) {
+#ifdef PRINTTRACE
+ print("I2C Bus busy!\n");
+#endif
+ return;
+ };
+#endif
- i2cp->id_callback = callback;
- i2c_lld_master_start(i2cp, header);
+ chSysLock();
+ chDbgAssert(i2cp->id_state == I2C_READY,
+ "i2cMasterTransmit(), #1", "not ready");
+
+ i2cp->id_state = I2C_ACTIVE;
+ i2c_lld_master_transmit(i2cp);
+ _i2c_wait_s(i2cp);
+#if !I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+#endif
+ if (i2cp->id_state == I2C_COMPLETE)
+ i2cp->id_state = I2C_READY;
+ chSysUnlock();
}
/**
- * @brief Terminates a master bus transaction.
+ * @brief Receives data from the I2C bus.
*
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] callback operation complete callback
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] i2cscfg pointer to the @p I2C slave config
*
- * @iclass
*/
-void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback) {
+void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
- chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStopI");
- chDbgAssert(i2cp->i2c_state == I2C_MREADY,
- "i2cMasterStopI(), #1", "invalid state");
+ size_t n;
+ i2cblock_t *rxbuf;
+ uint8_t nbit_addr;
- i2cp->id_callback = callback;
- i2c_lld_master_stop(i2cp);
-}
+ rxbuf = i2cscfg->rxbuf;
+ n = i2cscfg->rxbytes;
+ nbit_addr = i2cscfg->nbit_address;
+ chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) && (n > 0) && \
+ ((nbit_addr == 7) || (nbit_addr == 10)) && (rxbuf != NULL),
+ "i2cMasterReceive");
+
+ // init slave config field in driver
+ i2cp->id_slave_config = i2cscfg;
+
+#if I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+ if(i2c_lld_bus_is_busy(i2cp)) {
+#ifdef PRINTTRACE
+ print("I2C Bus busy!\n");
+#endif
+ return;
+ };
+#endif
+
+ chSysLock();
+ chDbgAssert(i2cp->id_state == I2C_READY,
+ "i2cMasterReceive(), #1", "not ready");
+
+ i2cp->id_state = I2C_ACTIVE;
+ i2c_lld_master_receive(i2cp);
+ _i2c_wait_s(i2cp);
+#if !I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+#endif
+ if (i2cp->id_state == I2C_COMPLETE)
+ i2cp->id_state = I2C_READY;
+ chSysUnlock();
+}
-/**
- * @brief Sends a restart bit.
- * @details Restart bits are required by some types of I2C transactions.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] callback operation complete callback
- *
- * @iclass
- */
-void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback) {
- chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterRestartI");
- chDbgAssert(i2cp->i2c_state == I2C_MREADY,
- "i2cMasterRestartI(), #1", "invalid state");
+uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
- i2cp->id_callback = callback;
- i2c_lld_master_restart(i2cp);
+ i2cMasterReceive(i2cp, i2cscfg);
+ return i2cp->id_slave_config->slave_addr;
}
+
/**
- * @brief Master transmission.
+ * @brief Handles communication events/errors.
+ * @details Must be called from the I/O interrupt service routine in order to
+ * notify I/O conditions as errors, signals change etc.
*
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] n number of bytes to be transmitted
- * @param[in] txbuf transmit data buffer pointer
- * @param[in] callback operation complete callback
+ * @param[in] i2cp pointer to a @p I2CDriver structure
+ * @param[in] mask condition flags to be added to the mask
*
* @iclass
*/
-void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
- i2ccallback_t callback) {
+void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask) {
- chDbgCheck((i2cp != NULL) && (n > 0) &&
- (txbuf != NULL) && (callback != NULL), "i2cMasterTransmitI");
- chDbgAssert(i2cp->i2c_state == I2C_MREADY,
- "i2cMasterTransmitI(), #1", "invalid state");
+ chDbgCheck(i2cp != NULL, "i2cAddFlagsI");
- i2cp->id_callback = callback;
- i2c_lld_master_transmit(i2cp, n, txbuf);
+ i2cp->id_slave_config->errors |= mask;
+ chEvtBroadcastI(&i2cp->id_slave_config->sevent);
}
/**
- * @brief Master receive.
+ * @brief Returns and clears the errors mask associated to the driver.
*
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] n number of bytes to be transmitted
- * @param[in] rxbuf receive data buffer pointer
- * @param[in] callback operation complete callback
+ * @param[in] i2cp pointer to a @p I2CDriver structure
+ * @return The condition flags modified since last time this
+ * function was invoked.
*
- * @iclass
+ * @api
*/
-void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf,
- i2ccallback_t callback) {
+i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp) {
+ i2cflags_t mask;
- chDbgCheck((i2cp != NULL) && (n > 0) &&
- (rxbuf != NULL) && (callback != NULL), "i2cMasterReceiveI");
- chDbgAssert(i2cp->i2c_state == I2C_MREADY,
- "i2cMasterReceiveI(), #1", "invalid state");
+ chDbgCheck(i2cp != NULL, "i2cGetAndClearFlags");
- i2cp->id_callback = callback;
- i2c_lld_master_receive(i2cp, n, rxbuf);
+ chSysLock();
+ mask = i2cp->id_slave_config->errors;
+ i2cp->id_slave_config->errors = I2CD_NO_ERROR;
+ chSysUnlock();
+ return mask;
}
+
+
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
- * @brief Gains exclusive access to the I2C bus.
+ * @brief Gains exclusive access to the I2C bus.
* @details This function tries to gain ownership to the I2C bus, if the bus
* is already being used then the invoking thread is queued.
- * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION
- * must be enabled.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*
- * @api
- *
+ * @note This function is only available when the @p I2C_USE_MUTUAL_EXCLUSION
+ * option is set to @p TRUE.
*/
void i2cAcquireBus(I2CDriver *i2cp) {
chDbgCheck(i2cp != NULL, "i2cAcquireBus");
#if CH_USE_MUTEXES
- chMtxLock(&i2cp->id_mutex);
+ chMtxLock(&i2cp->mutex);
#elif CH_USE_SEMAPHORES
chSemWait(&i2cp->id_semaphore);
#endif
}
/**
- * @brief Releases exclusive access to the I2C bus.
- * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION
- * must be enabled.
+ * @brief Releases exclusive access to the I2C bus.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*
- * @api
+ * @note This function is only available when the @p I2C_USE_MUTUAL_EXCLUSION
+ * option is set to @p TRUE.
*/
void i2cReleaseBus(I2CDriver *i2cp) {
diff --git a/os/hal/src/i2c_albi.c b/os/hal/src/i2c_albi.c new file mode 100644 index 000000000..64bed78eb --- /dev/null +++ b/os/hal/src/i2c_albi.c @@ -0,0 +1,268 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/**
+ * @brief I2C Driver initialization.
+ */
+void i2cInit(void) {
+
+ i2c_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p I2CDriver structure.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2cObjectInit(I2CDriver *i2cp) {
+ chEvtInit(&i2cp->sevent);
+ i2cp->errors = I2CD_NO_ERROR;
+ i2cp->state = I2C_STOP;
+// i2cp->i2cd_config = NULL;
+#if I2C_USE_WAIT
+ i2cp->thread = NULL;
+#endif /* I2C_USE_WAIT */
+#if I2C_USE_MUTUAL_EXCLUSION
+#if CH_USE_MUTEXES
+ chMtxInit(&i2cp->mutex);
+#elif CH_USE_SEMAPHORES
+ chSemInit(&i2cp->semaphore, 1);
+#endif
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_INIT_HOOK)
+ I2C_DRIVER_EXT_INIT_HOOK(i2cp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] config pointer to the @p I2CConfig object
+ */
+void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
+
+ chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
+
+ chSysLock();
+ chDbgAssert((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
+ "i2cStart(), #1", "invalid state");
+
+ i2cp->nbit_address = config->nBitAddress;
+ i2c_lld_start(i2cp);
+ i2c_lld_set_clock(i2cp, config->ClockSpeed, config->FastModeDutyCycle);
+ i2c_lld_set_opmode(i2cp, config->opMode);
+ i2c_lld_set_own_address(i2cp, config->OwnAddress1, config->nBitAddress);
+ i2cp->state = I2C_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2cStop(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cStop");
+
+ chSysLock();
+ chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY),
+ "i2cStop(), #1", "invalid state");
+ i2c_lld_stop(i2cp);
+ i2cp->state = I2C_STOP;
+ chSysUnlock();
+}
+
+/**
+ * @brief Sends data ever the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] slave_addr 7-bit or 10-bit address of the slave
+ * @param[in] n number of words to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ */
+void i2cMasterTransmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf) {
+
+ chDbgCheck((i2cp != NULL) && (n > 0) && (txbuf != NULL),
+ "i2cMasterTransmit");
+
+#if I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+ if(i2c_lld_bus_is_busy(i2cp)) {
+#ifdef PRINTTRACE
+ print("I2C Bus busy!\n");
+#endif
+ return;
+ };
+#endif
+
+ chSysLock();
+ chDbgAssert(i2cp->state == I2C_READY,
+ "i2cMasterTransmit(), #1", "not ready");
+
+ i2cp->state = I2C_ACTIVE;
+ i2c_lld_master_transmit(i2cp, slave_addr, n, txbuf);
+ _i2c_wait_s(i2cp);
+#if !I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+#endif
+ if (i2cp->state == I2C_COMPLETE)
+ i2cp->state = I2C_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Receives data from the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] slave_addr 7-bit or 10-bit address of the slave
+ * @param[in] n number of bytes to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ */
+void i2cMasterReceive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf) {
+
+ chDbgCheck((i2cp != NULL) && (n > 0) && (rxbuf != NULL),
+ "i2cMasterReceive");
+
+#if I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+ if(i2c_lld_bus_is_busy(i2cp)) {
+#ifdef PRINTTRACE
+ print("I2C Bus busy!\n");
+#endif
+ return;
+ };
+#endif
+
+ chSysLock();
+ chDbgAssert(i2cp->state == I2C_READY,
+ "i2cMasterReceive(), #1", "not ready");
+
+ i2cp->state = I2C_ACTIVE;
+ i2c_lld_master_receive(i2cp, slave_addr, n, rxbuf);
+ _i2c_wait_s(i2cp);
+#if !I2C_USE_WAIT
+ i2c_lld_wait_bus_free(i2cp);
+#endif
+ if (i2cp->state == I2C_COMPLETE)
+ i2cp->state = I2C_READY;
+ chSysUnlock();
+}
+
+uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp) {
+ uint16_t slv_addr;
+
+ i2cMasterReceive(i2cp, 0x0C, 2, &slv_addr);
+ return slv_addr;
+}
+
+
+/**
+ * @brief Handles communication events/errors.
+ * @details Must be called from the I/O interrupt service routine in order to
+ * notify I/O conditions as errors, signals change etc.
+ *
+ * @param[in] i2cp pointer to a @p I2CDriver structure
+ * @param[in] mask condition flags to be added to the mask
+ *
+ * @iclass
+ */
+void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask) {
+
+ chDbgCheck(i2cp != NULL, "i2cAddFlagsI");
+
+ i2cp->errors |= mask;
+ chEvtBroadcastI(&i2cp->sevent);
+}
+
+/**
+ * @brief Returns and clears the errors mask associated to the driver.
+ *
+ * @param[in] i2cp pointer to a @p I2CDriver structure
+ * @return The condition flags modified since last time this
+ * function was invoked.
+ *
+ * @api
+ */
+i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp) {
+ i2cflags_t mask;
+
+ chDbgCheck(i2cp != NULL, "i2cGetAndClearFlags");
+
+ chSysLock();
+ mask = i2cp->errors;
+ i2cp->errors = I2CD_NO_ERROR;
+ chSysUnlock();
+ return mask;
+}
+
+
+
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the I2C bus.
+ * @details This function tries to gain ownership to the I2C bus, if the bus
+ * is already being used then the invoking thread is queued.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @note This function is only available when the @p I2C_USE_MUTUAL_EXCLUSION
+ * option is set to @p TRUE.
+ */
+void i2cAcquireBus(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cAcquireBus");
+
+#if CH_USE_MUTEXES
+ chMtxLock(&i2cp->mutex);
+#elif CH_USE_SEMAPHORES
+ chSemWait(&i2cp->semaphore);
+#endif
+}
+
+/**
+ * @brief Releases exclusive access to the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @note This function is only available when the @p I2C_USE_MUTUAL_EXCLUSION
+ * option is set to @p TRUE.
+ */
+void i2cReleaseBus(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cReleaseBus");
+
+#if CH_USE_MUTEXES
+ (void)i2cp;
+ chMtxUnlock();
+#elif CH_USE_SEMAPHORES
+ chSemSignal(&i2cp->semaphore);
+#endif
+}
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+
+#endif /* CH_HAL_USE_I2C */
diff --git a/os/hal/src/i2c_brts.c b/os/hal/src/i2c_brts.c new file mode 100644 index 000000000..ad9a5d0ac --- /dev/null +++ b/os/hal/src/i2c_brts.c @@ -0,0 +1,249 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file i2c.c
+ * @brief I2C Driver code.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief I2C Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void i2cInit(void) {
+ i2c_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p I2CDriver structure.
+ *
+ * @param[out] i2cp pointer to the @p I2CDriver object
+ *
+ * @init
+ */
+void i2cObjectInit(I2CDriver *i2cp) {
+
+ i2cp->id_state = I2C_STOP;
+ i2cp->id_config = NULL;
+ i2cp->id_slave_config = NULL;
+
+#if I2C_USE_WAIT
+ i2cp->id_thread = NULL;
+#endif /* I2C_USE_WAIT */
+
+#if I2C_USE_MUTUAL_EXCLUSION
+#if CH_USE_MUTEXES
+ chMtxInit(&i2cp->id_mutex);
+#else
+ chSemInit(&i2cp->id_semaphore, 1);
+#endif /* CH_USE_MUTEXES */
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+
+#if defined(I2C_DRIVER_EXT_INIT_HOOK)
+ I2C_DRIVER_EXT_INIT_HOOK(i2cp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] config pointer to the @p I2CConfig object
+ *
+ * @api
+ */
+void i2cStart(I2CDriver *i2cp, I2CConfig *config) {
+
+ chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
+
+ chSysLock();
+ chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
+ "i2cStart(), #1",
+ "invalid state");
+ i2cp->id_config = config;
+ i2c_lld_start(i2cp);
+ i2cp->id_state = I2C_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @api
+ */
+void i2cStop(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cStop");
+
+ chSysLock();
+ chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
+ "i2cStop(), #1",
+ "invalid state");
+ i2c_lld_stop(i2cp);
+ i2cp->id_state = I2C_STOP;
+ chSysUnlock();
+}
+
+/**
+ * @brief Generate (re)start on the bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2cMasterStart(I2CDriver *i2cp){
+
+ chDbgCheck((i2cp != NULL), "i2cMasterTransmit");
+
+ chSysLock();
+ i2c_lld_master_start(i2cp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Generate stop on the bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ */
+void i2cMasterStop(I2CDriver *i2cp){
+
+ chDbgCheck((i2cp != NULL), "i2cMasterTransmit");
+ chSysLock();
+ i2c_lld_master_stop(i2cp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Sends data ever the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
+ *
+ */
+void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
+
+ chDbgCheck((i2cp != NULL) && (i2cscfg != NULL),
+ "i2cMasterTransmit");
+ chDbgAssert(i2cp->id_state == I2C_READY,
+ "i2cMasterTransmit(), #1",
+ "not active");
+
+ chSysLock();
+ i2c_lld_master_transmit(i2cp, i2cscfg);
+ chSysUnlock();
+}
+
+
+/**
+ * @brief Receives data from the I2C bus.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
+ */
+void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
+
+ chDbgCheck((i2cp != NULL) && (i2cscfg != NULL),
+ "i2cMasterReceive");
+ chDbgAssert(i2cp->id_state == I2C_READY,
+ "i2cMasterReceive(), #1",
+ "not active");
+
+ chSysLock();
+ i2c_lld_master_receive(i2cp, i2cscfg);
+ chSysUnlock();
+}
+
+
+
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the I2C bus.
+ * @details This function tries to gain ownership to the I2C bus, if the bus
+ * is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @api
+ *
+ */
+void i2cAcquireBus(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cAcquireBus");
+
+#if CH_USE_MUTEXES
+ chMtxLock(&i2cp->id_mutex);
+#elif CH_USE_SEMAPHORES
+ chSemWait(&i2cp->id_semaphore);
+#endif
+}
+
+/**
+ * @brief Releases exclusive access to the I2C bus.
+ * @pre In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @api
+ */
+void i2cReleaseBus(I2CDriver *i2cp) {
+
+ chDbgCheck(i2cp != NULL, "i2cReleaseBus");
+
+#if CH_USE_MUTEXES
+ (void)i2cp;
+ chMtxUnlock();
+#elif CH_USE_SEMAPHORES
+ chSemSignal(&i2cp->id_semaphore);
+#endif
+}
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/testhal/STM32/I2C/Makefile b/testhal/STM32/I2C/Makefile new file mode 100644 index 000000000..888e33eb2 --- /dev/null +++ b/testhal/STM32/I2C/Makefile @@ -0,0 +1,213 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra
+ #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable register caching optimization (read documentation).
+ifeq ($(USE_CURRP_CACHING),)
+ USE_CURRP_CACHING = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+ USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Define linker script file here
+LDSCRIPT= ch.ld
+
+# Imported source files
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
+include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/evtimer.c \
+ $(CHIBIOS)/os/various/syscalls.c \
+ main.c \
+ i2c_pns.c \
+ lis3.c\
+ tmp75.c\
+ max1236.c\
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+# -lm добавлен именно здесь, потому что больше некуда
+MCU = cortex-m3
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FWLIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ CSRC += $(STM32SRC)
+ INCDIR += $(STM32INC)
+ USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
+
+
diff --git a/testhal/STM32/I2C/ch.ld b/testhal/STM32/I2C/ch.ld new file mode 100644 index 000000000..44f494121 --- /dev/null +++ b/testhal/STM32/I2C/ch.ld @@ -0,0 +1,113 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * ST32F103 memory setup.
+ */
+__main_stack_size__ = 0x0400;
+__process_stack_size__ = 0x0400;
+__stacks_total_size__ = __main_stack_size__ + __process_stack_size__;
+
+MEMORY
+{
+ flash : org = 0x08000000, len = 128k
+ ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__ = ORIGIN(ram);
+__ram_size__ = LENGTH(ram);
+__ram_end__ = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+ . = 0;
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ _text = .;
+ KEEP(*(vectors))
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > flash
+
+ .ctors :
+ {
+ PROVIDE(_ctors_start_ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(_ctors_end_ = .);
+ } > flash
+
+ .dtors :
+ {
+ PROVIDE(_dtors_start_ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(_dtors_end_ = .);
+ } > flash
+
+ .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
+
+ __exidx_start = .;
+ .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
+ __exidx_end = .;
+
+ .eh_frame_hdr : {*(.eh_frame_hdr)}
+
+ .eh_frame : ONLY_IF_RO {*(.eh_frame)}
+
+ . = ALIGN(4);
+ _etext = .;
+ _textdata = _etext;
+
+ .data :
+ {
+ _data = .;
+ *(.data)
+ . = ALIGN(4);
+ *(.data.*)
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ _edata = .;
+ } > ram AT > flash
+
+ .bss :
+ {
+ _bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ *(.bss.*)
+ . = ALIGN(4);
+ *(COMMON)
+ . = ALIGN(4);
+ _bss_end = .;
+ } > ram
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__ = _end;
+__heap_end__ = __ram_end__ - __stacks_total_size__;
diff --git a/testhal/STM32/I2C/chconf.h b/testhal/STM32/I2C/chconf.h new file mode 100644 index 000000000..657ddf887 --- /dev/null +++ b/testhal/STM32/I2C/chconf.h @@ -0,0 +1,507 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/* Kernel parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Nested locks.
+ * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock()
+ * operations is allowed.<br>
+ * For performance and code size reasons the recommended setting
+ * is to leave this option disabled.<br>
+ * You may use this option if you need to merge ChibiOS/RT with
+ * external libraries that require nested lock/unlock operations.
+ *
+ * @note T he default is @p FALSE.
+ */
+#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__)
+#define CH_USE_NESTED_LOCKS TRUE
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_COREMEM.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/*===========================================================================*/
+/* Performance options. */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED FALSE
+#endif
+
+/**
+ * @brief Exotic optimization.
+ * @details If defined then a CPU register is used as storage for the global
+ * @p currp variable. Caching this variable in a register greatly
+ * improves both space and time OS efficiency. A side effect is that
+ * one less register has to be saved during the context switch
+ * resulting in lower RAM usage and faster context switch.
+ *
+ * @note This option is only usable with the GCC compiler and is only useful
+ * on processors with many registers like ARM cores.
+ * @note If this option is enabled then ALL the libraries linked to the
+ * ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p
+ * -ffixed-@<reg@>.
+ * @note This option must be enabled in the Makefile, it is listed here for
+ * documentation only.
+ */
+#if defined(__DOXYGEN__)
+#define CH_CURRP_REGISTER_CACHE "reg"
+#endif
+
+/*===========================================================================*/
+/* Subsystem options. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES FALSE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS FALSE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP FALSE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS FALSE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC FALSE
+#endif
+
+/*===========================================================================*/
+/* Debug options. */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS TRUE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS TRUE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE TRUE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS TRUE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING FALSE
+#endif
+
+/*===========================================================================*/
+/* Kernel hooks. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitily from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+ /* System tick event code here.*/ \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/I2C/halconf.h b/testhal/STM32/I2C/halconf.h new file mode 100644 index 000000000..9a7979cc9 --- /dev/null +++ b/testhal/STM32/I2C/halconf.h @@ -0,0 +1,259 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C TRUE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE 512
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/**
+ * @brief Number of positive insertion queries before generating the
+ * insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL 10
+#endif
+
+/**
+ * @brief Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY 10
+#endif
+
+/**
+ * @brief Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ * saves two context switches and interrupt servicing. Note
+ * that this option has no effect on large transfers which
+ * are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING TRUE
+#endif
+
+/*===========================================================================*/
+/* PAL driver related settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* PWM driver related settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/I2C/i2c_pns.c b/testhal/STM32/I2C/i2c_pns.c new file mode 100644 index 000000000..11982d0a7 --- /dev/null +++ b/testhal/STM32/I2C/i2c_pns.c @@ -0,0 +1,61 @@ +#include "ch.h"
+#include "hal.h"
+
+#include "i2c_pns.h"
+
+#include "lis3.h"
+#include "tmp75.h"
+#include "max1236.h"
+
+/* I2C1 */
+static I2CConfig i2cfg1 = {
+ opmodeI2C,
+ 100000,
+ stdDutyCycle,
+ 0,
+ 0,
+};
+
+/* I2C2 */
+static I2CConfig i2cfg2 = {
+ opmodeI2C,
+ 100000,
+ stdDutyCycle,
+ 0,
+ 0,
+};
+
+
+
+void I2CInit_pns(void){
+
+ i2cInit();
+
+ i2cStart(&I2CD1, &i2cfg1);
+ while(I2CD1.id_state != I2C_READY){ // wait ready status
+ chThdSleepMilliseconds(1);
+ }
+
+ i2cStart(&I2CD2, &i2cfg2);
+ while(I2CD2.id_state != I2C_READY){ // wait ready status
+ chThdSleepMilliseconds(1);
+ }
+
+ /* tune ports for I2C1*/
+ palSetPadMode(IOPORT2, 6, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+ palSetPadMode(IOPORT2, 7, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+
+ /* tune ports for I2C2*/
+ palSetPadMode(IOPORT2, 10, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+ palSetPadMode(IOPORT2, 11, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+
+
+ /* startups. Pauses added just to be safe */
+ init_max1236();
+ chThdSleepMilliseconds(100);
+
+ init_lis3();
+ chThdSleepMilliseconds(100);
+}
+
+
diff --git a/testhal/STM32/I2C/i2c_pns.h b/testhal/STM32/I2C/i2c_pns.h new file mode 100644 index 000000000..4dfdf320e --- /dev/null +++ b/testhal/STM32/I2C/i2c_pns.h @@ -0,0 +1,8 @@ +#ifndef I2C_PNS_H_
+#define I2C_PNS_H_
+
+
+void I2CInit_pns(void);
+
+
+#endif /* I2C_PNS_H_ */
diff --git a/testhal/STM32/I2C/lis3.c b/testhal/STM32/I2C/lis3.c new file mode 100644 index 000000000..06f6da1d0 --- /dev/null +++ b/testhal/STM32/I2C/lis3.c @@ -0,0 +1,170 @@ +/**
+ * This is most complex and difficult device.
+ * It realize "read through write" paradigm. This is not standard, but
+ * most of I2C devices use this paradigm.
+ * You must write to device reading address, send restart to bus,
+ * and then begin reading process.
+ */
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#include "lis3.h"
+
+
+// buffers
+static i2cblock_t accel_rx_data[ACCEL_RX_DEPTH];
+static i2cblock_t accel_tx_data[ACCEL_TX_DEPTH];
+
+/* Error trap */
+static void i2c_lis3_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+ (void)i2cscfg;
+ int status = 0;
+ status = i2cp->id_i2c->SR1;
+ while(TRUE);
+}
+
+// Accelerometer lis3lv02dq config
+static I2CSlaveConfig lis3 = {
+ NULL,
+ i2c_lis3_error_cb,
+ accel_rx_data,
+ ACCEL_RX_DEPTH,
+ 0,
+ 0,
+ accel_tx_data,
+ ACCEL_TX_DEPTH,
+ 0,
+ 0,
+ 0b0011101,
+ FALSE,
+};
+
+
+/**
+ * This treading need for convenient realize
+ * "read through write" process.
+ */
+static WORKING_AREA(I2CAccelThreadWA, 128);
+static Thread *i2c_accel_tp = NULL;
+static msg_t I2CAccelThread(void *arg) {
+ (void)arg;
+
+ int16_t acceleration_x = 0;
+ int16_t acceleration_y = 0;
+ int16_t acceleration_z = 0;
+
+ I2CDriver *i2cp;
+ msg_t msg;
+
+ while (TRUE) {
+ /* Waiting for wake up */
+ chSysLock();
+ i2c_accel_tp = chThdSelf();
+ chSchGoSleepS(THD_STATE_SUSPENDED);
+ msg = chThdSelf()->p_msg; /* Retrieving the message, optional.*/
+ chSysUnlock();
+
+ /***************** Perform processing here. ***************************/
+ i2cp = (I2CDriver *)msg;
+
+ /* collect measured data */
+ acceleration_x = lis3.rxbuf[0] + (lis3.rxbuf[1] << 8);
+ acceleration_y = lis3.rxbuf[2] + (lis3.rxbuf[3] << 8);
+ acceleration_z = lis3.rxbuf[4] + (lis3.rxbuf[5] << 8);
+ }
+ return 0;
+}
+
+
+
+/* This callback raise up when transfer finished */
+static void i2c_lis3_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+
+ if (i2cp->id_slave_config->restart){ // is it restart flag set to TRUE
+ /* reset restart flag */
+ i2cp->id_slave_config->restart = FALSE;
+ /* now send restart and read acceleration data.
+ * Function i2cMasterReceive() send restart implicitly. */
+ i2cMasterReceive(i2cp, i2cscfg);
+ }
+ else{
+ /* If jump here than requested data have been read.
+ * Stop communication, release bus and wake up processing thread */
+ i2cMasterStop(i2cp);
+ i2cReleaseBus(&I2CD1);
+
+ // wake up heavy thread for data processing
+ if (i2c_accel_tp != NULL) {
+ i2c_accel_tp->p_msg = (msg_t)i2cp;
+ chSchReadyI(i2c_accel_tp);
+ i2c_accel_tp = NULL;
+ }
+ }
+}
+
+/**
+ * Init function. Here we will also start personal serving thread.
+ */
+int init_lis3(void){
+
+ /* Starting the accelerometer serving thread.*/
+ i2c_accel_tp = chThdCreateStatic(I2CAccelThreadWA,
+ sizeof(I2CAccelThreadWA),
+ HIGHPRIO,
+ I2CAccelThread,
+ NULL);
+
+ /* wait thread statup */
+ while (i2c_accel_tp == NULL)
+ chThdSleepMilliseconds(1);
+
+ lis3.txbufhead = 0;
+ lis3.rxbufhead = 0;
+
+
+ /* Write configuration data */
+ lis3.txbytes = 4;
+ /* fill transmit buffer. See datasheet to understand what we write */
+ lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT;
+ lis3.txbuf[1] = 0b11100111;
+ lis3.txbuf[2] = 0b01000001;
+ lis3.txbuf[3] = 0b00000000;
+
+ /* setting callback */
+ lis3.id_callback = i2c_lis3_cb;
+
+ i2cAcquireBus(&I2CD1);
+
+ /* sending */
+ i2cMasterTransmit(&I2CD1, &lis3);
+
+ return 0;
+}
+
+/**
+ *
+ */
+void request_acceleration_data(void){
+
+ /* fill transmit buffer with address of register that we want to read */
+ lis3.txbufhead = 0;
+ lis3.txbuf[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address
+ lis3.txbytes = 1;
+
+ /* tune receive structures */
+ lis3.rxbufhead = 0;
+ lis3.rxbytes = 6;
+
+ /* Now it is most important action. We must set restart flag to TRUE.
+ * And in callback function we must reset it to FALSE after sending
+ * of register address. In TMP75 and MAX1236 this flag does not use. */
+ lis3.restart = TRUE;
+
+ /* talk to slave what we want from it */
+ i2cAcquireBus(&I2CD1);
+ i2cMasterTransmit(&I2CD1, &lis3);
+}
+
diff --git a/testhal/STM32/I2C/lis3.h b/testhal/STM32/I2C/lis3.h new file mode 100644 index 000000000..e50359bde --- /dev/null +++ b/testhal/STM32/I2C/lis3.h @@ -0,0 +1,28 @@ +#include <stdlib.h>
+#include "ch.h"
+
+#ifndef LIS3_H_
+#define LIS3_H_
+
+
+
+/* buffers depth */
+#define ACCEL_RX_DEPTH 8
+#define ACCEL_TX_DEPTH 8
+
+/* autoincrement bit position. This bit needs to perform reading of
+ * multiple bytes at one request */
+#define AUTO_INCREMENT_BIT (1<<7)
+
+/* slave specific addresses */
+#define ACCEL_STATUS_REG 0x27
+#define ACCEL_CTRL_REG1 0x20
+#define ACCEL_OUT_DATA 0x28
+
+
+
+inline int init_lis3(void);
+inline void request_acceleration_data(void);
+
+
+#endif /* LIS3_H_ */
diff --git a/testhal/STM32/I2C/main.c b/testhal/STM32/I2C/main.c new file mode 100644 index 000000000..793f73f49 --- /dev/null +++ b/testhal/STM32/I2C/main.c @@ -0,0 +1,120 @@ +/**
+ * Lets imagine that we have board with LIS3LV02DL accelerometer on channel #1
+ * and MAX1236 ADC, TMP75 thermometer on channel #2.
+ *
+ * NOTE: I assume, that you have datasheets on all this stuff.
+ *
+ * NOTE: Also, I assume, that you know how to I2C works.
+ *
+ * In order from simplicity to complexity:
+ * TMP75
+ * MAX1236
+ * LIS3LV02DL
+ *
+ * Project splitted to separate source files for each device.
+ *
+ * Data from sensors we will be read from different thread sleeping different
+ * amount of time.
+ */
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#include "i2c_pns.h"
+#include "tmp75.h"
+#include "max1236.h"
+#include "lis3.h"
+
+
+
+/* Temperature polling thread */
+static WORKING_AREA(PollTmp75ThreadWA, 128);
+static msg_t PollTmp75Thread(void *arg) {
+ (void)arg;
+ systime_t time = chTimeNow();
+
+ while (TRUE) {
+ time += MS2ST(1001);
+ /* Call reading function */
+ request_temperature();
+ chThdSleepUntil(time);
+ }
+ return 0;
+}
+
+/* MAX1236 polling thread */
+static WORKING_AREA(PollMax1236ThreadWA, 128);
+static msg_t PollMax1236Thread(void *arg) {
+ (void)arg;
+ systime_t time = chTimeNow();
+
+ while (TRUE) {
+ time += MS2ST(20);
+ /* Call reading function */
+ read_max1236();
+ chThdSleepUntil(time);
+ }
+ return 0;
+}
+
+
+static WORKING_AREA(PollAccelThreadWA, 128);
+static msg_t PollAccelThread(void *arg) {
+ (void)arg;
+ systime_t time = chTimeNow();
+
+ while (TRUE) {
+ time += MS2ST(2);
+ request_acceleration_data();
+ chThdSleepUntil(time);
+ }
+ return 0;
+}
+
+
+
+
+/*
+ * Entry point, note, the main() function is already a thread in the system
+ * on entry.
+ */
+int main(void) {
+
+ halInit();
+ chSysInit();
+
+ I2CInit_pns();
+
+ /* Create temperature thread */
+ chThdCreateStatic(PollTmp75ThreadWA,
+ sizeof(PollTmp75ThreadWA),
+ NORMALPRIO,
+ PollTmp75Thread,
+ NULL);
+
+
+ /* Create max1236 thread */
+ chThdCreateStatic(PollMax1236ThreadWA,
+ sizeof(PollMax1236ThreadWA),
+ NORMALPRIO,
+ PollMax1236Thread,
+ NULL);
+
+
+ /* Create accelerometer thread */
+ chThdCreateStatic(PollAccelThreadWA,
+ sizeof(PollAccelThreadWA),
+ HIGHPRIO,
+ PollAccelThread,
+ NULL);
+
+
+ /* main loop that do nothing */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/STM32/I2C/main.h b/testhal/STM32/I2C/main.h new file mode 100644 index 000000000..1435a05e5 --- /dev/null +++ b/testhal/STM32/I2C/main.h @@ -0,0 +1,19 @@ +/*
+ * main.h
+ *
+ * Created on: 25.03.2011
+ * Author: barthess
+ */
+
+#ifndef MAIN_H_
+#define MAIN_H_
+
+
+// глобальные флаги
+#define GET_FILTERED_RAW_GYRO TRUE
+#define GET_FILTERED_RAW_ACCEL TRUE
+
+
+
+
+#endif /* MAIN_H_ */
diff --git a/testhal/STM32/I2C/max1236.c b/testhal/STM32/I2C/max1236.c new file mode 100644 index 000000000..e7e253916 --- /dev/null +++ b/testhal/STM32/I2C/max1236.c @@ -0,0 +1,106 @@ +/**
+ * Maxim ADC has not so suitable default settings after startup.
+ * So we will create init function to tune this ADC.
+ */
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#include "max1236.h"
+
+// Data buffers
+static i2cblock_t max1236_rx_data[MAX1236_RX_DEPTH];
+static i2cblock_t max1236_tx_data[MAX1236_TX_DEPTH];
+
+/* Error trap */
+static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+ (void)i2cscfg;
+ int status = 0;
+ status = i2cp->id_i2c->SR1;
+ while(TRUE);
+}
+
+
+/* This callback raise up when transfer finished */
+static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+ uint16_t ch1 = 0;
+ uint16_t ch2 = 0;
+ uint16_t ch3 = 0;
+ uint16_t ch4 = 0;
+
+ /* send stop */
+ i2cMasterStop(i2cp);
+
+ /* unlock bus */
+ i2cReleaseBus(&I2CD2);
+
+ /* get ADC data */
+ ch1 = ((i2cscfg->rxbuf[0] & 0xF) << 8) + i2cscfg->rxbuf[1];
+ ch2 = ((i2cscfg->rxbuf[2] & 0xF) << 8) + i2cscfg->rxbuf[3];
+ ch3 = ((i2cscfg->rxbuf[4] & 0xF) << 8) + i2cscfg->rxbuf[5];
+ ch4 = ((i2cscfg->rxbuf[6] & 0xF) << 8) + i2cscfg->rxbuf[7];
+}
+
+
+// ADC maxim MAX1236 config
+static I2CSlaveConfig max1236 = {
+ NULL, // first set to NULL. We will set this pointer to the function later.
+ i2c_max1236_error_cb,
+ max1236_rx_data,
+ MAX1236_RX_DEPTH,
+ 0,
+ 0,
+ max1236_tx_data,
+ MAX1236_TX_DEPTH,
+ 0,
+ 0,
+ 0b0110100,
+ FALSE,
+};
+
+
+/**
+ * Initilization routine. See datasheet on page 13 to understand
+ * how to initialize ADC.
+ */
+void init_max1236(void){
+ /* lock bus */
+ i2cAcquireBus(&I2CD2);
+
+ /* this data we must send to IC to setup ADC settings */
+ max1236.txbufhead = 0;
+ max1236.txbytes = 2; // total 2 bytes to be sent
+ max1236.txbuf[0] = 0b10000011; // config register content. Consult datasheet
+ max1236.txbuf[1] = 0b00000111; // config register content. Consult datasheet
+
+ // transmit out 2 bytes
+ i2cMasterTransmit(&I2CD2, &max1236);
+ while(I2CD2.id_state != I2C_READY) // wait
+ chThdSleepMilliseconds(1);
+
+ /* now add pointer to callback function */
+ max1236.id_callback = i2c_max1236_cb;
+
+ /*clear transmitting structures */
+ max1236.txbytes = 0;
+ max1236.txbufhead = 0;
+
+ /* unlock bus */
+ i2cReleaseBus(&I2CD2);
+}
+
+
+/* Now simply read 8 bytes to get all 4 ADC channels */
+void read_max1236(void){
+ /* tune receive buffer */
+ max1236.rxbufhead = 0;
+ max1236.rxbytes = 8;
+
+ /* lock bus */
+ i2cAcquireBus(&I2CD2);
+
+ /* start reading */
+ i2cMasterReceive(&I2CD2, &max1236);
+}
diff --git a/testhal/STM32/I2C/max1236.h b/testhal/STM32/I2C/max1236.h new file mode 100644 index 000000000..aff466cf4 --- /dev/null +++ b/testhal/STM32/I2C/max1236.h @@ -0,0 +1,14 @@ +#include "ch.h"
+
+#ifndef MAX1236_H_
+#define MAX1236_H_
+
+
+#define MAX1236_RX_DEPTH 8
+#define MAX1236_TX_DEPTH 2
+
+
+void init_max1236(void);
+void read_max1236(void);
+
+#endif /* MAX1236_H_ */
diff --git a/testhal/STM32/I2C/mcuconf.h b/testhal/STM32/I2C/mcuconf.h new file mode 100644 index 000000000..92f8e17d8 --- /dev/null +++ b/testhal/STM32/I2C/mcuconf.h @@ -0,0 +1,131 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM32 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE 9
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_MCO STM32_MCO_NOCLOCK
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_ADC1_DMA_PRIORITY 3
+#define STM32_ADC_ADC1_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 TRUE
+#define STM32_PWM_USE_TIM4 TRUE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_DMA_PRIORITY 2
+#define STM32_SPI_SPI2_DMA_PRIORITY 2
+#define STM32_SPI_SPI3_DMA_PRIORITY 2
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 TRUE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 TRUE
+#define STM32_I2C_USE_I2C2 TRUE
+#define STM32_I2C_I2C1_IRQ_PRIORITY 11
+#define STM32_I2C_I2C2_IRQ_PRIORITY 11
+#define STM32_I2C_I2C1_DMA_PRIORITY 4
+#define STM32_I2C_I2C2_DMA_PRIORITY 4
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
diff --git a/testhal/STM32/I2C/tmp75.c b/testhal/STM32/I2C/tmp75.c new file mode 100644 index 000000000..4d9923881 --- /dev/null +++ b/testhal/STM32/I2C/tmp75.c @@ -0,0 +1,72 @@ +/**
+ * TMP75 is most simple I2C device in our case. It is already useful with
+ * default settings after powerup.
+ * You only must read 2 sequential bytes from it.
+ */
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#include "tmp75.h"
+
+
+// input buffer
+static i2cblock_t tmp75_rx_data[TMP75_RX_DEPTH];
+static i2cblock_t tmp75_tx_data[TMP75_TX_DEPTH];
+
+// Simple error trap
+static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+ (void)i2cscfg;
+ int status = 0;
+ status = i2cp->id_i2c->SR1;
+ while(TRUE);
+}
+
+/* This callback raise up when transfer finished */
+static void i2c_tmp75_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+ int16_t temperature = 0;
+
+ /* Manually send stop signal to the bus. This is important! */
+ i2cMasterStop(i2cp);
+ /* unlock bus */
+ i2cReleaseBus(&I2CD2);
+
+ /* store temperature value */
+ temperature = (i2cscfg->rxbuf[0] << 8) + i2cscfg->rxbuf[1];
+
+}
+
+// Fill TMP75 config.
+static I2CSlaveConfig tmp75 = {
+ i2c_tmp75_cb,
+ i2c_tmp75_error_cb,
+ tmp75_rx_data,
+ TMP75_RX_DEPTH,
+ 0,
+ 0,
+ tmp75_tx_data,
+ TMP75_TX_DEPTH,
+ 0,
+ 0,
+ 0b1001000,
+ FALSE,
+};
+
+/* This is main function. */
+void request_temperature(void){
+ tmp75.txbytes = 0; // set to zero just to be safe
+
+ /* tune receiving buffer */
+ tmp75.rxbufhead = 0;// point to beginig of buffer
+ tmp75.rxbytes = 2; // we need read 2 bytes
+
+ /* get exclusive access to the bus */
+ i2cAcquireBus(&I2CD2);
+
+ /* start receiving process in background and return */
+ i2cMasterReceive(&I2CD2, &tmp75);
+}
+
+
diff --git a/testhal/STM32/I2C/tmp75.h b/testhal/STM32/I2C/tmp75.h new file mode 100644 index 000000000..ab4b5fa9b --- /dev/null +++ b/testhal/STM32/I2C/tmp75.h @@ -0,0 +1,13 @@ +#ifndef TMP75_H_
+#define TMP75_H_
+
+
+
+/* buffers depth */
+#define TMP75_RX_DEPTH 2
+#define TMP75_TX_DEPTH 2
+
+void init_tmp75(void);
+void request_temperature(void);
+
+#endif /* TMP75_H_ */
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