diff options
Diffstat (limited to 'os/nil')
26 files changed, 5008 insertions, 0 deletions
diff --git a/os/nil/include/nil.h b/os/nil/include/nil.h new file mode 100644 index 000000000..161c79a6d --- /dev/null +++ b/os/nil/include/nil.h @@ -0,0 +1,819 @@ +/*
+ Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
+
+ This file is part of Nil RTOS.
+
+ Nil RTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Nil RTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file nil.h
+ * @brief Nil RTOS main header file.
+ * @details This header includes all the required kernel headers so it is the
+ * only header you usually need to include in your application.
+ *
+ * @addtogroup nil
+ * @{
+ */
+
+#ifndef _NIL_H_
+#define _NIL_H_
+
+typedef struct nil_thread thread_t;
+
+#include "nilconf.h"
+#include "niltypes.h"
+#include "nilcore.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Nil RTOS identification
+ * @{
+ */
+#define _NIL_ /**< @brief Nil RTOS identification.*/
+
+#define CH_KERNEL_VERSION "0.1.0alpha"
+
+#define CH_KERNEL_MAJOR 0
+#define CH_KERNEL_MINOR 1
+#define CH_KERNEL_PATCH 0
+/** @} */
+
+/**
+ * @name Wakeup messages
+ * @{
+ */
+#define MSG_OK 0 /**< @brief Normal wakeup message. */
+#define MSG_TIMEOUT -1 /**< @brief Wake-up caused by a timeout
+ condition. */
+#define MSG_RESET -2 /**< @brief Wake-up caused by a reset
+ condition. */
+/** @} */
+
+/**
+ * @name Special time constants
+ * @{
+ */
+/**
+ * @brief Zero time specification for some functions with a timeout
+ * specification.
+ * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
+ * see the specific function documentation.
+ */
+#define TIME_IMMEDIATE ((systime_t)-1)
+
+/**
+ * @brief Infinite time specification for all functions with a timeout
+ * specification.
+ */
+#define TIME_INFINITE ((systime_t)0)
+/** @} */
+
+/**
+ * @name Thread state related macros
+ * @{
+ */
+#define NIL_STATE_READY 0 /**< @brief Thread ready or executing. */
+#define NIL_STATE_SLEEPING 1 /**< @brief Thread sleeping. */
+#define NIL_STATE_SUSP 2 /**< @brief Thread suspended. */
+#define NIL_STATE_WTSEM 3 /**< @brief Thread waiting on semaphore.*/
+#define NIL_STATE_WTOREVT 4 /**< @brief Thread waiting for events. */
+#define NIL_THD_IS_READY(tr) ((tr)->state == NIL_STATE_READY)
+#define NIL_THD_IS_SLEEPING(tr) ((tr)->state == NIL_STATE_SLEEPING)
+#define NIL_THD_IS_SUSP(tr) ((tr)->state == NIL_STATE_SUSP)
+#define NIL_THD_IS_WTSEM(tr) ((tr)->state == NIL_STATE_WTSEM)
+#define NIL_THD_IS_WTOREVT(tr) ((tr)->state == NIL_STATE_WTOREVT)
+/** @} */
+
+/**
+ * @name Events related macros
+ * @{
+ */
+/**
+ * @brief All events allowed mask.
+ */
+#define ALL_EVENTS ((eventmask_t)-1)
+
+/**
+ * @brief Returns an event mask from an event identifier.
+ */
+#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid)))
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of user threads in the application.
+ * @note This number is not inclusive of the idle thread which is
+ * implicitly handled.
+ */
+#if !defined(NIL_CFG_NUM_THREADS) || defined(__DOXYGEN__)
+#define NIL_CFG_NUM_THREADS 2
+#endif
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(NIL_CFG_ST_RESOLUTION) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_RESOLUTION 32
+#endif
+
+/**
+ * @brief System tick frequency.
+ * @note This value together with the @p NIL_CFG_ST_RESOLUTION
+ * option defines the maximum amount of time allowed for
+ * timeouts.
+ */
+#if !defined(NIL_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_FREQUENCY 100
+#endif
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#if !defined(NIL_CFG_ST_TIMEDELTA) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_TIMEDELTA 0
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(NIL_CFG_USE_EVENTS) || defined(__DOXYGEN__)
+#define NIL_CFG_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief System assertions.
+ */
+#if !defined(NIL_CFG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define NIL_CFG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Stack check.
+ */
+#if !defined(NIL_CFG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define NIL_CFG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#if !defined(NIL_CFG_THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define NIL_CFG_THREAD_EXT_FIELDS
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if NIL_CFG_NUM_THREADS < 1
+#error "at least one thread must be defined"
+#endif
+
+#if NIL_CFG_NUM_THREADS > 12
+#error "Nil is not recommended for thread-intensive applications, consider" \
+ "ChibiOS/RT instead"
+#endif
+
+#if (NIL_CFG_ST_RESOLUTION != 16) && (NIL_CFG_ST_RESOLUTION != 32)
+#error "invalid NIL_CFG_ST_RESOLUTION specified, must be 16 or 32"
+#endif
+
+#if NIL_CFG_ST_FREQUENCY <= 0
+#error "invalid NIL_CFG_ST_FREQUENCY specified, must be greated than zero"
+#endif
+
+#if (NIL_CFG_ST_TIMEDELTA < 0) || (NIL_CFG_ST_TIMEDELTA == 1)
+#error "invalid NIL_CFG_ST_TIMEDELTA specified, must " \
+ "be zero or greater than one"
+#endif
+
+#if NIL_CFG_ENABLE_ASSERTS
+#define NIL_DBG_ENABLED TRUE
+#else
+#define NIL_DBG_ENABLED FALSE
+#endif
+
+/** Boundaries of the idle thread boundaries, only required if stack checking
+ is enabled.*/
+#if NIL_CFG_ENABLE_STACK_CHECK
+extern stkalign_t __main_thread_stack_base__, __main_thread_stack_end__;
+
+#define THD_IDLE_BASE (&__main_thread_stack_base__)
+#define THD_IDLE_END (&__main_thread_stack_end__)
+#else
+#define THD_IDLE_BASE NULL
+#define THD_IDLE_END NULL
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of internal context structure.
+ */
+typedef struct port_intctx intctx_t;
+
+/**
+ * @brief Type of a structure representing a counting semaphore.
+ */
+typedef struct {
+ volatile cnt_t cnt; /**< @brief Semaphore counter. */
+} semaphore_t;
+
+/**
+ * @brief Thread function.
+ */
+typedef void (*tfunc_t)(void *);
+
+/**
+ * @brief Type of a structure representing a thread static configuration.
+ */
+typedef struct nil_thread_cfg thread_config_t;
+
+/**
+ * @brief Type of a structure representing a thread.
+ */
+typedef struct nil_thread thread_t;
+
+/**
+ * @brief Structure representing a thread static configuration.
+ */
+struct nil_thread_cfg {
+ stkalign_t *wbase; /**< @brief Thread working area base. */
+ stkalign_t *wend; /**< @brief Thread working area end. */
+ const char *namep; /**< @brief Thread name, for debugging. */
+ tfunc_t funcp; /**< @brief Thread function. */
+ void *arg; /**< @brief Thread function argument. */
+};
+
+/**
+ * @brief Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief Structure representing a thread.
+ */
+struct nil_thread {
+ intctx_t *ctxp; /**< @brief Pointer to internal context. */
+ tstate_t state; /**< @brief Thread state. */
+ /* Note, the following union contains a pointer while the thread is in a
+ sleeping state (!NIL_THD_IS_READY()) else contains the wake-up message.*/
+ union {
+ msg_t msg; /**< @brief Wake-up message. */
+ void *p; /**< @brief Generic pointer. */
+ thread_reference_t *trp; /**< @brief Pointer to thread reference. */
+ semaphore_t *semp; /**< @brief Pointer to semaphore. */
+#if NIL_CFG_USE_EVENTS
+ eventmask_t ewmask; /**< @brief Enabled events mask. */
+#endif
+ } u1;
+ volatile systime_t timeout;/**< @brief Timeout counter, zero
+ if disabled. */
+#if NIL_CFG_USE_EVENTS
+ eventmask_t epmask; /**< @brief Pending events mask. */
+#endif
+#if NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+ stkalign_t *stklim;/**< @brief Thread stack boundary. */
+#endif
+ /* Optional extra fields.*/
+ NIL_CFG_THREAD_EXT_FIELDS
+};
+
+/**
+ * @brief System data structure.
+ * @note This structure contain all the data areas used by the OS except
+ * stacks.
+ */
+typedef struct {
+ /**
+ * @brief Pointer to the running thread.
+ */
+ thread_t *current;
+ /**
+ * @brief Pointer to the next thread to be executed.
+ * @note This pointer must point at the same thread pointed by @p currp
+ * or to an higher priority thread if a switch is required.
+ */
+ thread_t *next;
+#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
+ /**
+ * @brief System time.
+ */
+ systime_t systime;
+#endif
+#if NIL_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
+ /**
+ * @brief System time of the last tick event.
+ */
+ systime_t lasttime;
+ /**
+ * @brief Time of the next scheduled tick event.
+ */
+ systime_t nexttime;
+#endif
+ /**
+ * @brief Thread structures for all the defined threads.
+ */
+ thread_t threads[NIL_CFG_NUM_THREADS + 1];
+#if NIL_DBG_ENABLED || defined(__DOXYGEN__)
+ /**
+ * @brief Panic message.
+ * @note This field is only present if some debug options have been
+ * activated.
+ */
+ const char *dbg_panic_msg;
+#endif
+} nil_system_t;
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name Threads tables definition macros
+ * @{
+ */
+/**
+ * @brief Start of user threads table.
+ */
+#define THD_TABLE_BEGIN \
+ const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1] = {
+
+/**
+ * @brief Entry of user threads table
+ */
+#define THD_TABLE_ENTRY(wap, name, funcp, arg) \
+ {wap, (wap) + sizeof (wap), name, funcp, arg},
+
+/**
+ * @brief End of user threads table.
+ */
+#define THD_TABLE_END \
+ {THD_IDLE_BASE, THD_IDLE_END, "idle", 0, NULL} \
+};
+/** @} */
+
+/**
+ * @name Working Areas and Alignment
+ */
+/**
+ * @brief Enforces a correct alignment for a stack area size value.
+ *
+ * @param[in] n the stack size to be aligned to the next stack
+ * alignment boundary
+ * @return The aligned stack size.
+ *
+ * @api
+ */
+#define THD_ALIGN_STACK_SIZE(n) \
+ ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
+
+/**
+ * @brief Calculates the total Working Area size.
+ *
+ * @param[in] n the stack size to be assigned to the thread
+ * @return The total used memory in bytes.
+ *
+ * @api
+ */
+#define THD_WORKING_AREA_SIZE(n) \
+ THD_ALIGN_STACK_SIZE(sizeof(thread_t) + PORT_WA_SIZE(n))
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ *
+ * @api
+ */
+#define THD_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)]
+/** @} */
+
+/**
+ * @name Threads abstraction macros
+ */
+/**
+ * @brief Thread declaration macro.
+ * @note Thread declarations should be performed using this macro because
+ * the port layer could define optimizations for thread functions.
+ */
+#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg)
+/** @} */
+
+/**
+ * @name ISRs abstraction macros
+ */
+/**
+ * @brief IRQ handler enter code.
+ * @note Usually IRQ handlers functions are also declared naked.
+ * @note On some architectures this macro can be empty.
+ *
+ * @special
+ */
+#define CH_IRQ_PROLOGUE() PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ handler exit code.
+ * @note Usually IRQ handlers function are also declared naked.
+ *
+ * @special
+ */
+#define CH_IRQ_EPILOGUE() PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief Standard normal IRQ handler declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ *
+ * @special
+ */
+#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Fast ISRs abstraction macros
+ */
+/**
+ * @brief Standard fast IRQ handler declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ * @note Not all architectures support fast interrupts.
+ *
+ * @special
+ */
+#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name Time conversion utilities
+ * @{
+ */
+/**
+ * @brief Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec number of seconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define S2ST(sec) \
+ ((systime_t)((sec) * NIL_CFG_ST_FREQUENCY))
+
+/**
+ * @brief Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec number of milliseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define MS2ST(msec) \
+ ((systime_t)(((((uint32_t)(msec)) * \
+ ((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000UL) + 1UL))
+
+/**
+ * @brief Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec number of microseconds
+ * @return The number of ticks.
+ *
+ * @api
+ */
+#define US2ST(usec) \
+ ((systime_t)(((((uint32_t)(usec)) * \
+ ((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000000UL) + 1UL))
+/** @} */
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysDisable() port_disable()
+
+/**
+ * @brief Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysEnable() port_enable()
+
+/**
+ * @brief Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysLock() port_lock()
+
+/**
+ * @brief Leaves the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysUnlock() port_unlock()
+
+/**
+ * @brief Enters the kernel lock mode from within an interrupt handler.
+ * @note This API may do nothing on some architectures, it is required
+ * because on ports that support preemptable interrupt handlers
+ * it is required to raise the interrupt mask to the same level of
+ * the system mutual exclusion zone.<br>
+ * It is good practice to invoke this API before invoking any I-class
+ * syscall from an interrupt handler.
+ * @note This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+#define chSysLockFromISR() port_lock_from_isr()
+
+/**
+ * @brief Leaves the kernel lock mode from within an interrupt handler.
+ *
+ * @note This API may do nothing on some architectures, it is required
+ * because on ports that support preemptable interrupt handlers
+ * it is required to raise the interrupt mask to the same level of
+ * the system mutual exclusion zone.<br>
+ * It is good practice to invoke this API after invoking any I-class
+ * syscall from an interrupt handler.
+ * @note This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+#define chSysUnlockFromISR() port_unlock_from_isr()
+
+/**
+ * @brief Evaluates if a reschedule is required.
+ *
+ * @retval true if there is a thread that must go in running state
+ * immediately.
+ * @retval false if preemption is not required.
+ *
+ * @iclass
+ */
+#define chSchIsRescRequiredI() ((bool)(nil.current != nil.next))
+
+/**
+ * @brief Returns a pointer to the current @p thread_t.
+ *
+ * @xclass
+ */
+#define chThdGetSelfX() nil.current
+
+/**
+ * @brief Delays the invoking thread for the specified number of seconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system clock.
+ * @note The maximum specified value is implementation dependent.
+ *
+ * @param[in] sec time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * milliseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system clock.
+ * @note The maximum specified value is implementation dependent.
+ *
+ * @param[in] msec time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
+
+/**
+ * @brief Delays the invoking thread for the specified number of
+ * microseconds.
+ * @note The specified time is rounded up to a value allowed by the real
+ * system clock.
+ * @note The maximum specified value is implementation dependent.
+ *
+ * @param[in] usec time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] timeout the delay in system ticks
+ *
+ * @sclass
+ */
+#define chThdSleepS(timeout) chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, timeout)
+
+/**
+ * @brief Suspends the invoking thread until the system time arrives to the
+ * specified value.
+ *
+ * @param[in] time absolute system time
+ *
+ * @sclass
+ */
+#define chThdSleepUntilS(time) \
+ chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, (time) - chVTGetSystemTimeX())
+
+/**
+ * @brief Initializes a semaphore with the specified counter value.
+ *
+ * @param[out] sp pointer to a @p semaphore_t structure
+ * @param[in] n initial value of the semaphore counter. Must be
+ * non-negative.
+ *
+ * @init
+ */
+#define chSemObjectInit(sp, n) ((sp)->cnt = n)
+
+/**
+ * @brief Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval CH_MSG_OK if the thread has not stopped on the semaphore or the
+ * semaphore has been signaled.
+ * @retval CH_MSG_RST if the semaphore has been reset using @p chSemReset().
+ *
+ * @api
+ */
+#define chSemWait(sp) chSemWaitTimeout(sp, TIME_INFINITE)
+
+/**
+ * @brief Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval CH_MSG_OK if the thread has not stopped on the semaphore or the
+ * semaphore has been signaled.
+ * @retval CH_MSG_RST if the semaphore has been reset using @p chSemReset().
+ *
+ * @sclass
+ */
+#define chSemWaitS(sp) chSemWaitTimeoutS(sp, TIME_INFINITE)
+
+/**
+ * @brief Returns the semaphore counter current value.
+ *
+ * @iclass
+ */
+#define chSemGetCounterI(sp) ((sp)->cnt)
+
+/**
+ * @brief Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ * invocation.
+ * @note The counter can reach its maximum and then restart from zero.
+ * @note This function can be called from any context but its atomicity
+ * is not guaranteed on architectures whose word size is less than
+ * @systime_t size.
+ *
+ * @return The system time in ticks.
+ *
+ * @xclass
+ */
+#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
+#define chVTGetSystemTimeX() (nil.systime)
+#else
+#define chVTGetSystemTimeX() port_timer_get_time()
+#endif
+
+/**
+ * @brief Returns the elapsed time since the specified start time.
+ *
+ * @param[in] start start time
+ * @return The elapsed time.
+ *
+ * @xclass
+ */
+#define chVTTimeElapsedSinceX(start) \
+ ((systime_t)(chVTGetSystemTimeX() - start))
+
+/**
+ * @brief Checks if the specified time is within the specified time window.
+ * @note When start==end then the function returns always true because the
+ * whole time range is specified.
+ * @note This function can be called from any context.
+ *
+ * @param[in] time the time to be verified
+ * @param[in] start the start of the time window (inclusive)
+ * @param[in] end the end of the time window (non inclusive)
+ * @retval true current time within the specified time window.
+ * @retval false current time not within the specified time window.
+ *
+ * @xclass
+ */
+#define chVTIsTimeWithinX(time, start, end) \
+ ((bool)((time) - (start) < (end) - (start)))
+
+/**
+ * @brief Condition assertion.
+ * @details If the condition check fails then the kernel panics with a
+ * message and halts.
+ * @note The condition is tested only if the @p NIL_CFG_ENABLE_ASSERTS
+ * switch is specified in @p nilconf.h else the macro does nothing.
+ * @note The remark string is not currently used except for putting a
+ * comment in the code about the assertion.
+ *
+ * @param[in] c the condition to be verified to be true
+ * @param[in] r a remark string
+ *
+ * @api
+ */
+#if !defined(chDbgAssert)
+#define chDbgAssert(c, r) do { \
+ if (NIL_CFG_ENABLE_ASSERTS && !(c)) \
+ chSysHalt(__func__); \
+} while (0)
+#endif /* !defined(chDbgAssert) */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern nil_system_t nil;
+extern const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void chSysInit(void);
+ void chSysHalt(const char *reason);
+ void chSysTimerHandlerI(void);
+ syssts_t chSysGetStatusAndLockX(void);
+ void chSysRestoreStatusX(syssts_t sts);
+ thread_t *chSchReadyI(thread_t *tp, msg_t msg);
+ void chSchRescheduleS(void);
+ msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout);
+ msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+ void chThdResumeI(thread_reference_t *trp, msg_t msg);
+ void chThdSleep(systime_t time);
+ void chThdSleepUntil(systime_t time);
+ msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time);
+ msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time);
+ void chSemSignal(semaphore_t *sp);
+ void chSemSignalI(semaphore_t *sp);
+ void chSemReset(semaphore_t *sp, cnt_t n);
+ void chSemResetI(semaphore_t *sp, cnt_t n);
+ void chEvtSignal(thread_t *tp, eventmask_t mask);
+ void chEvtSignalI(thread_t *tp, eventmask_t mask);
+ eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout);
+ eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NIL_H_ */
+
+/** @} */
diff --git a/os/nil/nil.mk b/os/nil/nil.mk new file mode 100644 index 000000000..51f0e8083 --- /dev/null +++ b/os/nil/nil.mk @@ -0,0 +1,5 @@ +# List of all the ChibiOS/NIL kernel files.
+KERNSRC = ${CHIBIOS}/os/nil/src/nil.c
+
+# Required include directories
+KERNINC = ${CHIBIOS}/os/nil/include
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk new file mode 100644 index 000000000..6e63c076c --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M0 STM32F0xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v6m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F0xx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk new file mode 100644 index 000000000..742053e48 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M3 STM32F1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F1xx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk new file mode 100644 index 000000000..18df7e0a9 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M4 STM32F30x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk new file mode 100644 index 000000000..710062615 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M4 STM32F37x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F37x \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk new file mode 100644 index 000000000..6dacde089 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M0 STM32F4xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v6m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F4xx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk new file mode 100644 index 000000000..12894b1c0 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/NIL Cortex-M4 STM32L1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+ $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+ ${CHIBIOS}/os/ext/CMSIS/ST \
+ ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32L1xx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx \
+ ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s new file mode 100644 index 000000000..d824fd260 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s @@ -0,0 +1,122 @@ +/*
+ ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/NIL.
+
+ ChibiOS/NIL is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/NIL is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+ * @brief ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "nilconf.h"
+#include "nilcore.h"
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .set CONTEXT_OFFSET, 0
+ .set SCB_ICSR, 0xE000ED04
+ .set ICSR_PENDSVSET, 0x10000000
+ .set ICSR_NMIPENDSET, 0x80000000
+
+ .cpu cortex-m0
+ .fpu softvfp
+
+ .thumb
+ .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, lr}
+ mov r4, r8
+ mov r5, r9
+ mov r6, r10
+ mov r7, r11
+ push {r4, r5, r6, r7}
+ mov r3, sp
+ str r3, [r1, #CONTEXT_OFFSET]
+ ldr r3, [r0, #CONTEXT_OFFSET]
+ mov sp, r3
+ pop {r4, r5, r6, r7}
+ mov r8, r4
+ mov r9, r5
+ mov r10, r6
+ mov r11, r7
+ pop {r4, r5, r6, r7, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_thread_start
+_port_thread_start:
+ cpsie i
+ mov r0, r5
+ blx r4
+ mov r3, #0
+ bl chSysHalt
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch_from_isr
+_port_switch_from_isr:
+ bl chSchRescheduleS
+ .globl _port_exit_from_isr
+_port_exit_from_isr:
+ ldr r2, .L2
+ ldr r3, .L3
+ str r3, [r2, #0]
+#if CORTEX_ALTERNATE_SWITCH
+ cpsie i
+#endif
+.L1: b .L1
+
+ .align 2
+.L2: .word SCB_ICSR
+#if CORTEX_ALTERNATE_SWITCH
+.L3: .word ICSR_PENDSVSET
+#else
+.L3: .word ICSR_NMIPENDSET
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s new file mode 100644 index 000000000..27e5fcc9e --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s @@ -0,0 +1,120 @@ +/*
+ ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/NIL.
+
+ ChibiOS/NIL is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/NIL is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+ * @brief ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "nilconf.h"
+#include "nilcore.h"
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .set CONTEXT_OFFSET, 0
+ .set SCB_ICSR, 0xE000ED04
+ .set ICSR_PENDSVSET, 0x10000000
+
+ .syntax unified
+ .cpu cortex-m4
+#if CORTEX_USE_FPU
+ .fpu fpv4-sp-d16
+#else
+ .fpu softvfp
+#endif
+
+ .thumb
+ .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch
+_port_switch:
+ push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+ vpush {s16-s31}
+#endif
+ str sp, [r1, #CONTEXT_OFFSET]
+ ldr sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+ vpop {s16-s31}
+#endif
+ pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_thread_start
+_port_thread_start:
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ movs r3, #0
+ msr BASEPRI, r3
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ cpsie i
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+ mov r0, r5
+ blx r4
+ mov r3, #0
+ bl chSysHalt
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+ .thumb_func
+ .globl _port_switch_from_isr
+_port_switch_from_isr:
+ bl chSchRescheduleS
+ .globl _port_exit_from_isr
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+ movw r3, #:lower16:SCB_ICSR
+ movt r3, #:upper16:SCB_ICSR
+ mov r2, ICSR_PENDSVSET
+ str r2, [r3, #0]
+ cpsie i
+#else /* !CORTEX_SIMPLIFIED_PRIORITY */
+ svc #0
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+.L1: b .L1
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h new file mode 100644 index 000000000..cb0eda2d0 --- /dev/null +++ b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h @@ -0,0 +1,87 @@ +/*
+ ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/NIL.
+
+ ChibiOS/NIL is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/NIL is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/niltypes.h
+ * @brief ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then the
+ * realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) \
+ __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore.c b/os/nil/ports/ARMCMx/nilcore.c new file mode 100644 index 000000000..58b86e76b --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore.c @@ -0,0 +1,55 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/nilcore.c
+ * @brief ARM Cortex-Mx port code.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore.h b/os/nil/ports/ARMCMx/nilcore.h new file mode 100644 index 000000000..60202222a --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore.h @@ -0,0 +1,245 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/nilcore.h
+ * @brief ARM Cortex-Mx port macros and structures.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining a generic ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM
+
+/* The following code is not processed when the file is included from an
+ asm module because those intrinsic macros are not necessarily defined
+ by the assembler too.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#elif defined(__ICCARM__)
+#define PORT_COMPILER_NAME "IAR"
+
+#elif defined(__CC_ARM)
+#define PORT_COMPILER_NAME "RVCT"
+
+#else
+#error "unsupported compiler"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/** @} */
+
+/**
+ * @name Cortex-M variants
+ * @{
+ */
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M0PLUS 1 /**< @brief Cortex-M0+ variant. */
+#define CORTEX_M1 2 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+/** @} */
+
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p nilcore_timer.h, if this option is enabled then the file
+ * @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/*
+ * Inclusion of the appropriate CMSIS header for the selected device.
+ */
+#if CORTEX_MODEL == CORTEX_M0
+#include "core_cm0.h"
+#elif CORTEX_MODEL == CORTEX_M0PLUS
+#include "core_cm0plus.h"
+#elif CORTEX_MODEL == CORTEX_M3
+#include "core_cm3.h"
+#elif CORTEX_MODEL == CORTEX_M4
+#include "core_cm4.h"
+#else
+#error "unknown or unsupported Cortex-M model"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief Type of a generic ARM register.
+ */
+typedef void *regarm_t;
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ * @note In this architecture the stack alignment is enforced to 64 bits,
+ * 32 bits alignment is supported by hardware but deprecated by ARM,
+ * the implementation choice is to not offer the option.
+ */
+typedef uint64_t stkalign_t;
+
+/* The following declarations are there just for Doxygen documentation, the
+ real declarations are inside the sub-headers being specific for the
+ sub-architectures.*/
+#if defined(__DOXYGEN__)
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ * preemption-capable interrupt handler.
+ * @note It is implemented to match the Cortex-Mx exception context.
+ */
+struct port_extctx {};
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching.
+ */
+struct port_intctx {};
+#endif /* defined(__DOXYGEN__) */
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Total priority levels.
+ */
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ * priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY 0
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_PRIORITY(n) \
+ (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
+ (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIO_MASK(n) \
+ ((n) << (8 - CORTEX_PRIORITY_BITS))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) || \
+ (CORTEX_MODEL == CORTEX_M1)
+#include "nilcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "nilcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_timer.h b/os/nil/ports/ARMCMx/nilcore_timer.h new file mode 100644 index 000000000..a045ef544 --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore_timer.h @@ -0,0 +1,125 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/nilcore_timer.h
+ * @brief System timer header file.
+ *
+ * @addtogroup ARMCMx_TIMER
+ * @{
+ */
+
+#ifndef _NILCORE_TIMER_H_
+#define _NILCORE_TIMER_H_
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+#include "st.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+ stStartAlarm(time);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+ stStopAlarm();
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+ stSetAlarm(time);
+}
+
+/**
+ * @brief Returns the system time.
+ *
+ * @return The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+ return stGetCounter();
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+ return stGetAlarm();
+}
+
+#endif /* _NILCORE_TIMER_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.c b/os/nil/ports/ARMCMx/nilcore_v6m.c new file mode 100644 index 000000000..158e7d63d --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore_v6m.c @@ -0,0 +1,144 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file nilcore_v6m.c
+ * @brief ARMv6-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers. */
+/*===========================================================================*/
+
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief NMI vector.
+ * @details The NMI vector is used for exception mode re-entering after a
+ * context switch.
+ */
+void NMI_Handler(void) {
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Restoring the normal interrupts status.*/
+ port_unlock_from_isr();
+}
+#endif /* !CORTEX_ALTERNATE_SWITCH */
+
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ */
+void PendSV_Handler(void) {
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_ALTERNATE_SWITCH */
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief IRQ epilogue code.
+ *
+ * @param[in] lr value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+ if (lr != (regarm_t)0xFFFFFFF1) {
+ struct port_extctx *ctxp;
+
+ port_lock_from_isr();
+
+ /* The extctx structure is pointed by the PSP register.*/
+ ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Adding an artificial exception return context, there is no need to
+ populate it fully.*/
+ ctxp--;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Setting up a fake XPSR register value.*/
+ ctxp->xpsr = (regarm_t)0x01000000;
+
+ /* The exit sequence is different depending on if a preemption is
+ required or not.*/
+ if (chSchIsRescRequiredI()) {
+ /* Preemption is required we need to enforce a context switch.*/
+ ctxp->pc = (regarm_t)_port_switch_from_isr;
+ }
+ else {
+ /* Preemption not required, we just need to exit the exception
+ atomically.*/
+ ctxp->pc = (regarm_t)_port_exit_from_isr;
+ }
+
+ /* Note, returning without unlocking is intentional, this is done in
+ order to keep the rest of the context switch atomic.*/
+ }
+}
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.h b/os/nil/ports/ARMCMx/nilcore_v6m.h new file mode 100644 index 000000000..0e73cdc34 --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore_v6m.h @@ -0,0 +1,398 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file chcore_v6m.h
+ * @brief ARMv6-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V6M_H_
+#define _CHCORE_V6M_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "Cortex-M0"
+
+#elif (CORTEX_MODEL == CORTEX_M0PLUS)
+#define PORT_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
+#define PORT_CORE_VARIANT_NAME "Cortex-M0+"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define PORT_INFO "Preemption through NMI"
+#else
+#define PORT_INFO "Preemption through PendSV"
+#endif
+/** @} */
+
+/**
+ * @brief This port does not support a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p 0,
+ * this handler always has the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV 0
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
+#define PORT_IDLE_THREAD_STACK_SIZE 16
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE FALSE
+#endif
+
+/**
+ * @brief Alternate preemption method.
+ * @details Activating this option will make the Kernel use the PendSV
+ * handler for preemption instead of the NMI handler.
+ */
+#ifndef CORTEX_ALTERNATE_SWITCH
+#define CORTEX_ALTERNATE_SWITCH FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum usable priority for normal ISRs.
+ */
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define CORTEX_MAX_KERNEL_PRIORITY 1
+#else
+#define CORTEX_MAX_KERNEL_PRIORITY 0
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+ /* The documentation of the following declarations is in chconf.h in order
+ to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_thd;
+ regarm_t pc;
+ regarm_t xpsr;
+};
+
+struct port_intctx {
+ regarm_t r8;
+ regarm_t r9;
+ regarm_t r10;
+ regarm_t r11;
+ regarm_t r4;
+ regarm_t r5;
+ regarm_t r6;
+ regarm_t r7;
+ regarm_t lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
+ (tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) - \
+ sizeof(struct port_intctx)); \
+ (tp)->ctxp->r4 = (regarm_t)(pf); \
+ (tp)->ctxp->r5 = (regarm_t)(arg); \
+ (tp)->ctxp->lr = (regarm_t)(_port_thread_start); \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
+ sizeof(struct port_extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE() \
+ regarm_t _saved_lr; \
+ asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory")
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) { \
+ struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
+ if ((stkalign_t *)(r13 - 1) < (otp)->stklim) \
+ chSysHalt("stack overflow"); \
+ _port_switch(ntp, otp); \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(regarm_t lr);
+ void _port_switch_from_isr(void);
+ void _port_exit_from_isr(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+ NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return __get_PRIMASK();
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retvel false the word specified a disabled interrupts status.
+ * @retvel true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return (sts & 1) == 0;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details In this port this function disables interrupts globally.
+ */
+static inline void port_lock(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Kernel-unlock action.
+ * @details In this port this function enables interrupts globally.
+ */
+static inline void port_unlock(void) {
+
+ __enable_irq();
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @details In this port this function disables interrupts globally.
+ * @note Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+ port_lock();
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @details In this port this function enables interrupts globally.
+ * @note Same as @p port_lock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+ port_unlock();
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+ __enable_irq();
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ * @note Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+ __WFI;
+#endif
+}
+
+#endif /* _FROM_ASM_ */
+
+#endif /* _CHCORE_V6M_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.c b/os/nil/ports/ARMCMx/nilcore_v7m.c new file mode 100644 index 000000000..ac059e38d --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore_v7m.c @@ -0,0 +1,174 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file nilcore_v7m.c
+ * @brief ARMv7-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers. */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief SVC vector.
+ * @details The SVC vector is used for exception mode re-entering after a
+ * context switch.
+ * @note The PendSV vector is only used in advanced kernel mode.
+ */
+void SVC_Handler(void) {
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+#if CORTEX_USE_FPU
+ /* Restoring the special register FPCCR.*/
+ FPU->FPCCR = (uint32_t)ctxp->fpccr;
+ FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Restoring the normal interrupts status.*/
+ port_unlock_from_isr();
+}
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+
+#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ * @note The PendSV vector is only used in compact kernel mode.
+ */
+void PendSV_Handler(void) {
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ ctxp++;
+
+#if CORTEX_USE_FPU
+ /* Restoring the special register FPCCR.*/
+ FPU->FPCCR = (uint32_t)ctxp->fpccr;
+ FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Exception exit redirection to _port_switch_from_isr().
+ */
+void _port_irq_epilogue(void) {
+
+ port_lock_from_isr();
+ if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {
+
+ /* The port_extctx structure is pointed by the PSP register.*/
+ struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+ /* Adding an artificial exception return context, there is no need to
+ populate it fully.*/
+ ctxp--;
+
+ /* Writing back the modified PSP value.*/
+ __set_PSP((uint32_t)ctxp);
+
+ /* Setting up a fake XPSR register value.*/
+ ctxp->xpsr = (regarm_t)0x01000000;
+
+ /* The exit sequence is different depending on if a preemption is
+ required or not.*/
+ if (chSchIsRescRequiredI()) {
+ /* Preemption is required we need to enforce a context switch.*/
+ ctxp->pc = (regarm_t)_port_switch_from_isr;
+#if CORTEX_USE_FPU
+ /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
+ (void) __get_FPSCR();
+#endif
+ }
+ else {
+ /* Preemption not required, we just need to exit the exception
+ atomically.*/
+ ctxp->pc = (regarm_t)_port_exit_from_isr;
+ }
+
+#if CORTEX_USE_FPU
+ {
+ uint32_t fpccr;
+
+ /* Saving the special register SCB_FPCCR into the reserved offset of
+ the Cortex-M4 exception frame.*/
+ (ctxp + 1)->fpccr = (regarm_t)(fpccr = FPU->FPCCR);
+
+ /* Now the FPCCR is modified in order to not restore the FPU status
+ from the artificial return context.*/
+ FPU->FPCCR = fpccr | FPU_FPCCR_LSPACT_Msk;
+ }
+#endif
+
+ /* Note, returning without unlocking is intentional, this is done in
+ order to keep the rest of the context switch atomic.*/
+ return;
+ }
+ port_unlock_from_isr();
+}
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.h b/os/nil/ports/ARMCMx/nilcore_v7m.h new file mode 100644 index 000000000..ff2307495 --- /dev/null +++ b/os/nil/ports/ARMCMx/nilcore_v7m.h @@ -0,0 +1,554 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file chcore_v7m.h
+ * @brief ARMv7-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V7M_H_
+#define _CHCORE_V7M_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define PORT_ARCHITECTURE_ARM_v7ME
+#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
+#if CORTEX_USE_FPU
+#define PORT_CORE_VARIANT_NAME "Cortex-M4F"
+#else
+#define PORT_CORE_VARIANT_NAME "Cortex-M4"
+#endif
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define PORT_INFO "Advanced kernel mode"
+#else
+#define PORT_INFO "Compact kernel mode"
+#endif
+/** @} */
+
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE //TRUE
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 16
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE FALSE
+#endif
+
+/**
+ * @brief FPU support in context switch.
+ * @details Activating this option activates the FPU support in the kernel.
+ */
+#if !defined(CORTEX_USE_FPU)
+#define CORTEX_USE_FPU CORTEX_HAS_FPU
+#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
+/* This setting requires an FPU presence check in case it is externally
+ redefined.*/
+#error "the selected core does not have an FPU"
+#endif
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option makes the Kernel work in compact mode.
+ * In compact mode interrupts are disabled globally instead of
+ * raising the priority mask to some intermediate level.
+ */
+#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#if !defined(CORTEX_PRIORITY_SVCALL)
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+/* If it is externally redefined then better perform a validity check on it.*/
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+
+/**
+ * @brief NVIC VTOR initialization expression.
+ */
+#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
+#define CORTEX_VTOR_INIT 0x00000000
+#endif
+
+/**
+ * @brief NVIC PRIGROUP initialization expression.
+ * @details The default assigns all available priority bits as preemption
+ * priority with no sub-priority.
+ */
+#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
+#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief Maximum usable priority for normal ISRs.
+ */
+#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ */
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
+#else
+
+#define CORTEX_MAX_KERNEL_PRIORITY 0
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to
+ * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
+ * highest priority that cannot preempt the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* The documentation of the following declarations is in chconf.h in order
+ to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_thd;
+ regarm_t pc;
+ regarm_t xpsr;
+#if CORTEX_USE_FPU
+ regarm_t s0;
+ regarm_t s1;
+ regarm_t s2;
+ regarm_t s3;
+ regarm_t s4;
+ regarm_t s5;
+ regarm_t s6;
+ regarm_t s7;
+ regarm_t s8;
+ regarm_t s9;
+ regarm_t s10;
+ regarm_t s11;
+ regarm_t s12;
+ regarm_t s13;
+ regarm_t s14;
+ regarm_t s15;
+ regarm_t fpscr;
+ regarm_t fpccr;
+#endif /* CORTEX_USE_FPU */
+};
+
+struct port_intctx {
+#if CORTEX_USE_FPU
+ regarm_t s16;
+ regarm_t s17;
+ regarm_t s18;
+ regarm_t s19;
+ regarm_t s20;
+ regarm_t s21;
+ regarm_t s22;
+ regarm_t s23;
+ regarm_t s24;
+ regarm_t s25;
+ regarm_t s26;
+ regarm_t s27;
+ regarm_t s28;
+ regarm_t s29;
+ regarm_t s30;
+ regarm_t s31;
+#endif /* CORTEX_USE_FPU */
+ regarm_t r4;
+ regarm_t r5;
+ regarm_t r6;
+ regarm_t r7;
+ regarm_t r8;
+ regarm_t r9;
+ regarm_t r10;
+ regarm_t r11;
+ regarm_t lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
+ (tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) - \
+ sizeof(struct port_intctx)); \
+ (tp)->ctxp->r4 = (regarm_t)(pf); \
+ (tp)->ctxp->r5 = (regarm_t)(arg); \
+ (tp)->ctxp->lr = (regarm_t)(_port_thread_start); \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
+ sizeof(struct port_extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) { \
+ struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
+ if ((stkalign_t *)(r13 - 1) < (otp)->stklim) \
+ chSysHalt("stack overflow"); \
+ _port_switch(ntp, otp); \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+ void _port_switch_from_isr(void);
+ void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+ /* Initialization of the vector table and priority related settings.*/
+ SCB->VTOR = CORTEX_VTOR_INIT;
+
+ /* Initializing priority grouping.*/
+ NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
+
+ /* DWT cycle counter enable.*/
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+ /* Initialization of the system vectors used by the port.*/
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
+#endif
+ NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+ register uint32_t sts;
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ sts = __get_BASEPRI();
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ sts = __get_PRIMASK();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+ return sts;
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retvel false the word specified a disabled interrupts status.
+ * @retvel true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ return sts == CORTEX_BASEPRI_DISABLED;
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ return (sts & 1) == 0;
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details In this port this function raises the base priority to kernel
+ * level.
+ */
+static inline void port_lock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ __disable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Kernel-unlock action.
+ * @details In this port this function lowers the base priority to user
+ * level.
+ */
+static inline void port_unlock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+ __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ __enable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @details In this port this function raises the base priority to kernel
+ * level.
+ * @note Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+ port_lock();
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @details In this port this function lowers the base priority to user
+ * level.
+ * @note Same as @p port_unlock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+ port_unlock();
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ * @note In this port it disables all the interrupt sources by raising
+ * the priority mask to level 0.
+ */
+static inline void port_disable(void) {
+
+ __disable_irq();
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ * @note Interrupt sources above kernel level remains enabled.
+ * @note In this port it raises/lowers the base priority to kernel level.
+ */
+static inline void port_suspend(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+ __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+ __enable_irq();
+#else
+ __disable_irq();
+#endif
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ * @note In this port it lowers the base priority to user level.
+ */
+static inline void port_enable(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+ __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#endif
+ __enable_irq();
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ * @note Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+ __WFI;
+#endif
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+ return DWT->CYCCNT;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CHCORE_V7M_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/compilers/GCC/niltypes.h b/os/nil/ports/AVR/compilers/GCC/niltypes.h new file mode 100644 index 000000000..25d849d77 --- /dev/null +++ b/os/nil/ports/AVR/compilers/GCC/niltypes.h @@ -0,0 +1,87 @@ +/*
+ ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/NIL.
+
+ ChibiOS/NIL is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/NIL is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file AVR/compilers/GCC/niltypes.h
+ * @brief AVR port system types.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+typedef uint8_t syssts_t; /**< System status word. */
+typedef uint16_t rtcnt_t; /**< Realtime counter. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef int16_t msg_t; /**< Inter-thread message. */
+typedef uint8_t eventmask_t; /**< Mask of event identifiers. */
+typedef int8_t cnt_t; /**< Generic signed counter. */
+typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then the
+ * realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) \
+ __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore.c b/os/nil/ports/AVR/nilcore.c new file mode 100644 index 000000000..eb762b00b --- /dev/null +++ b/os/nil/ports/AVR/nilcore.c @@ -0,0 +1,138 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file AVR/nilcore.c
+ * @brief AVR port code.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ * @note The function is declared as a weak symbol, it is possible to
+ * redefine it in your application code.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked, weak))
+#endif
+void port_switch(Thread *ntp, Thread *otp) {
+
+ asm volatile ("push r2");
+ asm volatile ("push r3");
+ asm volatile ("push r4");
+ asm volatile ("push r5");
+ asm volatile ("push r6");
+ asm volatile ("push r7");
+ asm volatile ("push r8");
+ asm volatile ("push r9");
+ asm volatile ("push r10");
+ asm volatile ("push r11");
+ asm volatile ("push r12");
+ asm volatile ("push r13");
+ asm volatile ("push r14");
+ asm volatile ("push r15");
+ asm volatile ("push r16");
+ asm volatile ("push r17");
+ asm volatile ("push r28");
+ asm volatile ("push r29");
+
+ asm volatile ("movw r30, r22");
+ asm volatile ("in r0, 0x3d");
+ asm volatile ("std Z+5, r0");
+ asm volatile ("in r0, 0x3e");
+ asm volatile ("std Z+6, r0");
+
+ asm volatile ("movw r30, r24");
+ asm volatile ("ldd r0, Z+5");
+ asm volatile ("out 0x3d, r0");
+ asm volatile ("ldd r0, Z+6");
+ asm volatile ("out 0x3e, r0");
+
+ asm volatile ("pop r29");
+ asm volatile ("pop r28");
+ asm volatile ("pop r17");
+ asm volatile ("pop r16");
+ asm volatile ("pop r15");
+ asm volatile ("pop r14");
+ asm volatile ("pop r13");
+ asm volatile ("pop r12");
+ asm volatile ("pop r11");
+ asm volatile ("pop r10");
+ asm volatile ("pop r9");
+ asm volatile ("pop r8");
+ asm volatile ("pop r7");
+ asm volatile ("pop r6");
+ asm volatile ("pop r5");
+ asm volatile ("pop r4");
+ asm volatile ("pop r3");
+ asm volatile ("pop r2");
+ asm volatile ("ret");
+}
+
+/**
+ * @brief Start a thread by invoking its work function.
+ * @details If the work function returns @p chThdExit() is automatically
+ * invoked.
+ */
+void _port_thread_start(void) {
+
+ chSysUnlock();
+ asm volatile ("movw r24, r4");
+ asm volatile ("movw r30, r2");
+ asm volatile ("icall");
+ chSysHalt(0);
+}
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore.h b/os/nil/ports/AVR/nilcore.h new file mode 100644 index 000000000..6394eeb0b --- /dev/null +++ b/os/nil/ports/AVR/nilcore.h @@ -0,0 +1,438 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file AVR/nilcore.h
+ * @brief AVR port macros and structures.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining the port architecture.
+ */
+#define PORT_ARCHITECTURE_AVR
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "AVR"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "MegaAVR"
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#define PORT_INFO "16 bits code addressing"
+
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 8.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 8
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * @note In this port the default is 32 bytes per thread.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p nilcore_timer.h, if this option is enabled then the file
+ * @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ */
+typedef uint8_t stkalign_t;
+
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ * preemption-capable interrupt handler.
+ */
+struct port_extctx {
+ uint8_t _next;
+ uint8_t r31;
+ uint8_t r30;
+ uint8_t r27;
+ uint8_t r26;
+ uint8_t r25;
+ uint8_t r24;
+ uint8_t r23;
+ uint8_t r22;
+ uint8_t r21;
+ uint8_t r20;
+ uint8_t r19;
+ uint8_t r18;
+ uint8_t sr;
+ uint8_t r1;
+ uint8_t r0;
+ uint16_t pc;
+};
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching.
+ */
+struct port_intctx {
+ uint8_t _next;
+ uint8_t r29;
+ uint8_t r28;
+ uint8_t r17;
+ uint8_t r16;
+ uint8_t r15;
+ uint8_t r14;
+ uint8_t r13;
+ uint8_t r12;
+ uint8_t r11;
+ uint8_t r10;
+ uint8_t r9;
+ uint8_t r8;
+ uint8_t r7;
+ uint8_t r6;
+ uint8_t r5;
+ uint8_t r4;
+ uint8_t r3;
+ uint8_t r2;
+ uint8_t pcl;
+ uint8_t pch;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
+ (tp)->ctxp.sp = (struct port_intctx*)(((uint8_t *)(wend)) - \
+ sizeof(struct port_intctx)); \
+ (tp)->ctxp.sp->r2 = (uint8_t)(pf); \
+ (tp)->ctxp.sp->r3 = (uint8_t)((pf) >> 8); \
+ (tp)->ctxp.sp->r4 = (uint8_t)(arg); \
+ (tp)->ctxp.sp->r5 = (uint8_t)((arg) >> 8); \
+ (tp)->ctxp.sp->pcl = (uint8_t)(_port_thread_start >> 8); \
+ (tp)->ctxp.sp->pch = (uint8_t)_port_thread_start; \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) ((sizeof(struct port_intctx) - 1) + \
+ (sizeof(struct port_extctx) - 1) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ * @note This code tricks the compiler to save all the specified registers
+ * by "touching" them.
+ */
+#define PORT_IRQ_PROLOGUE() { \
+ asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \
+ "r25", "r26", "r27", "r30", "r31"); \
+}
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() chSchRescheduleS()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) ISR(id)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) ISR(id)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return 0;
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retvel false the word specified a disabled interrupts status.
+ * @retvel true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return false;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return false;
+}
+
+/**
+ * @brief Kernel-lock action.
+ */
+static inline void port_lock(void) {
+
+ asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief Kernel-unlock action.
+ */
+static inline void port_unlock(void) {
+
+ asm volatile ("sei" : : : "memory");
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+ asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+ asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+ asm volatile ("sei" : : : "memory");
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+ asm volatile ("sleep" : : : "memory");
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+ return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore_timer.h b/os/nil/ports/AVR/nilcore_timer.h new file mode 100644 index 000000000..0eadcf12a --- /dev/null +++ b/os/nil/ports/AVR/nilcore_timer.h @@ -0,0 +1,129 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file AVR/nilcore_timer.h
+ * @brief System timer header file.
+ *
+ * @addtogroup AVR_TIMER
+ * @{
+ */
+
+#ifndef _NILCORE_TIMER_H_
+#define _NILCORE_TIMER_H_
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+/*#include "st.h"*/
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#error "tickless mode not yet implemented in AVR port"
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#if 0
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+ stStartAlarm(time);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+ stStopAlarm();
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+ stSetAlarm(time);
+}
+
+/**
+ * @brief Returns the system time.
+ *
+ * @return The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+ return stGetCounter();
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+ return stGetAlarm();
+}
+#endif
+
+#endif /* _NILCORE_TIMER_H_ */
+
+/** @} */
diff --git a/os/nil/src/nil.c b/os/nil/src/nil.c new file mode 100644 index 000000000..789256127 --- /dev/null +++ b/os/nil/src/nil.c @@ -0,0 +1,760 @@ +/*
+ Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
+
+ This file is part of Nil RTOS.
+
+ Nil RTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Nil RTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file nil.c
+ * @brief Nil RTOS main source file.
+ *
+ * @defgroup nil
+ * @details Nil RTOS services.
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief System data structures.
+ */
+nil_system_t nil;
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the kernel.
+ * @details Initializes the kernel structures, the current instructions flow
+ * becomes the idle thread upon return. The idle thread must not
+ * invoke any kernel primitive able to change state to not runnable.
+ * @note This function assumes that the @p nil global variable has been
+ * zeroed by the runtime environment. If this is not the case then
+ * make sure to clear it before calling this function.
+ *
+ * @special
+ */
+void chSysInit(void) {
+ thread_t *tp;
+ const thread_config_t *tcp;
+
+ /* Port layer initialization.*/
+ port_init();
+
+ /* Iterates through the list of defined threads.*/
+ tp = &nil.threads[0];
+ tcp = nil_thd_configs;
+ while (tp < &nil.threads[NIL_CFG_NUM_THREADS]) {
+#if NIL_CFG_ENABLE_STACK_CHECK
+ tp->stklim = (stkalign_t *)tcp->wbase;
+#endif
+
+ /* Port dependent thread initialization.*/
+ PORT_SETUP_CONTEXT(tp, tcp->wend, tcp->funcp, tcp->arg);
+
+ /* Initialization hook.*/
+#if defined(NIL_CFG_THREAD_EXT_INIT_HOOK)
+ NIL_CFG_THREAD_EXT_INIT_HOOK(tp);
+#endif
+
+ tp++, tcp++;
+ }
+
+#if NIL_CFG_ENABLE_STACK_CHECK
+ /* The idle thread is a special case because its stack is set up by the
+ runtime environment.*/
+ tp->stklim = THD_IDLE_BASE;
+#endif
+
+ /* Runs the highest priority thread, the current one becomes the null
+ thread.*/
+ nil.current = nil.next = nil.threads;
+ port_switch(nil.current, tp);
+
+ /* Interrupts enabled for the idle thread.*/
+ chSysEnable();
+}
+
+/**
+ * @brief Halts the system.
+ * @details This function is invoked by the operating system when an
+ * unrecoverable error is detected, for example because a programming
+ * error in the application code that triggers an assertion while
+ * in debug mode.
+ * @note Can be invoked from any system state.
+ *
+ * @special
+ */
+void chSysHalt(const char *reason) {
+
+ port_disable();
+
+#if NIL_DBG_ENABLED
+ nil.dbg_panic_msg = reason;
+#else
+ (void)reason;
+#endif
+
+#if defined(NIL_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+ NIL_CFG_SYSTEM_HALT_HOOK(reason);
+#endif
+
+ /* Harmless infinite loop.*/
+ while (true)
+ ;
+}
+
+/**
+ * @brief Time management handler.
+ * @note This handler has to be invoked by a periodic ISR in order to
+ * reschedule the waiting threads.
+ *
+ * @iclass
+ */
+void chSysTimerHandlerI(void) {
+
+#if NIL_CFG_ST_TIMEDELTA == 0
+ thread_t *tp = &nil.threads[0];
+ nil.systime++;
+ do {
+ /* Is the thread in a wait state with timeout?.*/
+ if (tp->timeout > 0) {
+
+ chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
+
+ /* Did the timer reach zero?*/
+ if (--tp->timeout == 0) {
+ /* Timeout on semaphores requires a special handling because the
+ semaphore counter must be incremented.*/
+ if (NIL_THD_IS_WTSEM(tp))
+ tp->u1.semp->cnt++;
+ else if (NIL_THD_IS_SUSP(tp))
+ *tp->u1.trp = NULL;
+ chSchReadyI(tp, MSG_TIMEOUT);
+ }
+ }
+ /* Lock released in order to give a preemption chance on those
+ architectures supporting IRQ preemption.*/
+ chSysUnlockFromISR();
+ tp++;
+ chSysLockFromISR();
+ } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
+#else
+ thread_t *tp = &nil.threads[0];
+ systime_t next = 0;
+
+ chDbgAssert(nil.nexttime == port_timer_get_alarm(), "time mismatch");
+
+ do {
+ /* Is the thread in a wait state with timeout?.*/
+ if (tp->timeout > 0) {
+
+ chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
+ chDbgAssert(tp->timeout >= nil.nexttime - nil.lasttime, "skipped one");
+
+ tp->timeout -= nil.nexttime - nil.lasttime;
+ if (tp->timeout == 0) {
+ /* Timeout on semaphores requires a special handling because the
+ semaphore counter must be incremented.*/
+ if (NIL_THD_IS_WTSEM(tp))
+ tp->u1.semp->cnt++;
+ else if (NIL_THD_IS_SUSP(tp))
+ *tp->u1.trp = NULL;
+ chSchReadyI(tp, MSG_TIMEOUT);
+ }
+ else {
+ if (tp->timeout <= next - 1)
+ next = tp->timeout;
+ }
+ }
+ /* Lock released in order to give a preemption chance on those
+ architectures supporting IRQ preemption.*/
+ chSysUnlockFromISR();
+ tp++;
+ chSysLockFromISR();
+ } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
+ nil.lasttime = nil.nexttime;
+ if (next > 0) {
+ nil.nexttime += next;
+ port_timer_set_alarm(nil.nexttime);
+ }
+ else {
+ /* No tick event needed.*/
+ port_timer_stop_alarm();
+ }
+#endif
+}
+
+/**
+ * @brief Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ * from any context. Because its flexibility it is less efficient
+ * than @p chSysLock() which is preferable when the calling context
+ * is known.
+ * @post The system is in a critical zone.
+ *
+ * @return The previous system status, the encoding of this
+ * status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+syssts_t chSysGetStatusAndLockX(void) {
+
+ syssts_t sts = port_get_irq_status();
+ if (port_irq_enabled(sts)) {
+ if (port_is_isr_context())
+ chSysLockFromISR();
+ else
+ chSysLock();
+ }
+ return sts;
+}
+
+/**
+ * @brief Restores the specified execution status and leaves a critical zone.
+ * @note A call to @p chSchRescheduleS() is automatically performed
+ * if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts the system status to be restored.
+ *
+ * @xclass
+ */
+void chSysRestoreStatusX(syssts_t sts) {
+
+ if (port_irq_enabled(sts)) {
+ if (port_is_isr_context())
+ chSysUnlockFromISR();
+ else {
+ chSchRescheduleS();
+ chSysUnlock();
+ }
+ }
+}
+
+/**
+ * @brief Makes the specified thread ready for execution.
+ *
+ * @param[in] tp pointer to the @p thread_t object
+ * @param[in] msg the wakeup message
+ *
+ * @return The same reference passed as parameter.
+ */
+thread_t *chSchReadyI(thread_t *tp, msg_t msg) {
+
+ chDbgAssert((tp >= nil.threads) &&
+ (tp < &nil.threads[NIL_CFG_NUM_THREADS]),
+ "pointer out of range");
+ chDbgAssert(!NIL_THD_IS_READY(tp), "already ready");
+ chDbgAssert(nil.next <= nil.current, "priority ordering");
+
+ tp->u1.msg = msg;
+ tp->state = NIL_STATE_READY;
+ tp->timeout = 0;
+ if (tp < nil.next)
+ nil.next = tp;
+ return tp;
+}
+
+/**
+ * @brief Reschedules if needed.
+ *
+ * @sclass
+ */
+void chSchRescheduleS(void) {
+
+ if (chSchIsRescRequiredI()) {
+ thread_t *otp = nil.current;
+
+ nil.current = nil.next;
+#if defined(NIL_CFG_IDLE_LEAVE_HOOK)
+ if (otp == &nil.threads[NIL_CFG_NUM_THREADS]) {
+ NIL_CFG_IDLE_LEAVE_HOOK();
+ }
+#endif
+ port_switch(nil.next, otp);
+ }
+}
+
+/**
+ * @brief Puts the current thread to sleep into the specified state with
+ * timeout specification.
+ * @details The thread goes into a sleeping state, if it is not awakened
+ * explicitly within the specified system time then it is forcibly
+ * awakened with a @p NIL_MSG_TMO low level message.
+ *
+ * @param[in] newstate the new thread state or a semaphore pointer
+ * @param[in] timeout the number of ticks before the operation timeouts.
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The wakeup message.
+ * @retval NIL_MSG_TMO if a timeout occurred.
+ *
+ * @sclass
+ */
+msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout) {
+ thread_t *ntp, *otp = nil.current;
+
+ chDbgAssert(otp != &nil.threads[NIL_CFG_NUM_THREADS],
+ "idle cannot sleep");
+
+ /* Storing the wait object for the current thread.*/
+ otp->state = newstate;
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+ if (timeout != TIME_INFINITE) {
+ systime_t abstime;
+
+ /* TIMEDELTA makes sure to have enough time to reprogram the timer
+ before the free-running timer counter reaches the selected timeout.*/
+ if (timeout < NIL_CFG_ST_TIMEDELTA)
+ timeout = NIL_CFG_ST_TIMEDELTA;
+
+ /* Absolute time of the timeout event.*/
+ abstime = chVTGetSystemTimeX() + timeout;
+
+ if (nil.lasttime == nil.nexttime) {
+ /* Special case, first thread asking for a timeout.*/
+ port_timer_start_alarm(abstime);
+ nil.nexttime = abstime;
+ }
+ else {
+ /* Special case, there are already other threads with a timeout
+ activated, evaluating the order.*/
+ if (chVTIsTimeWithinX(abstime, nil.lasttime, nil.nexttime)) {
+ port_timer_set_alarm(abstime);
+ nil.nexttime = abstime;
+ }
+ }
+
+ /* Timeout settings.*/
+ otp->timeout = abstime - nil.lasttime;
+ }
+#else
+
+ /* Timeout settings.*/
+ otp->timeout = timeout;
+#endif
+
+ /* Scanning the whole threads array.*/
+ ntp = nil.threads;
+ while (true) {
+ /* Is this thread ready to execute?*/
+ if (NIL_THD_IS_READY(ntp)) {
+ nil.current = nil.next = ntp;
+#if defined(NIL_CFG_IDLE_ENTER_HOOK)
+ if (ntp == &nil.threads[NIL_CFG_NUM_THREADS]) {
+ NIL_CFG_IDLE_ENTER_HOOK();
+ }
+#endif
+ port_switch(ntp, otp);
+ return nil.current->u1.msg;
+ }
+
+ /* Points to the next thread in lowering priority order.*/
+ ntp++;
+ chDbgAssert(ntp <= &nil.threads[NIL_CFG_NUM_THREADS],
+ "pointer out of range");
+ }
+}
+
+/**
+ * @brief Sends the current thread sleeping and sets a reference variable.
+ * @note This function must reschedule, it can only be called from thread
+ * context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The wake up message.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+
+ chDbgAssert(*trp == NULL, "not NULL");
+
+ *trp = nil.current;
+ nil.current->u1.trp = trp;
+ return chSchGoSleepTimeoutS(NIL_STATE_SUSP, timeout);
+}
+
+/**
+ * @brief Wakes up a thread waiting on a thread reference object.
+ * @note This function must not reschedule because it can be called from
+ * ISR context.
+ *
+ * @param[in] trp a pointer to a thread reference object
+ * @param[in] msg the message code
+ *
+ * @iclass
+ */
+void chThdResumeI(thread_reference_t *trp, msg_t msg) {
+
+ if (*trp != NULL) {
+ thread_reference_t tr = *trp;
+
+ chDbgAssert(NIL_THD_IS_SUSP(tr), "not suspended");
+
+ *trp = NULL;
+ chSchReadyI(tr, msg);
+ }
+}
+
+/**
+ * @brief Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time the delay in system ticks
+ *
+ * @api
+ */
+void chThdSleep(systime_t time) {
+
+ chSysLock();
+
+ chThdSleepS(time);
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Suspends the invoking thread until the system time arrives to the
+ * specified value.
+ *
+ * @param[in] time absolute system time
+ *
+ * @api
+ */
+void chThdSleepUntil(systime_t time) {
+
+ chSysLock();
+
+ chThdSleepUntilS(time);
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval NIL_MSG_OK if the thread has not stopped on the semaphore or the
+ * semaphore has been signaled.
+ * @retval NIL_MSG_RST if the semaphore has been reset using @p chSemReset().
+ * @retval NIL_MSG_TMO if the semaphore has not been signaled or reset within
+ * the specified timeout.
+ *
+ * @api
+ */
+msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout) {
+ msg_t msg;
+
+ chSysLock();
+
+ msg = chSemWaitTimeoutS(sp, timeout);
+
+ chSysUnlock();
+ return msg;
+}
+
+/**
+ * @brief Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return A message specifying how the invoking thread has been
+ * released from the semaphore.
+ * @retval NIL_MSG_OK if the thread has not stopped on the semaphore or the
+ * semaphore has been signaled.
+ * @retval NIL_MSG_RST if the semaphore has been reset using @p chSemReset().
+ * @retval NIL_MSG_TMO if the semaphore has not been signaled or reset within
+ * the specified timeout.
+ *
+ * @sclass
+ */
+msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout) {
+
+ /* Note, the semaphore counter is a volatile variable so accesses are
+ manually optimized.*/
+ cnt_t cnt = sp->cnt;
+ if (cnt <= 0) {
+ if (TIME_IMMEDIATE == timeout)
+ return MSG_TIMEOUT;
+ sp->cnt = cnt - 1;
+ nil.current->u1.semp = sp;
+ return chSchGoSleepTimeoutS(NIL_STATE_WTSEM, timeout);
+ }
+ sp->cnt = cnt - 1;
+ return MSG_OK;
+}
+
+/**
+ * @brief Performs a signal operation on a semaphore.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ *
+ * @api
+ */
+void chSemSignal(semaphore_t *sp) {
+
+ chSysLock();
+
+ chSemSignalI(sp);
+ chSchRescheduleS();
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Performs a signal operation on a semaphore.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ *
+ * @iclass
+ */
+void chSemSignalI(semaphore_t *sp) {
+
+ if (++sp->cnt <= 0) {
+ thread_reference_t tr = nil.threads;
+ while (true) {
+ /* Is this thread waiting on this semaphore?*/
+ if (tr->u1.semp == sp) {
+
+ chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting");
+
+ chSchReadyI(tr, MSG_OK);
+ return;
+ }
+ tr++;
+
+ chDbgAssert(tr < &nil.threads[NIL_CFG_NUM_THREADS],
+ "pointer out of range");
+ }
+ }
+}
+
+/**
+ * @brief Performs a reset operation on the semaphore.
+ * @post After invoking this function all the threads waiting on the
+ * semaphore, if any, are released and the semaphore counter is set
+ * to the specified, non negative, value.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @param[in] n the new value of the semaphore counter. The value must
+ * be non-negative.
+ *
+ * @api
+ */
+void chSemReset(semaphore_t *sp, cnt_t n) {
+
+ chSysLock();
+
+ chSemResetI(sp, n);
+ chSchRescheduleS();
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Performs a reset operation on the semaphore.
+ * @post After invoking this function all the threads waiting on the
+ * semaphore, if any, are released and the semaphore counter is set
+ * to the specified, non negative, value.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp pointer to a @p semaphore_t structure
+ * @param[in] n the new value of the semaphore counter. The value must
+ * be non-negative.
+ *
+ * @iclass
+ */
+void chSemResetI(semaphore_t *sp, cnt_t n) {
+ thread_t *tp;
+ cnt_t cnt;
+
+ cnt = sp->cnt;
+ sp->cnt = n;
+ tp = nil.threads;
+ while (cnt < 0) {
+ /* Is this thread waiting on this semaphore?*/
+ if (tp->u1.semp == sp) {
+
+ chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting");
+
+ cnt++;
+ chSchReadyI(tp, MSG_RESET);
+ }
+ tp++;
+
+ chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS],
+ "pointer out of range");
+ }
+}
+
+/**
+ * @brief Adds a set of event flags directly to the specified @p thread_t.
+ *
+ * @param[in] tp the thread to be signaled
+ * @param[in] mask the event flags set to be ORed
+ *
+ * @api
+ */
+void chEvtSignal(thread_t *tp, eventmask_t mask) {
+
+ chSysLock();
+
+ chEvtSignalI(tp, mask);
+ chSchRescheduleS();
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Adds a set of event flags directly to the specified @p thread_t.
+ * @post This function does not reschedule so a call to a rescheduling
+ * function must be performed before unlocking the kernel. Note that
+ * interrupt handlers always reschedule on exit so an explicit
+ * reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp the thread to be signaled
+ * @param[in] mask the event flags set to be ORed
+ *
+ * @iclass
+ */
+void chEvtSignalI(thread_t *tp, eventmask_t mask) {
+
+ tp->epmask |= mask;
+ if (NIL_THD_IS_WTOREVT(tp) && ((tp->epmask & tp->u1.ewmask) != 0))
+ chSchReadyI(tp, MSG_OK);
+}
+
+/**
+ * @brief Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ * @p mask to become pending then the events are cleared and
+ * returned.
+ *
+ * @param[in] mask mask of the event flags that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mask of the served and cleared events.
+ * @retval 0 if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout) {
+ eventmask_t m;
+
+ chSysLock();
+
+ m = chEvtWaitAnyTimeoutS(mask, timeout);
+
+ chSysUnlock();
+ return m;
+}
+
+/**
+ * @brief Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ * @p mask to become pending then the events are cleared and
+ * returned.
+ *
+ * @param[in] mask mask of the event flags that the function should wait
+ * for, @p ALL_EVENTS enables all the events
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mask of the served and cleared events.
+ * @retval 0 if the operation has timed out.
+ *
+ * @sclass
+ */
+eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout) {
+ thread_t *ctp = nil.current;
+ eventmask_t m;
+
+ if ((m = (ctp->epmask & mask)) == 0) {
+ if (TIME_IMMEDIATE == timeout) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ ctp->u1.ewmask = mask;
+ if (chSchGoSleepTimeoutS(NIL_STATE_WTOREVT, timeout) < MSG_OK) {
+ chSysUnlock();
+ return (eventmask_t)0;
+ }
+ m = ctp->epmask & mask;
+ }
+ ctp->epmask &= ~m;
+ return m;
+}
+
+/** @} */
diff --git a/os/nil/templates/nilcore.c b/os/nil/templates/nilcore.c new file mode 100644 index 000000000..410765079 --- /dev/null +++ b/os/nil/templates/nilcore.c @@ -0,0 +1,55 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/nilcore.c
+ * @brief Port code.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/nil/templates/nilcore.h b/os/nil/templates/nilcore.h new file mode 100644 index 000000000..61df58bc9 --- /dev/null +++ b/os/nil/templates/nilcore.h @@ -0,0 +1,376 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/nilcore.h
+ * @brief Port macros and structures.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining the port architecture.
+ */
+#define PORT_ARCHITECTURE_XXX
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "XXX"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "XXXX-Y"
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#define PORT_INFO "port description"
+
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 16
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p nilcore_timer.h, if this option is enabled then the file
+ * @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ */
+typedef uint64_t stkalign_t;
+
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ * preemption-capable interrupt handler.
+ */
+struct port_extctx {
+
+};
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching.
+ */
+struct port_intctx {
+
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
+ sizeof(struct port_extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return 0;
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retvel false the word specified a disabled interrupts status.
+ * @retvel true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return false;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+ return false;
+}
+
+/**
+ * @brief Kernel-lock action.
+ */
+static inline void port_lock(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action.
+ */
+static inline void port_unlock(void) {
+
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+ return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/templates/niltypes.h b/os/nil/templates/niltypes.h new file mode 100644 index 000000000..c7d535a1a --- /dev/null +++ b/os/nil/templates/niltypes.h @@ -0,0 +1,87 @@ +/*
+ ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/NIL.
+
+ ChibiOS/NIL is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/NIL is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/niltypes.h
+ * @brief Port system types.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE (!FALSE)
+#endif
+/** @} */
+
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then the
+ * realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) \
+ __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
|