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-rw-r--r--testhal/STM32F0xx/IRQ_STORM/.project2
-rw-r--r--testhal/STM32F0xx/IRQ_STORM/chconf.h20
-rw-r--r--testhal/STM32F0xx/IRQ_STORM/main.c26
-rw-r--r--testhal/STM32F0xx/IRQ_STORM/mcuconf.h8
4 files changed, 28 insertions, 28 deletions
diff --git a/testhal/STM32F0xx/IRQ_STORM/.project b/testhal/STM32F0xx/IRQ_STORM/.project
index a3027689a..8c63b9bf4 100644
--- a/testhal/STM32F0xx/IRQ_STORM/.project
+++ b/testhal/STM32F0xx/IRQ_STORM/.project
@@ -27,7 +27,7 @@
<link>
<name>board</name>
<type>2</type>
- <locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
+ <locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
diff --git a/testhal/STM32F0xx/IRQ_STORM/chconf.h b/testhal/STM32F0xx/IRQ_STORM/chconf.h
index 9864162ac..3ab29fcae 100644
--- a/testhal/STM32F0xx/IRQ_STORM/chconf.h
+++ b/testhal/STM32F0xx/IRQ_STORM/chconf.h
@@ -41,7 +41,7 @@
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
-#define CH_CFG_ST_FREQUENCY 1000
+#define CH_CFG_ST_FREQUENCY 10000
#endif
/**
@@ -62,7 +62,7 @@
* this value.
*/
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
-#define CH_CFG_TIMEDELTA 0
+#define CH_CFG_TIMEDELTA 2
#endif
/**
@@ -357,7 +357,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
-#define CH_DBG_STATISTICS TRUE
+#define CH_DBG_STATISTICS FALSE
#endif
/**
@@ -368,7 +368,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
@@ -379,7 +379,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS TRUE
+#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
@@ -391,7 +391,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS TRUE
+#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
@@ -402,7 +402,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE TRUE
+#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
@@ -416,7 +416,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
@@ -428,7 +428,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS TRUE
+#define CH_DBG_FILL_THREADS FALSE
#endif
/**
@@ -441,7 +441,7 @@
* tickless mode.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
-#define CH_DBG_THREADS_PROFILING TRUE
+#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
diff --git a/testhal/STM32F0xx/IRQ_STORM/main.c b/testhal/STM32F0xx/IRQ_STORM/main.c
index 4a11fcad8..a6fd57121 100644
--- a/testhal/STM32F0xx/IRQ_STORM/main.c
+++ b/testhal/STM32F0xx/IRQ_STORM/main.c
@@ -51,7 +51,7 @@ static bool_t saturated;
/*
* Mailboxes and buffers.
*/
-static Mailbox mb[NUM_THREADS];
+static mailbox_t mb[NUM_THREADS];
static msg_t b[NUM_THREADS][MAILBOX_SIZE];
/*
@@ -101,7 +101,7 @@ static msg_t WorkerThread(void *arg) {
/* If this thread is not at the end of a chain re-sending the message,
note this check works because the variable target is unsigned.*/
msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
- if (msg != RDY_OK)
+ if (msg != MSG_OK)
saturated = TRUE;
}
else {
@@ -121,11 +121,11 @@ static void gpt2cb(GPTDriver *gptp) {
msg_t msg;
(void)gptp;
- chSysLockFromIsr();
+ chSysLockFromISR();
msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
- if (msg != RDY_OK)
+ if (msg != MSG_OK)
saturated = TRUE;
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
}
/*
@@ -135,11 +135,11 @@ static void gpt3cb(GPTDriver *gptp) {
msg_t msg;
(void)gptp;
- chSysLockFromIsr();
+ chSysLockFromISR();
msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
- if (msg != RDY_OK)
+ if (msg != MSG_OK)
saturated = TRUE;
- chSysUnlockFromIsr();
+ chSysUnlockFromISR();
}
/*
@@ -217,14 +217,14 @@ int main(void) {
sdStart(&SD1, NULL);
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */
- gptStart(&GPTD2, &gpt2cfg);
+ gptStart(&GPTD1, &gpt2cfg);
gptStart(&GPTD3, &gpt3cfg);
/*
* Initializes the mailboxes and creates the worker threads.
*/
for (i = 0; i < NUM_THREADS; i++) {
- chMBInit(&mb[i], b[i], MAILBOX_SIZE);
+ chMBObjectInit(&mb[i], b[i], MAILBOX_SIZE);
chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
NORMALPRIO - 20, WorkerThread, (void *)i);
}
@@ -287,10 +287,10 @@ int main(void) {
saturated = FALSE;
threshold = 0;
for (interval = 2000; interval >= 20; interval -= interval / 10) {
- gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/
+ gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/
gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
chThdSleepMilliseconds(1000);
- gptStopTimer(&GPTD2);
+ gptStopTimer(&GPTD1);
gptStopTimer(&GPTD3);
if (!saturated)
print(".");
@@ -311,7 +311,7 @@ int main(void) {
if (threshold > worst)
worst = threshold;
}
- gptStopTimer(&GPTD2);
+ gptStopTimer(&GPTD1);
gptStopTimer(&GPTD3);
print("Worst case at ");
diff --git a/testhal/STM32F0xx/IRQ_STORM/mcuconf.h b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h
index daa502b97..cd6d20966 100644
--- a/testhal/STM32F0xx/IRQ_STORM/mcuconf.h
+++ b/testhal/STM32F0xx/IRQ_STORM/mcuconf.h
@@ -77,12 +77,12 @@
/*
* GPT driver system settings.
*/
-#define STM32_GPT_USE_TIM1 FALSE
-#define STM32_GPT_USE_TIM2 TRUE
+#define STM32_GPT_USE_TIM1 TRUE
+#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 TRUE
-#define STM32_GPT_TIM1_IRQ_PRIORITY 2
+#define STM32_GPT_TIM1_IRQ_PRIORITY 1
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
-#define STM32_GPT_TIM3_IRQ_PRIORITY 2
+#define STM32_GPT_TIM3_IRQ_PRIORITY 3
/*
* I2C driver system settings.