From 27ab6ff1f19abb1cb4ee4c13a29e099a2c18209c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Dec 2011 19:44:39 +0000 Subject: Optimization in CM4 FPU support. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3607 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F407-168-GCC-FPU.txt | 26 ++++++++++++------------ os/ports/GCC/ARMCMx/chcore_v7m.c | 36 +++++++++++++++------------------- os/ports/GCC/ARMCMx/chcore_v7m.h | 2 +- 3 files changed, 30 insertions(+), 34 deletions(-) diff --git a/docs/reports/STM32F407-168-GCC-FPU.txt b/docs/reports/STM32F407-168-GCC-FPU.txt index 47dc76c84..0f8e9dc91 100644 --- a/docs/reports/STM32F407-168-GCC-FPU.txt +++ b/docs/reports/STM32F407-168-GCC-FPU.txt @@ -6,7 +6,7 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) *** ChibiOS/RT test suite *** *** Kernel: 2.3.5unstable -*** Compiled: Dec 11 2011 - 17:14:07 +*** Compiled: Dec 12 2011 - 20:40:15 *** Compiler: GCC 4.6.2 *** Architecture: ARMv7-ME *** Core Variant: Cortex-M4F @@ -100,51 +100,51 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 559399 msgs/S, 1118798 ctxswc/S +--- Score : 559422 msgs/S, 1118844 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 476758 msgs/S, 953516 ctxswc/S +--- Score : 476781 msgs/S, 953562 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 476757 msgs/S, 953514 ctxswc/S +--- Score : 476781 msgs/S, 953562 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 1639312 ctxswc/S +--- Score : 1639392 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 371289 threads/S +--- Score : 371307 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 496514 threads/S +--- Score : 496538 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 151014 reschedules/S, 906084 ctxswc/S +--- Score : 151022 reschedules/S, 906132 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 1018620 ctxswc/S +--- Score : 1018660 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 1766592 bytes/S +--- Score : 1766676 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 1997950 timers/S +--- Score : 1998046 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 2601996 wait+signal/S +--- Score : 2602084 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 1766592 lock+unlock/S +--- Score : 1766664 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 936823755..12932a5ce 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -98,21 +98,20 @@ CH_IRQ_HANDLER(SysTickVector) { * @note The PendSV vector is only used in advanced kernel mode. */ void SVCallVector(void) { - uint32_t *psp; + struct extctx *ctxp; /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory"); + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); /* Discarding the current exception context and positioning the stack to point to the real one.*/ - psp = (uint32_t *)((struct extctx *)psp + 1); + ctxp++; #if CORTEX_USE_FPU - /* Restoring the special registers SCB_FPCCR and FPCAR.*/ - SCB_FPCAR = *psp++; - SCB_FPCCR = *psp++; + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; #endif - asm volatile ("msr PSP, %0" : : "r" (psp) : "memory"); + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); port_unlock_from_isr(); } #endif /* !CORTEX_SIMPLIFIED_PRIORITY */ @@ -125,21 +124,20 @@ void SVCallVector(void) { * @note The PendSV vector is only used in compact kernel mode. */ void PendSVVector(void) { - uint32_t *psp; + struct extctx *ctxp; /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory"); + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); /* Discarding the current exception context and positioning the stack to point to the real one.*/ - psp = (uint32_t *)((struct extctx *)psp + 1); + ctxp++; #if CORTEX_USE_FPU - /* Restoring the special registers SCB_FPCCR and FPCAR.*/ - SCB_FPCAR = *psp++; - SCB_FPCCR = *psp++; + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; #endif - asm volatile ("msr PSP, %0" : : "r" (psp) : "memory"); + asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); } #endif /* CORTEX_SIMPLIFIED_PRIORITY */ @@ -186,19 +184,17 @@ void _port_irq_epilogue(void) { port_lock_from_isr(); if ((SCB_ICSR & ICSR_RETTOBASE)) { - uint32_t *psp; struct extctx *ctxp; /* Current PSP value.*/ - asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory"); + asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); #if CORTEX_USE_FPU { uint32_t fpccr; - /* Saving the special registers SCB_FPCCR and FPCAR as extra context.*/ - *--psp = fpccr = SCB_FPCCR; - *--psp = SCB_FPCAR; + /* Saving the special register SCB_FPCCR.*/ + ctxp->fpccr = (regarm_t)(fpccr = SCB_FPCCR); /* Now the FPCCR is modified in order to not restore the FPU status from the artificial return context.*/ @@ -208,7 +204,7 @@ void _port_irq_epilogue(void) { /* Adding an artificial exception return context, there is no need to populate it fully.*/ - ctxp = ((struct extctx *)psp) - 1; + ctxp--; asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); ctxp->pc = _port_switch_from_isr; ctxp->xpsr = (regarm_t)0x01000000; diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 8dd42f909..46979920f 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -184,7 +184,7 @@ struct extctx { regarm_t s14; regarm_t s15; regarm_t fpscr; - regarm_t reserved; + regarm_t fpccr; #endif /* CORTEX_USE_FPU */ }; -- cgit v1.2.3