From 5404d1ee8da67275b467d0ec4ce4ca9da8b98f27 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 29 Nov 2015 08:20:40 +0000 Subject: IRQ Storm for STM32F7. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8548 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32/STM32F7xx/IRQ_STORM/Makefile | 10 +-- testhal/STM32/STM32F7xx/IRQ_STORM/chconf.h | 2 + testhal/STM32/STM32F7xx/IRQ_STORM/main.c | 9 ++- testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h | 115 +++++++++++++++++++--------- 4 files changed, 89 insertions(+), 47 deletions(-) diff --git a/testhal/STM32/STM32F7xx/IRQ_STORM/Makefile b/testhal/STM32/STM32F7xx/IRQ_STORM/Makefile index 6126b5621..c234aa70a 100644 --- a/testhal/STM32/STM32F7xx/IRQ_STORM/Makefile +++ b/testhal/STM32/STM32F7xx/IRQ_STORM/Makefile @@ -88,20 +88,20 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. # Startup files. -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -#include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld +LDSCRIPT= $(STARTUPLD)/STM32F746xG.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/testhal/STM32/STM32F7xx/IRQ_STORM/chconf.h b/testhal/STM32/STM32F7xx/IRQ_STORM/chconf.h index 7d9906294..fe1c8d375 100644 --- a/testhal/STM32/STM32F7xx/IRQ_STORM/chconf.h +++ b/testhal/STM32/STM32F7xx/IRQ_STORM/chconf.h @@ -494,6 +494,8 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#define CORTEX_VTOR_INIT 0x00200000U + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/testhal/STM32/STM32F7xx/IRQ_STORM/main.c b/testhal/STM32/STM32F7xx/IRQ_STORM/main.c index a676086db..a8c456238 100644 --- a/testhal/STM32/STM32F7xx/IRQ_STORM/main.c +++ b/testhal/STM32/STM32F7xx/IRQ_STORM/main.c @@ -43,9 +43,9 @@ static const GPTConfig gpt3cfg = { * IRQ Storm configuration. */ static const irq_storm_config_t irq_storm_config = { - (BaseSequentialStream *)&SD2, - GPIOD, - GPIOD_LED5, + (BaseSequentialStream *)&SD1, + GPIOI, + GPIOI_ARD_D13, &GPTD4, &GPTD3, &gpt4cfg, @@ -69,9 +69,10 @@ int main(void) { chSysInit(); /* Prepares the Serial driver 2.*/ - sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL); /* Running the test.*/ irq_storm_execute(&irq_storm_config); diff --git a/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h index 05fc44366..15db71d2b 100644 --- a/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h @@ -31,38 +31,64 @@ * 0...3 Lowest...Highest. */ -#define STM32F4xx_MCUCONF +#define STM32F7xx_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE #define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 #define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 +#define STM32_PLLQ_VALUE 9 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S #define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 5 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE /* * ADC driver system settings. @@ -170,21 +196,6 @@ #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - /* * ICU driver system settings. */ @@ -236,29 +247,34 @@ /* * SDC driver system settings. */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 250 -#define STM32_SDC_READ_TIMEOUT_MS 25 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 /* * SERIAL driver system settings. */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 #define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 /* * SPI driver system settings. @@ -266,18 +282,33 @@ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -295,6 +326,8 @@ #define STM32_UART_USE_UART4 FALSE #define STM32_UART_USE_UART5 FALSE #define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) @@ -307,6 +340,10 @@ #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 @@ -319,6 +356,8 @@ #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* -- cgit v1.2.3