From c0065617e0ad6d47e3e8446dbeec017fd0255528 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Thu, 23 Jun 2016 09:03:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9649 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../Infineon/XMC1100/XMC1000_RomFunctionTable.h | 164 + os/common/ext/CMSIS/Infineon/XMC1100/XMC1100.h | 4230 ++++++++++++++++++++ .../ext/CMSIS/Infineon/XMC1100/system_XMC1100.h | 84 + .../startup/ARMCMx/devices/XMC1100/cmparams.h | 74 + 4 files changed, 4552 insertions(+) create mode 100644 os/common/ext/CMSIS/Infineon/XMC1100/XMC1000_RomFunctionTable.h create mode 100644 os/common/ext/CMSIS/Infineon/XMC1100/XMC1100.h create mode 100644 os/common/ext/CMSIS/Infineon/XMC1100/system_XMC1100.h create mode 100644 os/common/startup/ARMCMx/devices/XMC1100/cmparams.h diff --git a/os/common/ext/CMSIS/Infineon/XMC1100/XMC1000_RomFunctionTable.h b/os/common/ext/CMSIS/Infineon/XMC1100/XMC1000_RomFunctionTable.h new file mode 100644 index 000000000..1ffc56ba2 --- /dev/null +++ b/os/common/ext/CMSIS/Infineon/XMC1100/XMC1000_RomFunctionTable.h @@ -0,0 +1,164 @@ +/*************************************************************************** */ +/** +* @file XMC1000_RomFunctionTable.h +* Infineon XMC Device Series +* @version V1.0 +* @date 08 April 2013 +* +Copyright (C) 2013 Infineon Technologies AG. All rights reserved. +* +* +* @par +* Infineon Technologies AG (Infineon) is supplying this software for use with +* Infineon's microcontrollers. This file can be freely distributed +* within development tools that are supporting such microcontrollers. +* +* @par +* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +* +******************************************************************************/ + +/***************************************************************************** +************************* Version history ************************************ +V1.0, 08 Jan 2013, GD, First version with XMC1000 devices +*****************************************************************************/ + +#ifndef ROM_FUNCTION_TABLE_H +#define ROM_FUNCTION_TABLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* *************************************************************************** +******************************* Constants ******************************* +*************************************************************************** */ +/* Start address of the ROM function table */ +#define ROM_FUNCTION_TABLE_START (0x00000100U) + +/* Pointer to Erase Flash Page routine */ +#define _NvmErase (ROM_FUNCTION_TABLE_START + 0x00U) + +/* Pointer to Erase, Program & Verify Flash Page routine */ +#define _NvmProgVerify (ROM_FUNCTION_TABLE_START + 0x04U) + +/* Pointer to Request BMI installation routine */ +#define _BmiInstallationReq (ROM_FUNCTION_TABLE_START + 0x08U) + + +/* *************************************************************************** +******************************** Enumerations ******************************** +*************************************************************************** */ +typedef enum TagNVMStatus +{ + +/* The function succeeded */ + NVM_PASS = (int32_t)0x00010000U, + +/* Generic error code */ + NVM_E_FAIL = (int32_t)0x80010001U, + +/* Source data not in RAM */ + NVM_E_SRC_AREA_EXCCEED = (int32_t)0x80010003U, + +/* Source data is not 4 byte aligned */ + NVM_E_SRC_ALIGNMENT = (int32_t)0x80010004U, + +/* NVM module cannot be physically accessed */ + NVM_E_NVM_FAIL = (int32_t)0x80010005U, + +/* Verification of written page not successful */ + NVM_E_VERIFY = (int32_t)0x80010006U, + +/* Destination data is not (completely) located in NVM */ + NVM_E_DST_AREA_EXCEED = (int32_t)0x80010009U, + +/* Destination data is not properly aligned */ + NVM_E_DST_ALIGNMENT = (int32_t)0x80010010U, + +} NVM_STATUS; + + +/* *************************************************************************** +*********************************** Macros *********************************** +*************************************************************************** */ + +/* *************************************************************************** +Description: Erase granularity = 1 Page of 16 blocks of 16 Bytes + = Equivalent to 256 Bytes using this routine. + +Input parameters: +– Logical address of the Flash Page to be erased which must be page aligned +and in NVM address range + +Return status: +– OK (NVM_PASS) +– Invalid address (NVM_E_DST_ALIGNMENT or NVM_E_DST_AREA_EXCEED) +– Operation failed (Error during low level NVM programming driver): + NVM_E_FAIL + NVM_E_VERIFY + NVM_E_NVM_FAIL + +Prototype: + NVM_STATUS XMC1000_NvmErasePage(uint32_t *pageAddr) +*************************************************************************** */ +#define XMC1000_NvmErasePage (*((NVM_STATUS (**) (uint32_t * )) \ + _NvmErase)) + +/* *************************************************************************** +Description: This procedure performs erase (skipped if not necessary), program +and verify of selected Flash page. + +Input parameter: +– Logical address of the target Flash Page, must be page aligned and in NVM +address range + +– Address in SRAM where the data starts, must be 4-byte aligned + +Return status: +– OK (NVM_PASS) +– Invalid addresses + NVM_E_DST_ALIGNMENT + NVM_E_SRC_ALIGNMENT + NVM_E_DST_AREA_EXCEED + NVM_E_SRC_AREA_EXCCEED +– Operation failed (Error during low level NVM programming driver): + NVM_E_FAIL + NVM_E_VERIFY + NVM_E_NVM_FAIL + +Prototype: + NVM_STATUS XMC1000_NvmProgVerify(const uint32_t *srcAddr, uint32_t *dstAddr) +*************************************************************************** */ +#define XMC1000_NvmProgVerify (*((NVM_STATUS (**) (const uint32_t * ,\ + uint32_t * ))\ + _NvmProgVerify)) + + +/* *************************************************************************** +Description: This procedure initiates installation of a new BMI value. In +particular, it can be used as well as to restore the state upon delivery for a +device already in User Productive mode. + +Input parameter: +– BMI value to be installed + +Return status: +– wrong input BMI value (0x01) - only upon error, if OK the procedure triggers +a reset respectively does not return to calling routine ! + +Prototype: + unsigned long XMC1000_BmiInstallationReq(unsigned short requestedBmiValue) +**************************************************************************** */ +#define XMC1000_BmiInstallationReq (*((uint32_t (**) (uint16_t)) \ + _BmiInstallationReq)) + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_FUNCTION_TABLE_H */ diff --git a/os/common/ext/CMSIS/Infineon/XMC1100/XMC1100.h b/os/common/ext/CMSIS/Infineon/XMC1100/XMC1100.h new file mode 100644 index 000000000..f19474d9b --- /dev/null +++ b/os/common/ext/CMSIS/Infineon/XMC1100/XMC1100.h @@ -0,0 +1,4230 @@ +/****************************************************************************/ +/** +Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. +* +* +* @par +* Infineon Technologies AG (Infineon) is supplying this software for use with +* Infineon's microcontrollers. This file can be freely distributed within +* development tools that are supporting such microcontrollers. +* +* @par +* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, +* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +* +******************************************************************************/ + + +/****************************************************************************************************//** + * @file XMC1100.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * XMC1100 from Infineon. + * + * @version V1.2.2 (Reference Manual v1.2) + * @date 23. January 2015 + * + * @note Generated with SVDConv V2.86c + * from CMSIS SVD File 'XMC1100_Processed_SVD.xml' Version 1.2.2 (Reference Manual v1.2), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC1100 + * @{ + */ + +#ifndef XMC1100_H +#define XMC1100_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC1100 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */ + SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */ + SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */ + ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */ + ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */ + ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */ + ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */ + + USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */ + USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */ + USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */ + USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */ + USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */ + USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */ + + VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */ + VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */ + + CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */ + CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */ + CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */ + CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */ + +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_XMC1100.h" /*!< XMC1100 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ + +extern uint32_t SystemCoreClock; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the system + * + */ +void SystemInit(void); + +/** + * @brief Initialize CPU settings + * + */ +void SystemCoreSetup(void); + +/** + * @brief Initialize clock + * + */ +void SystemCoreClockSetup(void); + +/** + * @brief Update SystemCoreClock variable + * + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/os/common/startup/ARMCMx/devices/XMC1100/cmparams.h b/os/common/startup/ARMCMx/devices/XMC1100/cmparams.h new file mode 100644 index 000000000..7cba8bce3 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/XMC1100/cmparams.h @@ -0,0 +1,74 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file XMC1100/cmparams.h + * @brief ARM Cortex-M0 parameters for the XMC1100. + * + * @defgroup ARMCMx_XMC1100 XMC1100 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * XMC1100 platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "XMC1100.h" + +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ -- cgit v1.2.3