From 541fc3bcfaac3cb0dc22a649bc7d377c5ac72f73 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 27 Dec 2017 10:39:47 +0000 Subject: Better default assignment of DMA channels. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11201 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h | 88 +++++++++++++-------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h') diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index 4a1b10dcf..d26cec4bc 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -140,7 +140,7 @@ #define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK #define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK #define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK -#define STM32_LPTIM1SEL STM32_LPTIM1_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 #define STM32_CECSEL STM32_CECSEL_LSE_CK #define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK #define STM32_I2C123SEL STM32_I2C123SEL_PCLK1 @@ -181,9 +181,9 @@ #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_CHANNEL 0 +#define STM32_ADC_ADC2_DMA_CHANNEL 1 +#define STM32_ADC_ADC3_DMA_CHANNEL 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC2_DMA_PRIORITY 2 #define STM32_ADC_ADC3_DMA_PRIORITY 2 @@ -212,8 +212,8 @@ #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 3 +#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 4 /* * GPT driver system settings. @@ -251,14 +251,14 @@ #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C4 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6 +#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7 +#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8 +#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9 +#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8 +#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9 +#define STM32_I2C_I2C4_RX_BDMA_CHANNEL 0 +#define STM32_I2C_I2C4_TX_BDMA_CHANNEL 1 #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 @@ -325,7 +325,7 @@ #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 #define STM32_SDC_SDMMC_READ_TIMEOUT 1000 #define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_CHANNEL 5 #define STM32_SDC_SDMMC1_DMA_PRIORITY 3 #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 @@ -352,24 +352,24 @@ /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI1 TRUE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_RX_DMA_CHANNEL 10 +#define STM32_SPI_SPI1_TX_DMA_CHANNEL 11 +#define STM32_SPI_SPI2_RX_DMA_CHANNEL 12 +#define STM32_SPI_SPI2_TX_DMA_CHANNEL 13 +#define STM32_SPI_SPI3_RX_DMA_CHANNEL 10 +#define STM32_SPI_SPI3_TX_DMA_CHANNEL 11 +#define STM32_SPI_SPI4_RX_DMA_CHANNEL 12 +#define STM32_SPI_SPI4_TX_DMA_CHANNEL 13 +#define STM32_SPI_SPI5_RX_DMA_CHANNEL 12 +#define STM32_SPI_SPI5_TX_DMA_CHANNEL 13 +#define STM32_SPI_SPI6_RX_BDMA_CHANNEL 2 +#define STM32_SPI_SPI6_TX_BDMA_CHANNEL 3 #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -401,22 +401,22 @@ #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_UART7 FALSE #define STM32_UART_USE_UART8 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_RX_DMA_CHANNEL 14 +#define STM32_UART_USART1_TX_DMA_CHANNEL 15 +#define STM32_UART_USART2_RX_DMA_CHANNEL 8 +#define STM32_UART_USART2_TX_DMA_CHANNEL 9 +#define STM32_UART_USART3_RX_DMA_CHANNEL 12 +#define STM32_UART_USART3_TX_DMA_CHANNEL 13 +#define STM32_UART_UART4_RX_DMA_CHANNEL 14 +#define STM32_UART_UART4_TX_DMA_CHANNEL 15 +#define STM32_UART_UART5_RX_DMA_CHANNEL 8 +#define STM32_UART_UART5_TX_DMA_CHANNEL 9 +#define STM32_UART_USART6_RX_DMA_CHANNEL 12 +#define STM32_UART_USART6_TX_DMA_CHANNEL 13 +#define STM32_UART_UART7_RX_DMA_CHANNEL 8 +#define STM32_UART_UART7_TX_DMA_CHANNEL 9 +#define STM32_UART_UART8_RX_DMA_CHANNEL 12 +#define STM32_UART_UART8_TX_DMA_CHANNEL 13 #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 -- cgit v1.2.3