From 3bbaa571d416b04e88c3ca7fea276d750eee9c96 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Sat, 4 Jun 2016 16:01:07 +0000 Subject: Improved PLLSAI for STM32F446xx and STM32F469xx/79xx. Updated mcuconf.h for STM32F446xx and STM32F469xx/79xx. Added Clock 48 selector. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9575 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h | 22 +++++++++++----------- demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h | 22 +++++++++++----------- demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h | 14 +++++++------- 3 files changed, 29 insertions(+), 29 deletions(-) (limited to 'demos/STM32') diff --git a/demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h b/demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h index 2a12bcb50..2da67dd47 100644 --- a/demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h +++ b/demos/STM32/RT-STM32F446RE-NUCLEO64/mcuconf.h @@ -45,9 +45,18 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 +#define STM32_PLLN_VALUE 360 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SM_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIM_VALUE 4 +#define STM32_PLLSAIP_VALUE 8 +#define STM32_PLLSAIQ_VALUE 4 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 @@ -58,18 +67,9 @@ #define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S #define STM32_MCO2PRE STM32_MCO2PRE_DIV1 #define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 4 -#define STM32_PLLSAIQ_VALUE 4 #define STM32_SAI1SEL STM32_SAI2SEL_PLLR #define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE diff --git a/demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h index 9d0fd8d6b..93d344daa 100644 --- a/demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32F446ZE-NUCLEO144/mcuconf.h @@ -45,9 +45,18 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 +#define STM32_PLLN_VALUE 360 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SM_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIM_VALUE 4 +#define STM32_PLLSAIP_VALUE 8 +#define STM32_PLLSAIQ_VALUE 4 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 @@ -58,18 +67,9 @@ #define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S #define STM32_MCO2PRE STM32_MCO2PRE_DIV1 #define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 4 -#define STM32_PLLSAIQ_VALUE 4 #define STM32_SAI1SEL STM32_SAI2SEL_PLLR #define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h index 797541457..c687a343a 100644 --- a/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h @@ -48,6 +48,13 @@ #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 @@ -58,13 +65,6 @@ #define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S #define STM32_MCO2PRE STM32_MCO2PRE_DIV1 #define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIR_VALUE 4 -#define STM32_PLLSAIP_VALUE 4 -#define STM32_PLLSAIQ_VALUE 4 #define STM32_SAI1SEL STM32_SAI2SEL_PLLR #define STM32_SAI2SEL STM32_SAI2SEL_PLLR #define STM32_CK48MSEL STM32_CK48MSEL_PLL -- cgit v1.2.3