From abd118ef2d74d46717a95f0c3309237fc3c1f170 Mon Sep 17 00:00:00 2001 From: roccomarco Date: Sat, 1 Jul 2017 11:39:03 +0000 Subject: Updated CMSIS headers for STM32 MCUs git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10267 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h | 7715 ++++++++++++++++-------- 1 file changed, 5340 insertions(+), 2375 deletions(-) (limited to 'os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h') diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h b/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h index 5e4faae87..cc3af34ef 100644 --- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h +++ b/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f071xb.h * @author MCD Application Team - * @version V2.2.3 - * @date 29-January-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -708,76 +706,140 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 family) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */ -#define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ /* Legacy defines */ #define ADC_ISR_AWD (ADC_ISR_AWD1) #define ADC_ISR_EOSEQ (ADC_ISR_EOS) /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */ -#define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ /* Legacy defines */ #define ADC_IER_AWDIE (ADC_IER_AWD1IE) #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< ADC group regular sequencer scan direction */ - -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */ - -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */ - -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< ADC group regular external trigger source */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */ - -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */ - -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC low power auto wait */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC low power auto power off */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR1_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ - -#define ADC_CFGR1_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR1_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ -#define ADC_CFGR1_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ -#define ADC_CFGR1_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ -#define ADC_CFGR1_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ -#define ADC_CFGR1_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /* Legacy defines */ #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) @@ -791,19 +853,23 @@ typedef struct #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< bit 1 */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< bit 0 */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ /* Legacy defines */ #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< ADC group of channels sampling time 2 */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ @@ -812,33 +878,37 @@ typedef struct #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */ -#define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */ -#define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */ -#define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */ -#define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */ -#define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */ -#define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */ -#define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */ -#define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */ -#define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */ - -#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */ -#define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */ -#define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */ -#define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */ -#define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */ -#define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */ -#define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */ -#define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */ -#define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */ -#define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */ -#define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */ -#define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /* Legacy defines */ #define ADC_TR_HT (ADC_TR1_HT1) @@ -847,52 +917,100 @@ typedef struct #define ADC_LTR_LT (ADC_TR1_LT1) /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ -#define ADC_DR_DATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_DR_DATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_DR_DATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ -#define ADC_DR_DATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ -#define ADC_DR_DATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ -#define ADC_DR_DATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ -#define ADC_DR_DATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ -#define ADC_DR_DATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ -#define ADC_DR_DATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ -#define ADC_DR_DATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ -#define ADC_DR_DATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ -#define ADC_DR_DATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ -#define ADC_DR_DATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ -#define ADC_DR_DATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ -#define ADC_DR_DATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ -#define ADC_DR_DATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /************************* ADC Common registers *****************************/ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ /* */ @@ -901,56 +1019,136 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CEC_CR register *********************/ -#define CEC_CR_CECEN ((uint32_t)0x00000001U) /*!< CEC Enable */ -#define CEC_CR_TXSOM ((uint32_t)0x00000002U) /*!< CEC Tx Start Of Message */ -#define CEC_CR_TXEOM ((uint32_t)0x00000004U) /*!< CEC Tx End Of Message */ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ /******************* Bit definition for CEC_CFGR register *******************/ -#define CEC_CFGR_SFT ((uint32_t)0x00000007U) /*!< CEC Signal Free Time */ -#define CEC_CFGR_RXTOL ((uint32_t)0x00000008U) /*!< CEC Tolerance */ -#define CEC_CFGR_BRESTP ((uint32_t)0x00000010U) /*!< CEC Rx Stop */ -#define CEC_CFGR_BREGEN ((uint32_t)0x00000020U) /*!< CEC Bit Rising Error generation */ -#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040U) /*!< CEC Long Bit Period Error gener. */ -#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080U) /*!< CEC Broadcast No Error generation */ -#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100U) /*!< CEC Signal Free Time optional */ -#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000U) /*!< CEC Own Address */ -#define CEC_CFGR_LSTN ((uint32_t)0x80000000U) /*!< CEC Listen mode */ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ /******************* Bit definition for CEC_TXDR register *******************/ -#define CEC_TXDR_TXD ((uint32_t)0x000000FFU) /*!< CEC Tx Data */ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD ((uint32_t)0x000000FFU) /*!< CEC Rx Data */ +#define CEC_TXDR_RXD_Pos (0U) +#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ /******************* Bit definition for CEC_ISR register ********************/ -#define CEC_ISR_RXBR ((uint32_t)0x00000001U) /*!< CEC Rx-Byte Received */ -#define CEC_ISR_RXEND ((uint32_t)0x00000002U) /*!< CEC End Of Reception */ -#define CEC_ISR_RXOVR ((uint32_t)0x00000004U) /*!< CEC Rx-Overrun */ -#define CEC_ISR_BRE ((uint32_t)0x00000008U) /*!< CEC Rx Bit Rising Error */ -#define CEC_ISR_SBPE ((uint32_t)0x00000010U) /*!< CEC Rx Short Bit period Error */ -#define CEC_ISR_LBPE ((uint32_t)0x00000020U) /*!< CEC Rx Long Bit period Error */ -#define CEC_ISR_RXACKE ((uint32_t)0x00000040U) /*!< CEC Rx Missing Acknowledge */ -#define CEC_ISR_ARBLST ((uint32_t)0x00000080U) /*!< CEC Arbitration Lost */ -#define CEC_ISR_TXBR ((uint32_t)0x00000100U) /*!< CEC Tx Byte Request */ -#define CEC_ISR_TXEND ((uint32_t)0x00000200U) /*!< CEC End of Transmission */ -#define CEC_ISR_TXUDR ((uint32_t)0x00000400U) /*!< CEC Tx-Buffer Underrun */ -#define CEC_ISR_TXERR ((uint32_t)0x00000800U) /*!< CEC Tx-Error */ -#define CEC_ISR_TXACKE ((uint32_t)0x00001000U) /*!< CEC Tx Missing Acknowledge */ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ /******************* Bit definition for CEC_IER register ********************/ -#define CEC_IER_RXBRIE ((uint32_t)0x00000001U) /*!< CEC Rx-Byte Received IT Enable */ -#define CEC_IER_RXENDIE ((uint32_t)0x00000002U) /*!< CEC End Of Reception IT Enable */ -#define CEC_IER_RXOVRIE ((uint32_t)0x00000004U) /*!< CEC Rx-Overrun IT Enable */ -#define CEC_IER_BREIE ((uint32_t)0x00000008U) /*!< CEC Rx Bit Rising Error IT Enable */ -#define CEC_IER_SBPEIE ((uint32_t)0x00000010U) /*!< CEC Rx Short Bit period Error IT Enable*/ -#define CEC_IER_LBPEIE ((uint32_t)0x00000020U) /*!< CEC Rx Long Bit period Error IT Enable */ -#define CEC_IER_RXACKEIE ((uint32_t)0x00000040U) /*!< CEC Rx Missing Acknowledge IT Enable */ -#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080U) /*!< CEC Arbitration Lost IT Enable */ -#define CEC_IER_TXBRIE ((uint32_t)0x00000100U) /*!< CEC Tx Byte Request IT Enable */ -#define CEC_IER_TXENDIE ((uint32_t)0x00000200U) /*!< CEC End of Transmission IT Enable */ -#define CEC_IER_TXUDRIE ((uint32_t)0x00000400U) /*!< CEC Tx-Buffer Underrun IT Enable */ -#define CEC_IER_TXERRIE ((uint32_t)0x00000800U) /*!< CEC Tx-Error IT Enable */ -#define CEC_IER_TXACKEIE ((uint32_t)0x00001000U) /*!< CEC Tx Missing Acknowledge IT Enable */ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ /******************************************************************************/ /* */ @@ -959,91 +1157,165 @@ typedef struct /******************************************************************************/ /*********************** Bit definition for COMP_CSR register ***************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002U) /*!< COMP1 SW1 switch control */ -#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000CU) /*!< COMP1 power mode */ -#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004U) /*!< COMP1 power mode bit 0 */ -#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008U) /*!< COMP1 power mode bit 1 */ -#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040U) /*!< COMP1 inverting input select bit 2 */ -#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700U) /*!< COMP1 output select */ -#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100U) /*!< COMP1 output select bit 0 */ -#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200U) /*!< COMP1 output select bit 1 */ -#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400U) /*!< COMP1 output select bit 2 */ -#define COMP_CSR_COMP1POL ((uint32_t)0x00000800U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000U) /*!< COMP1 hysteresis */ -#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000U) /*!< COMP1 hysteresis bit 0 */ -#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000U) /*!< COMP1 hysteresis bit 1 */ -#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1SW1_Pos (1U) +#define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */ +#define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */ +#define COMP_CSR_COMP1MODE_Pos (2U) +#define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */ +#define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP1INSEL_Pos (4U) +#define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP1OUTSEL_Pos (8U) +#define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */ +#define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP1POL_Pos (11U) +#define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */ +#define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1HYST_Pos (12U) +#define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */ +#define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */ +#define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP1OUT_Pos (14U) +#define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (15U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00010000U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000U) /*!< COMP2 power mode bit 0 */ -#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000U) /*!< COMP2 power mode bit 1 */ -#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_WNDWEN ((uint32_t)0x00800000U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ -#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000U) /*!< COMP2 output select */ -#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000U) /*!< COMP2 output select bit 0 */ -#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000U) /*!< COMP2 output select bit 1 */ -#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000U) /*!< COMP2 output select bit 2 */ -#define COMP_CSR_COMP2POL ((uint32_t)0x08000000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000U) /*!< COMP2 hysteresis */ -#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000U) /*!< COMP2 hysteresis bit 0 */ -#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000U) /*!< COMP2 hysteresis bit 1 */ -#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (16U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2MODE_Pos (18U) +#define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_COMP2INSEL_Pos (20U) +#define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */ +#define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_WNDWEN_Pos (23U) +#define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_COMP2OUTSEL_Pos (24U) +#define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */ +#define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ +#define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_COMP2POL_Pos (27U) +#define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2HYST_Pos (28U) +#define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */ +#define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */ +#define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */ +#define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */ +#define COMP_CSR_COMP2OUT_Pos (30U) +#define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700U) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100U) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200U) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400U) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000U) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000U) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000U) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE_Pos (2U) +#define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMPxINSEL_Pos (4U) +#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMPxOUTSEL_Pos (8U) +#define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMPxPOL_Pos (11U) +#define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */ +#define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST_Pos (12U) +#define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */ +#define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMPxOUT_Pos (14U) +#define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (15U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ + +/* +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +*/ + +/* Support of Programmable Polynomial size and value feature */ +#define CRC_PROG_POLYNOMIAL_SUPPORT + /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< REV_IN Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< REV_IN Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -1051,46 +1323,98 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */ -#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */ -#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/ -#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */ -#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */ -#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */ -#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */ - -#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */ -#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */ - -#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */ - -#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */ -#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */ -#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */ -#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */ -#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */ -#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */ -#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */ -#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */ -#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */ -#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ /******************************************************************************/ /* */ @@ -1099,98 +1423,166 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 family) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun Interrupt enable */ - -#define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!< DAC channel2 DMA enabled */ -#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA Underrun Interrupt enable */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ + +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ + +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ + +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2_Pos (17U) +#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ +#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2_Pos (18U) +#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2_Pos (19U) +#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ + +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ +#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ + +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ + +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA Underrun Interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!< DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2_Pos (1U) +#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!< DAC channel2 12-bit Right aligned data */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel2 12-bit Left aligned data */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!< DAC channel2 8-bit Right aligned data */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!< DAC channel2 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!< DAC channel2 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!< DAC channel2 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ /******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!< DAC channel2 data output */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ /******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ /******************************************************************************/ /* */ @@ -1199,46 +1591,80 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100U) /*!< TIM14 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U) /*!< TIM15 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U) /*!< TIM16 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000U) /*!< TIM17 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -1246,97 +1672,239 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ - -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ - -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ - -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ - -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************************************************************************/ /* */ @@ -1344,34 +1912,90 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_MR20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_MR21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_MR22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_MR23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_MR25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_MR26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_MR27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */ -#define EXTI_IMR_MR31 ((uint32_t)0x80000000U) /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR20_Pos (20U) +#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_MR21_Pos (21U) +#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_MR22_Pos (22U) +#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_MR23_Pos (23U) +#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_MR25_Pos (25U) +#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_MR26_Pos (26U) +#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_MR27_Pos (27U) +#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR_MR31_Pos (31U) +#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -1403,35 +2027,96 @@ typedef struct #define EXTI_IMR_IM27 EXTI_IMR_MR27 #define EXTI_IMR_IM31 EXTI_IMR_MR31 +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x8EFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x8EFFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ + + /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_MR20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_MR21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_MR22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_MR23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_MR25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_MR26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_MR27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */ -#define EXTI_EMR_MR31 ((uint32_t)0x80000000U) /*!< Event Mask on line 31 */ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR20_Pos (20U) +#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_MR21_Pos (21U) +#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_MR22_Pos (22U) +#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_MR23_Pos (23U) +#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_MR25_Pos (25U) +#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_MR26_Pos (26U) +#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_MR27_Pos (27U) +#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ +#define EXTI_EMR_MR31_Pos (31U) +#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -1454,7 +2139,7 @@ typedef struct #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 #define EXTI_EMR_EM19 EXTI_EMR_MR19 -#define EXTI_EMR_EM20 EXTI_EMR_MR0 +#define EXTI_EMR_EM20 EXTI_EMR_MR20 #define EXTI_EMR_EM21 EXTI_EMR_MR21 #define EXTI_EMR_EM22 EXTI_EMR_MR22 #define EXTI_EMR_EM23 EXTI_EMR_MR23 @@ -1464,28 +2149,75 @@ typedef struct #define EXTI_EMR_EM31 EXTI_EMR_MR31 /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR20_Pos (20U) +#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_TR21_Pos (21U) +#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_TR22_Pos (22U) +#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_TR31_Pos (31U) +#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -1510,30 +2242,78 @@ typedef struct #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 +#define EXTI_RTSR_RT31 EXTI_RTSR_TR31 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR20_Pos (20U) +#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_TR21_Pos (21U) +#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_TR22_Pos (22U) +#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_TR31_Pos (31U) +#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */ +#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -1558,30 +2338,78 @@ typedef struct #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 +#define EXTI_FTSR_FT31 EXTI_FTSR_TR31 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER20_Pos (20U) +#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWIER21_Pos (21U) +#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWIER22_Pos (22U) +#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWIER31_Pos (31U) +#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */ +#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -1606,30 +2434,78 @@ typedef struct #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 +#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PR20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PR21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PR22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PR20_Pos (20U) +#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PR21_Pos (21U) +#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PR22_Pos (22U) +#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */ +#define EXTI_PR_PR31_Pos (31U) +#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */ +#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit 31 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -1654,6 +2530,7 @@ typedef struct #define EXTI_PR_PIF20 EXTI_PR_PR20 #define EXTI_PR_PIF21 EXTI_PR_PR21 #define EXTI_PR_PIF22 EXTI_PR_PR22 +#define EXTI_PR_PIF31 EXTI_PR_PR31 /******************************************************************************/ /* */ @@ -1662,63 +2539,137 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020U) /*!< Prefetch Buffer Status */ +#define FLASH_ACR_PRFTBE_Pos (4U) +#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS_Pos (5U) +#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ /****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFFU) /*!< FPEC Key */ +#define FLASH_KEYR_FKEYR_Pos (0U) +#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ /***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option Byte Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash program erase key1 */ -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ -#define FLASH_OPTKEY1 ((uint32_t)0x45670123U) /*!< Flash option key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash option key2: used with FLASH_OPTKEY1 to +#define FLASH_OPTKEY1_Pos (0U) +#define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ +#define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ +#define FLASH_OPTKEY2_Pos (0U) +#define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_PGERR ((uint32_t)0x00000004U) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010U) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint32_t)0x00000020U) /*!< End of operation */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_PGERR_Pos (2U) +#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ +#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ +#define FLASH_SR_WRPRTERR_Pos (4U) +#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ +#define FLASH_SR_EOP_Pos (5U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ /******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint32_t)0x00000001U) /*!< Programming */ -#define FLASH_CR_PER ((uint32_t)0x00000002U) /*!< Page Erase */ -#define FLASH_CR_MER ((uint32_t)0x00000004U) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint32_t)0x00000010U) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint32_t)0x00000020U) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint32_t)0x00000040U) /*!< Start */ -#define FLASH_CR_LOCK ((uint32_t)0x00000080U) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint32_t)0x00000200U) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint32_t)0x00000400U) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint32_t)0x00001000U) /*!< End of operation interrupt enable */ -#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000U) /*!< Option Bytes Loader Launch */ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ +#define FLASH_CR_OPTPG_Pos (4U) +#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ +#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ +#define FLASH_CR_OPTER_Pos (5U) +#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ +#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ +#define FLASH_CR_STRT_Pos (6U) +#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ +#define FLASH_CR_LOCK_Pos (7U) +#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ +#define FLASH_CR_OPTWRE_Pos (9U) +#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ +#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE_Pos (10U) +#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE_Pos (12U) +#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (13U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ /******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFFU) /*!< Flash Address */ +#define FLASH_AR_FAR_Pos (0U) +#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint32_t)0x00000001U) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002U) /*!< Read protection Level 1 */ -#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004U) /*!< Read protection Level 2 */ - -#define FLASH_OBR_USER ((uint32_t)0x00007700U) /*!< User Option Bytes */ -#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100U) /*!< IWDG SW */ -#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200U) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400U) /*!< nRST_STDBY */ -#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000U) /*!< nBOOT1 */ -#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000U) /*!< VDDA power supply supervisor */ -#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000U) /*!< RAM parity check */ -#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000U) /*!< Data0 */ -#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000U) /*!< Data1 */ +#define FLASH_OBR_OPTERR_Pos (0U) +#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ +#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT1_Pos (1U) +#define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ +#define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ +#define FLASH_OBR_RDPRT2_Pos (2U) +#define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ +#define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ + +#define FLASH_OBR_USER_Pos (8U) +#define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ +#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OBR_IWDG_SW_Pos (8U) +#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ +#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ +#define FLASH_OBR_nRST_STOP_Pos (9U) +#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ +#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY_Pos (10U) +#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ +#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OBR_nBOOT1_Pos (12U) +#define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ +#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ +#define FLASH_OBR_VDDA_MONITOR_Pos (13U) +#define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ +#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) +#define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ +#define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ +#define FLASH_OBR_DATA0_Pos (16U) +#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ +#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ +#define FLASH_OBR_DATA1_Pos (24U) +#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -1727,33 +2678,59 @@ typedef struct #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protect */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for OB_RDP register **********************/ -#define OB_RDP_RDP ((uint32_t)0x000000FFU) /*!< Read protection option byte */ -#define OB_RDP_nRDP ((uint32_t)0x0000FF00U) /*!< Read protection complemented option byte */ +#define OB_RDP_RDP_Pos (0U) +#define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */ +#define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ +#define OB_RDP_nRDP_Pos (8U) +#define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ +#define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ /****************** Bit definition for OB_USER register *********************/ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< User option byte */ -#define OB_USER_nUSER ((uint32_t)0xFF000000U) /*!< User complemented option byte */ +#define OB_USER_USER_Pos (16U) +#define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */ +#define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ +#define OB_USER_nUSER_Pos (24U) +#define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ +#define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ /****************** Bit definition for OB_WRP0 register *********************/ -#define OB_WRP0_WRP0 ((uint32_t)0x000000FFU) /*!< Flash memory write protection option bytes */ -#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP0_WRP0_Pos (0U) +#define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ +#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP0_nWRP0_Pos (8U) +#define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ +#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP1 register *********************/ -#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000U) /*!< Flash memory write protection option bytes */ -#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP1_WRP1_Pos (16U) +#define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ +#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP1_nWRP1_Pos (24U) +#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ +#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP2 register *********************/ -#define OB_WRP2_WRP2 ((uint32_t)0x000000FFU) /*!< Flash memory write protection option bytes */ -#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP2_WRP2_Pos (0U) +#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */ +#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP2_nWRP2_Pos (8U) +#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ +#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP3 register *********************/ -#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000U) /*!< Flash memory write protection option bytes */ -#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP3_WRP3_Pos (16U) +#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ +#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP3_nWRP3_Pos (24U) +#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ +#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ /******************************************************************************/ /* */ @@ -1761,122 +2738,186 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODER0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODER1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODER2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODER4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODER6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODER8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODER10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODER12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODER14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) +#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk +#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) +#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk +#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) +#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk +#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) +#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk +#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) +#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk +#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) +#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk +#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) +#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk +#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) +#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk +#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) +#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk +#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) +#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk +#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) +#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk +#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) +#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk +#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) +#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk +#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) +#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk +#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) +#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk +#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) +#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk +#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 @@ -1929,181 +2970,331 @@ typedef struct #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPDR0_Pos (0U) +#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk +#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPDR1_Pos (2U) +#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk +#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPDR2_Pos (4U) +#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk +#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPDR3_Pos (6U) +#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk +#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPDR4_Pos (8U) +#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk +#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPDR5_Pos (10U) +#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk +#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPDR6_Pos (12U) +#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk +#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPDR7_Pos (14U) +#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk +#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPDR8_Pos (16U) +#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk +#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPDR9_Pos (18U) +#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk +#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPDR10_Pos (20U) +#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk +#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPDR11_Pos (22U) +#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk +#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPDR12_Pos (24U) +#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk +#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPDR13_Pos (26U) +#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk +#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPDR14_Pos (28U) +#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk +#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPDR15_Pos (30U) +#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk +#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_0 ((uint32_t)0x00000001U) -#define GPIO_IDR_1 ((uint32_t)0x00000002U) -#define GPIO_IDR_2 ((uint32_t)0x00000004U) -#define GPIO_IDR_3 ((uint32_t)0x00000008U) -#define GPIO_IDR_4 ((uint32_t)0x00000010U) -#define GPIO_IDR_5 ((uint32_t)0x00000020U) -#define GPIO_IDR_6 ((uint32_t)0x00000040U) -#define GPIO_IDR_7 ((uint32_t)0x00000080U) -#define GPIO_IDR_8 ((uint32_t)0x00000100U) -#define GPIO_IDR_9 ((uint32_t)0x00000200U) -#define GPIO_IDR_10 ((uint32_t)0x00000400U) -#define GPIO_IDR_11 ((uint32_t)0x00000800U) -#define GPIO_IDR_12 ((uint32_t)0x00001000U) -#define GPIO_IDR_13 ((uint32_t)0x00002000U) -#define GPIO_IDR_14 ((uint32_t)0x00004000U) -#define GPIO_IDR_15 ((uint32_t)0x00008000U) +#define GPIO_IDR_0 (0x00000001U) +#define GPIO_IDR_1 (0x00000002U) +#define GPIO_IDR_2 (0x00000004U) +#define GPIO_IDR_3 (0x00000008U) +#define GPIO_IDR_4 (0x00000010U) +#define GPIO_IDR_5 (0x00000020U) +#define GPIO_IDR_6 (0x00000040U) +#define GPIO_IDR_7 (0x00000080U) +#define GPIO_IDR_8 (0x00000100U) +#define GPIO_IDR_9 (0x00000200U) +#define GPIO_IDR_10 (0x00000400U) +#define GPIO_IDR_11 (0x00000800U) +#define GPIO_IDR_12 (0x00001000U) +#define GPIO_IDR_13 (0x00002000U) +#define GPIO_IDR_14 (0x00004000U) +#define GPIO_IDR_15 (0x00008000U) /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_0 ((uint32_t)0x00000001U) -#define GPIO_ODR_1 ((uint32_t)0x00000002U) -#define GPIO_ODR_2 ((uint32_t)0x00000004U) -#define GPIO_ODR_3 ((uint32_t)0x00000008U) -#define GPIO_ODR_4 ((uint32_t)0x00000010U) -#define GPIO_ODR_5 ((uint32_t)0x00000020U) -#define GPIO_ODR_6 ((uint32_t)0x00000040U) -#define GPIO_ODR_7 ((uint32_t)0x00000080U) -#define GPIO_ODR_8 ((uint32_t)0x00000100U) -#define GPIO_ODR_9 ((uint32_t)0x00000200U) -#define GPIO_ODR_10 ((uint32_t)0x00000400U) -#define GPIO_ODR_11 ((uint32_t)0x00000800U) -#define GPIO_ODR_12 ((uint32_t)0x00001000U) -#define GPIO_ODR_13 ((uint32_t)0x00002000U) -#define GPIO_ODR_14 ((uint32_t)0x00004000U) -#define GPIO_ODR_15 ((uint32_t)0x00008000U) +#define GPIO_ODR_0 (0x00000001U) +#define GPIO_ODR_1 (0x00000002U) +#define GPIO_ODR_2 (0x00000004U) +#define GPIO_ODR_3 (0x00000008U) +#define GPIO_ODR_4 (0x00000010U) +#define GPIO_ODR_5 (0x00000020U) +#define GPIO_ODR_6 (0x00000040U) +#define GPIO_ODR_7 (0x00000080U) +#define GPIO_ODR_8 (0x00000100U) +#define GPIO_ODR_9 (0x00000200U) +#define GPIO_ODR_10 (0x00000400U) +#define GPIO_ODR_11 (0x00000800U) +#define GPIO_ODR_12 (0x00001000U) +#define GPIO_ODR_13 (0x00002000U) +#define GPIO_ODR_14 (0x00004000U) +#define GPIO_ODR_15 (0x00008000U) /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -2112,111 +3303,279 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register ****************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register ****************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register ********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register ********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *******************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *******************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /*****************************************************************************/ /* */ @@ -2224,24 +3583,38 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for IWDG_KR register *******************/ -#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register *******************/ -#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ /******************* Bit definition for IWDG_RLR register ******************/ -#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register *******************/ -#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register *******************/ -#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /*****************************************************************************/ /* */ @@ -2253,43 +3626,81 @@ typedef struct /******************** Bit definition for PWR_CR register *******************/ -#define PWR_CR_LPDS ((uint32_t)0x00000001U) /*!< Low-power Deepsleep */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ - -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register *******************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ - -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ -#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */ -#define PWR_CSR_EWUP4 ((uint32_t)0x00000800U) /*!< Enable WKUP pin 4 */ -#define PWR_CSR_EWUP5 ((uint32_t)0x00001000U) /*!< Enable WKUP pin 5 */ -#define PWR_CSR_EWUP6 ((uint32_t)0x00002000U) /*!< Enable WKUP pin 6 */ -#define PWR_CSR_EWUP7 ((uint32_t)0x00004000U) /*!< Enable WKUP pin 7 */ -#define PWR_CSR_EWUP8 ((uint32_t)0x00008000U) /*!< Enable WKUP pin 8 */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ + +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP3_Pos (10U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP4_Pos (11U) +#define PWR_CSR_EWUP4_Msk (0x1U << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */ +#define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */ +#define PWR_CSR_EWUP5_Pos (12U) +#define PWR_CSR_EWUP5_Msk (0x1U << PWR_CSR_EWUP5_Pos) /*!< 0x00001000 */ +#define PWR_CSR_EWUP5 PWR_CSR_EWUP5_Msk /*!< Enable WKUP pin 5 */ +#define PWR_CSR_EWUP6_Pos (13U) +#define PWR_CSR_EWUP6_Msk (0x1U << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */ +#define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */ +#define PWR_CSR_EWUP7_Pos (14U) +#define PWR_CSR_EWUP7_Msk (0x1U << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */ +#define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */ +#define PWR_CSR_EWUP8_Pos (15U) +#define PWR_CSR_EWUP8_Msk (0x1U << PWR_CSR_EWUP8_Pos) /*!< 0x00008000 */ +#define PWR_CSR_EWUP8 PWR_CSR_EWUP8_Msk /*!< Enable WKUP pin 8 */ /*****************************************************************************/ /* */ @@ -2297,156 +3708,206 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 family) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ /******************** Bit definition for RCC_CR register *******************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002U) /*!< Internal High Speed clock ready flag */ - -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8U) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008U) /*!