From abd118ef2d74d46717a95f0c3309237fc3c1f170 Mon Sep 17 00:00:00 2001 From: roccomarco Date: Sat, 1 Jul 2017 11:39:03 +0000 Subject: Updated CMSIS headers for STM32 MCUs git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10267 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h | 9544 +++++++++++++++--------- 1 file changed, 6210 insertions(+), 3334 deletions(-) (limited to 'os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h') diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h b/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h index b73d40ab6..ec3d620d4 100644 --- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h +++ b/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l151xb.h * @author MCD Application Team - * @version V2.1.1 - * @date 31-March-2015 + * @version 21-April-2017 + * @date V2.2.1 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -88,6 +88,7 @@ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ @@ -199,9 +200,14 @@ typedef struct typedef struct { - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + /** * @brief CRC calculation unit */ @@ -209,7 +215,9 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; @@ -568,76 +576,78 @@ typedef struct * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x0801FFFF) /*!< Program end FLASH address for Cat1 & Cat2 */ -#define FLASH_EEPROM_END ((uint32_t)0x08080FFF) /*!< FLASH EEPROM end address (4KB) */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0801FFFFU) /*!< Program end FLASH address for Cat1 & Cat2 */ +#define FLASH_EEPROM_END ((uint32_t)0x08080FFFU) /*!< FLASH EEPROM end address (4KB) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FF8004CU) /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ /** * @} @@ -664,18 +674,29 @@ typedef struct #define USB ((USB_TypeDef *) USB_BASE) /* USB device FS SRAM */ #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define COMP ((COMP_TypeDef *) COMP_BASE) -#define COMP1 ((COMP_TypeDef *) COMP_BASE) -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) + +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +/* Legacy define */ +#define DAC DAC1 + +#define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ +#define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ + #define RI ((RI_TypeDef *) RI_BASE) + #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +/* Legacy defines */ +#define ADC ADC1_COMMON + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -720,524 +741,756 @@ typedef struct /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOCS_Pos (1U) +#define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ +#define ADC_SR_OVR_Pos (5U) +#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ +#define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_SR_ADONS_Pos (6U) +#define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ +#define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ +#define ADC_SR_RCNR_Pos (8U) +#define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ +#define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ +#define ADC_SR_JCNR_Pos (9U) +#define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ +#define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOCS) +#define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ - -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOCSIE_Pos (5U) +#define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_PDD_Pos (16U) +#define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ +#define ADC_CR1_PDI_Pos (17U) +#define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ +#define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CR1_RES_Pos (24U) +#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ +#define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ +#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ +#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ + +#define ADC_CR1_OVRIE_Pos (26U) +#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ +#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ + +#define ADC_CR2_DELS_Pos (4U) +#define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ +#define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ +#define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ +#define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ +#define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ + +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_DDS_Pos (9U) +#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ +#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ +#define ADC_CR2_EOCS_Pos (10U) +#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ +#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CR2_JEXTSEL_Pos (16U) +#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ +#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_JEXTEN_Pos (20U) +#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ +#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ +#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ + +#define ADC_CR2_JSWSTART_Pos (22U) +#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ + +#define ADC_CR2_EXTSEL_Pos (24U) +#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ +#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ +#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ +#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ + +#define ADC_CR2_EXTEN_Pos (28U) +#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ +#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ +#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ + +#define ADC_CR2_SWSTART_Pos (30U) +#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ -#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ -#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ -#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ -#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR1_SMP20_Pos (0U) +#define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ +#define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP21_Pos (3U) +#define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ +#define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP22_Pos (6U) +#define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ +#define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP23_Pos (9U) +#define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ +#define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP24_Pos (12U) +#define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ +#define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP25_Pos (15U) +#define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ +#define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP26_Pos (18U) +#define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ +#define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SMPR3_SMP0_Pos (0U) +#define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR3_SMP1_Pos (3U) +#define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR3_SMP2_Pos (6U) +#define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR3_SMP3_Pos (9U) +#define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR3_SMP4_Pos (12U) +#define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR3_SMP5_Pos (15U) +#define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR3_SMP6_Pos (18U) +#define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR3_SMP7_Pos (21U) +#define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR3_SMP8_Pos (24U) +#define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR3_SMP9_Pos (27U) +#define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ +#define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */ + +#define ADC_SQR1_SQ27_Pos (10U) +#define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ +#define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ26_Pos (5U) +#define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ +#define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ25_Pos (0U) +#define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ +#define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR2_SQ19_Pos (0U) +#define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ +#define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ20_Pos (5U) +#define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ +#define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ21_Pos (10U) +#define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ +#define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ22_Pos (15U) +#define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ +#define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ23_Pos (20U) +#define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ +#define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ24_Pos (25U) +#define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ +#define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR3_SQ13_Pos (0U) +#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ14_Pos (5U) +#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ15_Pos (10U) +#define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ16_Pos (15U) +#define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ17_Pos (20U) +#define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ +#define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ18_Pos (25U) +#define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ +#define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR4_SQ7_Pos (0U) +#define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ8_Pos (5U) +#define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR4_SQ9_Pos (10U) +#define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR4_SQ10_Pos (15U) +#define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR4_SQ11_Pos (20U) +#define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR4_SQ12_Pos (25U) +#define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR5_SQ1_Pos (0U) +#define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR5_SQ2_Pos (5U) +#define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR5_SQ3_Pos (10U) +#define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR5_SQ4_Pos (15U) +#define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR5_SQ5_Pos (20U) +#define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR5_SQ6_Pos (25U) +#define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ /******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ +#define ADC_CSR_AWD1_Pos (0U) +#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ +#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_EOCS1_Pos (1U) +#define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_CSR_JEOS1_Pos (2U) +#define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ +#define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_JSTRT1_Pos (3U) +#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ +#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ +#define ADC_CSR_STRT1_Pos (4U) +#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ +#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ +#define ADC_CSR_OVR1_Pos (5U) +#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ +#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_ADONS1_Pos (6U) +#define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ +#define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ + +/* Legacy defines */ +#define ADC_CSR_EOC1 (ADC_CSR_EOCS1) +#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ +#define ADC_CCR_ADCPRE_Pos (16U) +#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ +#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_TSVREFE_Pos (23U) +#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /******************************************************************************/ /* */ @@ -1246,25 +1499,45 @@ typedef struct /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ +#define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ +#define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ +#define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ +#define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ +#define COMP_CSR_CMP1EN_Pos (4U) +#define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ +#define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ +#define COMP_CSR_CMP1OUT_Pos (7U) +#define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ +#define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ +#define COMP_CSR_SPEED_Pos (12U) +#define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ +#define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ +#define COMP_CSR_CMP2OUT_Pos (13U) +#define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ +#define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ + +#define COMP_CSR_WNDWE_Pos (17U) +#define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ +#define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_INSEL_Pos (18U) +#define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ +#define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ +#define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ +#define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_OUTSEL_Pos (21U) +#define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ +#define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ + +/* Bits present in COMP register but not related to comparator */ +/* (or partially related to comparator, in addition to other peripherals) */ +#define COMP_CSR_VREFOUTEN_Pos (16U) +#define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ +#define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ /******************************************************************************/ /* */ @@ -1273,13 +1546,19 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ /******************************************************************************/ /* */ @@ -1288,91 +1567,159 @@ typedef struct /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!