From f50d9fb0480b9ce521e80af21ffbff79e0ca5b44 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 18 Aug 2012 13:17:03 +0000
Subject: Added support for STM32 OTH_HS peripheral (not tested yet).

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4578 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F2xx/stm32_rcc.h | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F2xx/stm32_rcc.h')

diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h
index 0bd3a6401..2b2051332 100644
--- a/os/hal/platforms/STM32F2xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h
@@ -603,7 +603,7 @@
  *
  * @api
  */
-#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
 
 /**
  * @brief   Disables the OTG_FS peripheral clock.
@@ -612,7 +612,7 @@
  *
  * @api
  */
-#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
 
 /**
  * @brief   Resets the OTG_FS peripheral.
@@ -620,6 +620,31 @@
  * @api
  */
 #define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+
+/**
+ * @brief   Enables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief   Disables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief   Resets the OTG_HS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST)
 /** @} */
 
 /**
-- 
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