From 82d5cb36c37aa9de158a47397de802b181d0abd6 Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 11 Oct 2012 17:57:18 +0000 Subject: F4x PLL clock checking fixed. According to RM0090 the value of PLLN may be between 64 and 432. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4740 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F4xx') diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index ce01b9ce0..a8f61cf62 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -986,7 +986,7 @@ /** * @brief STM32_PLLN field. */ -#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) || \ +#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ defined(__DOXYGEN__) #define STM32_PLLN (STM32_PLLN_VALUE << 6) #else -- cgit v1.2.3