From afec43446f5210546490f4289e15bdd78405c94a Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sun, 30 Dec 2018 13:04:09 +0000
Subject: Fixed H7 ADC clock settings.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12495 110e8d01-0319-4d1e-a829-52ad28d1bb01
---
 testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h     | 2 +-
 testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h     | 2 +-
 testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h     | 2 +-
 testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'testhal')

diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
index 87b28c672..da2d83264 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -92,7 +92,7 @@
 #define STM32_PLL2_DIVM_VALUE               4
 #define STM32_PLL2_DIVN_VALUE               400
 #define STM32_PLL2_FRACN_VALUE              0
-#define STM32_PLL2_DIVP_VALUE               8
+#define STM32_PLL2_DIVP_VALUE               40
 #define STM32_PLL2_DIVQ_VALUE               8
 #define STM32_PLL2_DIVR_VALUE               8
 #define STM32_PLL3_ENABLED                  TRUE
diff --git a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
index 5f1c781a7..0037a4d90 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -92,7 +92,7 @@
 #define STM32_PLL2_DIVM_VALUE               4
 #define STM32_PLL2_DIVN_VALUE               400
 #define STM32_PLL2_FRACN_VALUE              0
-#define STM32_PLL2_DIVP_VALUE               8
+#define STM32_PLL2_DIVP_VALUE               40
 #define STM32_PLL2_DIVQ_VALUE               8
 #define STM32_PLL2_DIVR_VALUE               8
 #define STM32_PLL3_ENABLED                  TRUE
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
index e22dd7fe7..18662c782 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
@@ -92,7 +92,7 @@
 #define STM32_PLL2_DIVM_VALUE               4
 #define STM32_PLL2_DIVN_VALUE               400
 #define STM32_PLL2_FRACN_VALUE              0
-#define STM32_PLL2_DIVP_VALUE               8
+#define STM32_PLL2_DIVP_VALUE               40
 #define STM32_PLL2_DIVQ_VALUE               8
 #define STM32_PLL2_DIVR_VALUE               8
 #define STM32_PLL3_ENABLED                  TRUE
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
index e642c6301..3920704a5 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -92,7 +92,7 @@
 #define STM32_PLL2_DIVM_VALUE               4
 #define STM32_PLL2_DIVN_VALUE               400
 #define STM32_PLL2_FRACN_VALUE              0
-#define STM32_PLL2_DIVP_VALUE               8
+#define STM32_PLL2_DIVP_VALUE               40
 #define STM32_PLL2_DIVQ_VALUE               8
 #define STM32_PLL2_DIVR_VALUE               8
 #define STM32_PLL3_ENABLED                  TRUE
-- 
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