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--  Mcode back-end for ortho - Binary X86 instructions generator.
--  Copyright (C) 2006 Tristan Gingold
--
--  GHDL is free software; you can redistribute it and/or modify it under
--  the terms of the GNU General Public License as published by the Free
--  Software Foundation; either version 2, or (at your option) any later
--  version.
--
--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--  for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with GCC; see the file COPYING.  If not, write to the Free
--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
--  02111-1307, USA.
with Ortho_Code.Abi;
with Ortho_Code.Decls;
with Ortho_Code.Types;
with Ortho_Code.Consts;
with Ortho_Code.Debug;
with Ortho_Code.X86.Insns;
with Ortho_Code.X86.Flags;
with Ortho_Code.Flags;
with Ortho_Code.Dwarf;
with Ortho_Code.Binary; use Ortho_Code.Binary;
with Ortho_Ident;
with Ada.Text_IO;
with Interfaces; use Interfaces;

package body Ortho_Code.X86.Emits is
   type Insn_Size is (Sz_8, Sz_16, Sz_32, Sz_32l, Sz_32h, Sz_64);

   --  Sz_64 if M64 or Sz_32
   Sz_Ptr : constant Insn_Size := Insn_Size'Val
     (Boolean'Pos (Flags.M64) * Insn_Size'Pos (Sz_64)
        + Boolean'Pos (not Flags.M64) * Insn_Size'Pos (Sz_32));

   --  For FP, size doesn't matter in modrm and SIB.  But don't emit the REX.W
   --  prefix, that's useless.
   Sz_Fp : constant Insn_Size := Sz_32;

   type Int_Mode_To_Size_Array is array (Mode_U8 .. Mode_I64) of Insn_Size;
   Int_Mode_To_Size : constant Int_Mode_To_Size_Array :=
     (Mode_U8  | Mode_I8 => Sz_8,
      Mode_U16 | Mode_I16 => Sz_16,
      Mode_U32 | Mode_I32 => Sz_32,
      Mode_U64 | Mode_I64 => Sz_64);

   --  Well known sections.
   Sect_Text : Binary_File.Section_Acc;
   Sect_Rodata : Binary_File.Section_Acc;
   Sect_Bss : Binary_File.Section_Acc;

   --  For 64 bit to 32 bit conversion, we need an extra register.  Just before
   --  the conversion, there is an OE_Reg instruction containing the extra
   --  register.  Its value is saved here.
   Reg_Helper : O_Reg;

   Subprg_Pc : Pc_Type;

   --  x86 opcodes.
   Opc_Data16 : constant := 16#66#;
--   Opc_Rex    : constant := 16#40#;
   Opc_Rex_W  : constant := 16#48#;
   Opc_Rex_R  : constant := 16#44#;
   Opc_Rex_X  : constant := 16#42#;
   Opc_Rex_B  : constant := 16#41#;
   Opc_Into   : constant := 16#ce#;
   Opc_Cdq    : constant := 16#99#;
   Opc_Int    : constant := 16#cd#;
   Opc_Addl_Reg_Rm  : constant := 16#03#;
   Opc_Xorl_Rm_Reg  : constant := 16#31#;
   Opc_Subl_Reg_Rm  : constant := 16#2b#;  --  Reg <- Reg - Rm
   Opc_Cmpl_Rm_Reg  : constant := 16#39#;
   Opc_Leal_Reg_Rm  : constant := 16#8d#;
   Opc_Movb_Imm_Reg : constant := 16#b0#;
   Opc_Movl_Imm_Reg : constant := 16#b8#;
   Opc_Movsxd_Reg_Rm : constant := 16#63#;
   Opc_Imul_Reg_Rm_Imm32 : constant := 16#69#;
   Opc_Imul_Reg_Rm_Imm8  : constant := 16#6b#;
   Opc_Mov_Rm_Imm : constant := 16#c6#;  -- Eb,Ib  or Ev,Iz (grp11, opc2=0)
   Opc_Mov_Rm_Reg : constant := 16#88#;  -- Store: Eb,Gb  or  Ev,Gv
   Opc_Mov_Reg_Rm : constant := 16#8a#;  -- Load:  Gb,Eb  or  Gv,Ev
   Opc_Movl_Reg_Rm : constant := 16#8b#;  -- Load: Gv,Ev
   --  Opc_Grp1_Rm_Imm : constant := 16#80#;
   Opc_Grp1b_Rm_Imm8  : constant := 16#80#;
   Opc_Grp1v_Rm_Imm32 : constant := 16#81#;
   --  Opc_Grp1b_Rm_Imm8  : constant := 16#82#; -- Should not be used.
   Opc_Grp1v_Rm_Imm8  : constant := 16#83#;
   Opc2_Grp1_Add   : constant := 2#000_000#; --  Second byte
   Opc2_Grp1_Or    : constant := 2#001_000#; --  Second byte
   Opc2_Grp1_Adc   : constant := 2#010_000#; --  Second byte
   Opc2_Grp1_Sbb   : constant := 2#011_000#; --  Second byte
   Opc2_Grp1_And   : constant := 2#100_000#; --  Second byte
   Opc2_Grp1_Sub   : constant := 2#101_000#; --  Second byte
   Opc2_Grp1_Xor   : constant := 2#110_000#; --  Second byte
   Opc2_Grp1_Cmp   : constant := 2#111_000#; --  Second byte
   Opc_Grp3_Width  : constant := 16#f6#;
   Opc2_Grp3_Not   : constant := 2#010_000#;
   Opc2_Grp3_Neg   : constant := 2#011_000#;
   Opc2_Grp3_Mul   : constant := 2#100_000#;
   Opc2_Grp3_Imul  : constant := 2#101_000#;
   Opc2_Grp3_Div   : constant := 2#110_000#;
   Opc2_Grp3_Idiv  : constant := 2#111_000#;
   Opc_Test_Rm_Reg : constant := 16#84#;  --  Eb,Gb  or  Ev,Gv
   Opc_Push_Imm8   : constant := 16#6a#;
   Opc_Push_Imm    : constant := 16#68#;
   Opc_Push_Reg    : constant := 16#50#; --  opc[2:0] is reg.
   Opc_Pop_Reg     : constant := 16#58#; --  opc[2:0] is reg.
   Opc_Grp5        : constant := 16#ff#;
   Opc2_Grp5_Push_Rm : constant := 2#110_000#;
   --  Opc_Grp1a       : constant := 16#8f#;
   --  Opc2_Grp1a_Pop_Rm : constant := 2#000_000#;
   Opc_Jcc         : constant := 16#70#;
   Opc_0f          : constant := 16#0f#;
   Opc2_0f_Jcc     : constant := 16#80#;
   Opc2_0f_Setcc   : constant := 16#90#;
   Opc2_0f_Movzx   : constant := 16#b6#;
   Opc2_0f_Imul    : constant := 16#af#;
   Opc2_0f_Andp    : constant := 16#54#;
   Opc2_0f_Xorp    : constant := 16#57#;
   Opc_Call        : constant := 16#e8#;
   Opc_Jmp_Long    : constant := 16#e9#;
   Opc_Jmp_Short   : constant := 16#eb#;
   Opc_Ret         : constant := 16#c3#;
   Opc_Leave       : constant := 16#c9#;
   Opc_Movsd_Xmm_M64 : constant := 16#10#;  --  Load xmm <- M64
   Opc_Movsd_M64_Xmm : constant := 16#11#;  --  Store M64 <- xmm
   Opc_Cvtsi2sd_Xmm_Rm : constant := 16#2a#;  --  Xmm <- cvt (rm)
   Opc_Cvtsd2si_Reg_Xm : constant := 16#2d#;  --  Reg <- cvt (xmm/m64)

   procedure Error_Emit (Msg : String; Insn : O_Enode)
   is
      use Ada.Text_IO;
   begin
      Put ("error_emit: ");
      Put (Msg);
      Put (", insn=");
      Put (O_Enode'Image (Insn));
      Put (" (");
      Put (OE_Kind'Image (Get_Expr_Kind (Insn)));
      Put (")");
      New_Line;
      raise Program_Error;
   end Error_Emit;

   procedure Gen_Rex (B : Byte) is
   begin
      if Flags.M64 then
         Gen_8 (B);
      end if;
   end Gen_Rex;

   procedure Gen_Rex_B (R : O_Reg; Sz : Insn_Size)
   is
      B : Byte;
   begin
      if Flags.M64 then
         B := 0;
         if R in Regs_R8_R15 or R in Regs_Xmm8_Xmm15 then
            B := B or Opc_Rex_B;
         end if;
         if Sz = Sz_64 then
            B := B or Opc_Rex_W;
         end if;
         if B /= 0 then
            Gen_8 (B);
         end if;
      end if;
   end Gen_Rex_B;

   --  For many opcodes, the size of the operand is coded in bit 0, and the
   --  prefix data16 can be used for 16-bit operation.
   --  Deal with size.
   procedure Gen_Insn_Sz (B : Byte; Sz : Insn_Size) is
   begin
      case Sz is
         when Sz_8 =>
            Gen_8 (B);
         when Sz_16 =>
            Gen_8 (Opc_Data16);
            Gen_8 (B + 1);
         when Sz_32
           | Sz_32l
           | Sz_32h
           | Sz_64 =>
            Gen_8 (B + 1);
      end case;
   end Gen_Insn_Sz;

   procedure Gen_Insn_Sz_S8 (B : Byte; Sz : Insn_Size) is
   begin
      case Sz is
         when Sz_8 =>
            Gen_8 (B);
         when Sz_16 =>
            Gen_8 (Opc_Data16);
            Gen_8 (B + 3);
         when Sz_32
           | Sz_32l
           | Sz_32h
           | Sz_64 =>
            Gen_8 (B + 3);
      end case;
   end Gen_Insn_Sz_S8;

   function Get_Const_Val (C : O_Enode; Sz : Insn_Size) return Uns32 is
   begin
      case Sz is
         when Sz_8
           | Sz_16
           | Sz_32
           | Sz_32l =>
            return Get_Expr_Low (C);
         when Sz_32h =>
            return Get_Expr_High (C);
         when Sz_64 =>
            return Get_Expr_Low (C);
      end case;
   end Get_Const_Val;

   function Is_Imm8 (N : O_Enode; Sz : Insn_Size) return Boolean is
   begin
      if Get_Expr_Kind (N) /= OE_Const then
         return False;
      end if;
      return Get_Const_Val (N, Sz) <= 127;
   end Is_Imm8;

   procedure Gen_Imm8 (N : O_Enode; Sz : Insn_Size) is
   begin
      Gen_8 (Byte (Get_Const_Val (N, Sz)));
   end Gen_Imm8;

--     procedure Gen_Imm32 (N : O_Enode; Sz : Insn_Size)
--     is
--        use Interfaces;
--     begin
--        case Get_Expr_Kind (N) is
--           when OE_Const =>
--              Gen_32 (Unsigned_32 (Get_Const_Val (N, Sz)));
--           when OE_Addrg =>
--              Gen_X86_32 (Get_Decl_Symbol (Get_Addr_Object (N)), 0);
--           when others =>
--              raise Program_Error;
--        end case;
--     end Gen_Imm32;

   --  Generate an immediat constant.
   procedure Gen_Imm_Addr (N : O_Enode)
   is
      Sym : Symbol;
      P : O_Enode;
      L, R : O_Enode;
      S, C : O_Enode;
      Off : Int32;
   begin
      Off := 0;
      P := N;
      while Get_Expr_Kind (P) = OE_Add loop
         L := Get_Expr_Left (P);
         R := Get_Expr_Right (P);

         --  Extract the const node.
         if Get_Expr_Kind (R) = OE_Const then
            S := L;
            C := R;
         elsif Get_Expr_Kind (L) = OE_Const then
            S := R;
            C := L;
         else
            raise Program_Error;
         end if;
         pragma Assert (Get_Expr_Mode (C) = Mode_U32);
         Off := Off + To_Int32 (Get_Expr_Low (C));
         P := S;
      end loop;
      pragma Assert (Get_Expr_Kind (P) = OE_Addrg);
      Sym := Get_Decl_Symbol (Get_Addr_Object (P));
      Gen_Abs (Sym, Integer_32 (Off));
   end Gen_Imm_Addr;

   --  Generate an immediat constant.
   procedure Gen_Imm (N : O_Enode; Sz : Insn_Size) is
   begin
      case Get_Expr_Kind (N) is
         when OE_Const =>
            case Sz is
               when Sz_8 =>
                  Gen_8 (Byte (Get_Expr_Low (N) and 16#FF#));
               when Sz_16 =>
                  Gen_16 (Unsigned_32 (Get_Expr_Low (N) and 16#FF_FF#));
               when Sz_32
                 | Sz_32l =>
                  Gen_32 (Unsigned_32 (Get_Expr_Low (N)));
               when Sz_32h =>
                  Gen_32 (Unsigned_32 (Get_Expr_High (N)));
               when Sz_64 =>
                  --  Immediates are sign extended.
                  pragma Assert (Is_Expr_S32 (N));
                  Gen_32 (Unsigned_32 (Get_Expr_Low (N)));
            end case;
         when OE_Add
           | OE_Addrg =>
            --  Only for 32-bit immediat.
            pragma Assert (Sz = Sz_32);
            Gen_Imm_Addr (N);
         when others =>
            raise Program_Error;
      end case;
   end Gen_Imm;

   function To_Reg32 (R : O_Reg) return Byte is
   begin
      pragma Assert (R in Regs_R32);
      return O_Reg'Pos (R) - O_Reg'Pos (R_Ax);
   end To_Reg32;
   pragma Inline (To_Reg32);

   function To_Reg64 (R : O_Reg) return Byte is
   begin
      pragma Assert (R in Regs_R64);
      return Byte (O_Reg'Pos (R) - O_Reg'Pos (R_Ax)) and 7;
   end To_Reg64;
   pragma Inline (To_Reg64);

   function To_Reg_Xmm (R : O_Reg) return Byte is
   begin
      return O_Reg'Pos (R) - O_Reg'Pos (R_Xmm0);
   end To_Reg_Xmm;
   pragma Inline (To_Reg_Xmm);

   function To_Reg32 (R : O_Reg; Sz : Insn_Size) return Byte is
   begin
      case Sz is
         when Sz_8 =>
            pragma Assert ((not Flags.M64 and R in Regs_R8)
                           or (Flags.M64 and R in Regs_R64));
            return To_Reg64 (R);
         when Sz_16 =>
            pragma Assert (R in Regs_R32);
            return To_Reg64 (R);
         when Sz_32 =>
            pragma Assert ((not Flags.M64 and R in Regs_R32)
                           or (Flags.M64 and R in Regs_R64));
            return To_Reg64 (R);
         when Sz_32l =>
            pragma Assert (not Flags.M64);
            case R is
               when R_Edx_Eax =>
                  return 2#000#;
               when R_Ebx_Ecx =>
                  return 2#001#;
               when R_Esi_Edi =>
                  return 2#111#;
               when others =>
                  raise Program_Error;
            end case;
         when Sz_32h =>
            pragma Assert (not Flags.M64);
            case R is
               when R_Edx_Eax =>
                  return 2#010#;
               when R_Ebx_Ecx =>
                  return 2#011#;
               when R_Esi_Edi =>
                  return 2#110#;
               when others =>
                  raise Program_Error;
            end case;
         when Sz_64 =>
            pragma Assert (R in Regs_R64);
            return Byte (O_Reg'Pos (R) - O_Reg'Pos (R_Ax)) and 7;
      end case;
   end To_Reg32;

   function To_Cond (R : O_Reg) return Byte is
   begin
      return O_Reg'Pos (R) - O_Reg'Pos (R_Ov);
   end To_Cond;
   pragma Inline (To_Cond);

   function To_Reg (R : O_Reg; Sz : Insn_Size) return Byte is
   begin
      if R in Regs_Xmm then
         return To_Reg_Xmm (R);
      else
         return To_Reg32 (R, Sz);
      end if;
   end To_Reg;

   --  SIB + disp values.
   SIB_Scale : Byte;
   SIB_Index : O_Reg;
   Rm_Base : O_Reg;
   Rm_Offset : Int32;
   Rm_Sym : Symbol;

   --  If not R_Nil, the reg/opc field (bit 3-5) of the ModR/M byte is a
   --  register.
   Rm_Opc_Reg : O_Reg;
   Rm_Opc_Sz : Insn_Size;

   --  If not R_Nil, encode mod=11 (no memory access).  All above variables
   --  must be 0/R_Nil.
   Rm_Reg : O_Reg;
   Rm_Sz : Insn_Size;

   procedure Gen_Rex_Mod_Rm
   is
      B : Byte;
   begin
      if Flags.M64 then
         B := 0;
         if Rm_Sz = Sz_64 then
            B := B or Opc_Rex_W;
         end if;
         if Rm_Opc_Reg in Regs_R8_R15
           or Rm_Opc_Reg in Regs_Xmm8_Xmm15
         then
            B := B or Opc_Rex_R;
         end if;
         if Rm_Reg in Regs_R8_R15
           or Rm_Reg in Regs_Xmm8_Xmm15
           or Rm_Base in Regs_R8_R15
         then
            B := B or Opc_Rex_B;
         end if;
         if SIB_Index in Regs_R8_R15 then
            B := B or Opc_Rex_X;
         end if;
         if B /= 0 then
            Gen_8 (B);
         end if;
      end if;
   end Gen_Rex_Mod_Rm;

   procedure Fill_Sib (N : O_Enode)
   is
      use Ortho_Code.Decls;
      Reg : constant O_Reg := Get_Expr_Reg (N);
   begin
      --  A simple register.
      if Reg in Regs_R64 then
         if Rm_Base = R_Nil then
            Rm_Base := Reg;
         elsif SIB_Index = R_Nil then
            SIB_Index := Reg;
         else
            --  It is not possible to add 3 registers with SIB.
            raise Program_Error;
         end if;
         return;
      end if;

      case Get_Expr_Kind (N) is
         when OE_Indir =>
            Fill_Sib (Get_Expr_Operand (N));
         when OE_Addrl =>
            declare
               Frame : constant O_Enode := Get_Addrl_Frame (N);
            begin
               if Frame = O_Enode_Null then
                  --  Local frame: use the frame pointer.
                  Rm_Base := R_Bp;
               else
                  --  In an outer frame: use the computed frame register.
                  Rm_Base := Get_Expr_Reg (Frame);
               end if;
            end;
            Rm_Offset := Rm_Offset + Get_Local_Offset (Get_Addr_Object (N));
         when OE_Addrg =>
            --  Cannot add two symbols.
            pragma Assert (Rm_Sym = Null_Symbol);
            Rm_Sym := Get_Decl_Symbol (Get_Addr_Object (N));
         when OE_Add =>
            Fill_Sib (Get_Expr_Left (N));
            Fill_Sib (Get_Expr_Right (N));
         when OE_Const =>
            Rm_Offset := Rm_Offset + To_Int32 (Get_Expr_Low (N));
         when OE_Shl =>
            --  Only one scale.
            pragma Assert (SIB_Index = R_Nil);
            SIB_Index := Get_Expr_Reg (Get_Expr_Left (N));
            SIB_Scale := Byte (Get_Expr_Low (Get_Expr_Right (N)));
         when others =>
            Error_Emit ("fill_sib", N);
      end case;
   end Fill_Sib;

   --  Write the SIB byte.
   procedure Gen_Sib
   is
      Base : Byte;
   begin
      if Rm_Base = R_Nil then
         Base := 2#101#;  --  BP
      else
         pragma Assert (not (SIB_Index = R_Sp
                               and (Rm_Base = R_Bp or Rm_Base = R_R13)));
         Base := To_Reg64 (Rm_Base);
      end if;
      Gen_8
        (SIB_Scale * 2#1_000_000# + To_Reg64 (SIB_Index) * 2#1_000# + Base);
   end Gen_Sib;

   --  ModRM is a register.
   procedure Init_Modrm_Reg (Reg : O_Reg;
                             Sz : Insn_Size;
                             Opc : O_Reg := R_Nil;
                             Opc_Sz : Insn_Size := Sz_32) is
   begin
      Rm_Base := R_Nil;
      SIB_Index := R_Nil;
      SIB_Scale := 0;
      Rm_Sym := Null_Symbol;
      Rm_Offset := 0;

      Rm_Opc_Reg := Opc;
      Rm_Opc_Sz := Opc_Sz;

      Rm_Reg := Reg;
      Rm_Sz := Sz;

      Gen_Rex_Mod_Rm;
   end Init_Modrm_Reg;

   --  Note: SZ is not relevant.
   procedure Init_Modrm_Sym (Sym : Symbol; Sz : Insn_Size; Opc_Reg : O_Reg) is
   begin
      Rm_Base := R_Nil;
      SIB_Index := R_Nil;
      SIB_Scale := 0;
      Rm_Sym := Sym;
      Rm_Offset := 0;

      Rm_Opc_Reg := Opc_Reg;
      Rm_Opc_Sz := Sz;

      Rm_Reg := R_Nil;
      Rm_Sz := Sz;

      Gen_Rex_Mod_Rm;
   end Init_Modrm_Sym;

   --  ModRM is a memory reference.
   procedure Init_Modrm_Mem (N : O_Enode; Sz : Insn_Size; Opc : O_Reg := R_Nil)
   is
      Reg : constant O_Reg := Get_Expr_Reg (N);
   begin
      Rm_Base := R_Nil;
      SIB_Index := R_Nil;
      Rm_Reg := R_Nil;
      Rm_Sz := Sz;

      Rm_Opc_Reg := Opc;
      Rm_Opc_Sz := Sz;

      if Sz = Sz_32h then
         Rm_Offset := 4;
      else
         Rm_Offset := 0;
      end if;
      SIB_Scale := 0;
      Rm_Sym := Null_Symbol;
      case Reg is
         when R_Mem
           | R_Imm
           | R_Eq
           | R_B_Off
           | R_B_I
           | R_I_Off
           | R_Sib =>
            Fill_Sib (N);
         when Regs_R64 =>
            Rm_Base := Reg;
         when R_Spill =>
            Rm_Base := R_Bp;
            Rm_Offset := Rm_Offset + Get_Spill_Info (N);
         when others =>
            Error_Emit ("init_modrm_mem: unhandled reg", N);
      end case;

      Gen_Rex_Mod_Rm;
   end Init_Modrm_Mem;

   procedure Init_Modrm_Expr
     (N : O_Enode; Sz : Insn_Size; Opc : O_Reg := R_Nil)
   is
      Reg : constant O_Reg := Get_Expr_Reg (N);
   begin
      case Reg is
         when Regs_R64
           | Regs_Pair
           | Regs_Xmm =>
            --  Destination is a register.
            Init_Modrm_Reg (Reg, Sz, Opc, Sz);
         when others =>
            --  Destination is an effective address.
            Init_Modrm_Mem (N, Sz, Opc);
      end case;
   end Init_Modrm_Expr;

   procedure Init_Modrm_Offset
     (Base : O_Reg; Off : Int32; Sz : Insn_Size; Opc : O_Reg := R_Nil) is
   begin
      SIB_Index := R_Nil;
      SIB_Scale := 0;
      Rm_Reg := R_Nil;
      Rm_Sym := Null_Symbol;
      Rm_Sz := Sz;

      Rm_Base := Base;

      Rm_Opc_Reg := Opc;
      Rm_Opc_Sz := Sz;

      if Sz = Sz_32h then
         Rm_Offset := Off + 4;
      else
         Rm_Offset := Off;
      end if;

      Gen_Rex_Mod_Rm;
   end Init_Modrm_Offset;

   --  Generate an R/M (+ SIB) byte.
   --  R is added to the R/M byte.
   procedure Gen_Mod_Rm_B (R : Byte) is
   begin
      if Rm_Reg /= R_Nil then
         --  Register: mod = 11, no memory access.
         pragma Assert (Rm_Base = R_Nil);
         pragma Assert (Rm_Sym = Null_Symbol);
         pragma Assert (Rm_Offset = 0);
         pragma Assert (SIB_Index = R_Nil);
         Gen_8 (2#11_000_000# + R + To_Reg (Rm_Reg, Rm_Sz));
         return;
      end if;

      if SIB_Index /= R_Nil or (Flags.M64 and Rm_Base = R_R12) then
         --  With SIB.
         if SIB_Index = R_Nil then
            SIB_Index := R_Sp;
         end if;
         if Rm_Base = R_Nil then
            --  No base (but index).  Use the special encoding with base=BP.
            Gen_8 (2#00_000_100# + R); --  mod=00, rm=SP -> disp32.
            Rm_Base := R_Bp;
            Gen_Sib;
            if Rm_Sym = Null_Symbol then
               Gen_32 (Unsigned_32 (To_Uns32 (Rm_Offset)));
            else
               pragma Assert (not Flags.M64);
               Gen_X86_32 (Rm_Sym, Integer_32 (Rm_Offset));
            end if;
         elsif Rm_Sym = Null_Symbol and Rm_Offset = 0
           and Rm_Base /= R_Bp and Rm_Base /= R_R13
         then
            --  No offset (only allowed if base is not BP).
            Gen_8 (2#00_000_100# + R);
            Gen_Sib;
         elsif Rm_Sym = Null_Symbol and Rm_Offset in -128 .. 127 then
            --  Disp8
            Gen_8 (2#01_000_100# + R);
            Gen_Sib;
            Gen_8 (Byte (To_Uns32 (Rm_Offset) and 16#Ff#));
         else
            --  Disp32
            Gen_8 (2#10_000_100# + R);
            Gen_Sib;
            if Rm_Sym = Null_Symbol then
               Gen_32 (Unsigned_32 (To_Uns32 (Rm_Offset)));
            else
               pragma Assert (not Flags.M64);
               Gen_X86_32 (Rm_Sym, Integer_32 (Rm_Offset));
            end if;
         end if;
      else
         case Rm_Base is
            when R_Sp =>
               --  It isn't possible to use SP as a base register without using
               --  an SIB encoding.
               raise Program_Error;
            when R_Nil =>
               --  There should be no case where the offset is negative.
               pragma Assert (Rm_Offset >= 0);
               --  Encode for disp32 (Mod=00, R/M=101) or RIP relative
               Gen_8 (2#00_000_101# + R);
               if Flags.M64 then
                  --  RIP relative
                  Gen_X86_Pc32 (Rm_Sym, Unsigned_32 (Rm_Offset));
               else
                  --  Disp32.
                  Gen_X86_32 (Rm_Sym, Integer_32 (Rm_Offset));
               end if;
            when R_Ax
              | R_Bx
              | R_Cx
              | R_Dx
              | R_Bp
              | R_Si
              | R_Di
              | R_R8 .. R_R11
              | R_R13 .. R_R15 =>
               if Rm_Offset = 0 and Rm_Sym = Null_Symbol
                 and Rm_Base /= R_Bp and Rm_Base /= R_R13
               then
                  --  No disp: use Mod=00 (not supported if base is BP or R13).
                  Gen_8 (2#00_000_000# + R + To_Reg64 (Rm_Base));
               elsif Rm_Sym = Null_Symbol
                 and Rm_Offset <= 127 and Rm_Offset >= -128
               then
                  --  Disp8 (Mod=01)
                  Gen_8 (2#01_000_000# + R + To_Reg64 (Rm_Base));
                  Gen_8 (Byte (To_Uns32 (Rm_Offset) and 16#Ff#));
               else
                  --  Disp32 (Mod=10)
                  Gen_8 (2#10_000_000# + R + To_Reg64 (Rm_Base));
                  if Rm_Sym = Null_Symbol then
                     Gen_32 (Unsigned_32 (To_Uns32 (Rm_Offset)));
                  else
                     pragma Assert (not Flags.M64);
                     Gen_X86_32 (Rm_Sym, Integer_32 (Rm_Offset));
                  end if;
               end if;
            when others =>
               raise Program_Error;
         end case;
      end if;
   end Gen_Mod_Rm_B;

   procedure Gen_Mod_Rm_Opc (R : Byte) is
   begin
      pragma Assert (Rm_Opc_Reg = R_Nil);
      Gen_Mod_Rm_B (R);
   end Gen_Mod_Rm_Opc;

   procedure Gen_Mod_Rm_Reg is
   begin
      pragma Assert (Rm_Opc_Reg /= R_Nil);
      Gen_Mod_Rm_B (To_Reg (Rm_Opc_Reg, Rm_Opc_Sz) * 8);
   end Gen_Mod_Rm_Reg;

   procedure Gen_Grp1_Insn (Op : Byte; Stmt : O_Enode; Sz : Insn_Size)
   is
      L : constant O_Enode := Get_Expr_Left (Stmt);
      R : constant O_Enode := Get_Expr_Right (Stmt);
      Lr : constant O_Reg := Get_Expr_Reg (L);
      Rr : constant O_Reg := Get_Expr_Reg (R);
   begin
      Start_Insn;
      case Rr is
         when R_Imm =>
            if Lr = R_Ax then
               --  Use compact encoding.
               if Sz = Sz_64 then
                  Gen_8 (Opc_Rex_W);
               end if;
               Gen_Insn_Sz (2#000_000_100# + Op, Sz);
               Gen_Imm (R, Sz);
            elsif Is_Imm8 (R, Sz) then
               Init_Modrm_Expr (L, Sz);
               Gen_Insn_Sz_S8 (16#80#, Sz);
               Gen_Mod_Rm_Opc (Op);
               Gen_Imm8 (R, Sz);
            else
               Init_Modrm_Expr (L, Sz);
               Gen_Insn_Sz (16#80#, Sz);
               Gen_Mod_Rm_Opc (Op);
               Gen_Imm (R, Sz);
            end if;
         when R_Mem
           | R_Spill
           | Regs_R64
           | Regs_Pair =>
            Init_Modrm_Expr (R, Sz, Lr);
            Gen_Insn_Sz (2#00_000_010# + Op, Sz);
            Gen_Mod_Rm_Reg;
         when others =>
            Error_Emit ("emit_op", Stmt);
      end case;
      End_Insn;
   end Gen_Grp1_Insn;

   --  Emit a one byte instruction.
   procedure Gen_1 (B : Byte) is
   begin
      Start_Insn;
      Gen_8 (B);
      End_Insn;
   end Gen_1;

   --  Emit a two byte instruction.
   procedure Gen_2 (B1, B2 : Byte) is
   begin
      Start_Insn;
      Gen_8 (B1);
      Gen_8 (B2);
      End_Insn;
   end Gen_2;

   --  Grp1 instructions have a mod/rm and an immediate value VAL.
   --  Mod/Rm must be initialized.
   procedure Gen_Insn_Grp1 (Opc2 : Byte; Val : Int32) is
   begin
      if Val in -128 .. 127 then
         case Rm_Sz is
            when Sz_8 =>
               Gen_8 (Opc_Grp1b_Rm_Imm8);
            when Sz_16 =>
               Gen_8 (Opc_Data16);
               Gen_8 (Opc_Grp1v_Rm_Imm8);
            when Sz_32
              | Sz_32l
              | Sz_32h
              | Sz_64 =>
               Gen_8 (Opc_Grp1v_Rm_Imm8);
         end case;
         Gen_Mod_Rm_Opc (Opc2);
         Gen_8 (Byte (To_Uns32 (Val) and 16#Ff#));
      else
         case Rm_Sz is
            when Sz_8 =>
               pragma Assert (False);
               null;
            when Sz_16 =>
               Gen_8 (Opc_Data16);
               Gen_8 (Opc_Grp1v_Rm_Imm32);
            when Sz_32
              | Sz_32l
              | Sz_32h
              | Sz_64 =>
               Gen_8 (Opc_Grp1v_Rm_Imm32);
         end case;
         Gen_Mod_Rm_Opc (Opc2);
         Gen_32 (Unsigned_32 (To_Uns32 (Val)));
      end if;
   end Gen_Insn_Grp1;

   procedure Gen_Cdq (Sz : Insn_Size) is
   begin
      Start_Insn;
      if Sz = Sz_64 then
         Gen_8 (Opc_Rex_W);
      end if;
      Gen_8 (Opc_Cdq);
      End_Insn;
   end Gen_Cdq;

   procedure Gen_Clear_Edx is
   begin
      --  Xorl edx, edx
      Gen_2 (Opc_Xorl_Rm_Reg, 2#11_010_010#);
   end Gen_Clear_Edx;

   procedure Gen_Grp3_Insn (Op : Byte; Val : O_Enode; Sz : Insn_Size) is
   begin
      Start_Insn;
      --  Unary Group 3 (test, not, neg...)
      Init_Modrm_Expr (Val, Sz);
      Gen_Insn_Sz (Opc_Grp3_Width, Sz);
      Gen_Mod_Rm_Opc (Op);
      End_Insn;
   end Gen_Grp3_Insn;

   procedure Gen_Grp3_Insn_Stmt (Op : Byte; Stmt : O_Enode; Sz : Insn_Size)
   is
   begin
      Gen_Grp3_Insn (Op, Get_Expr_Operand (Stmt), Sz);
   end Gen_Grp3_Insn_Stmt;

   procedure Emit_Load_Imm (Stmt : O_Enode; Sz : Insn_Size)
   is
      Tr : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      Start_Insn;
      --  TODO: handle 0 specially: use xor
      --  Mov immediate.
      case Sz is
         when Sz_8 =>
            Gen_Rex_B (Tr, Sz);
            Gen_8 (Opc_Movb_Imm_Reg + To_Reg32 (Tr, Sz));
            Gen_Imm (Stmt, Sz);
         when Sz_16 =>
            Gen_8 (Opc_Data16);
            Gen_8 (Opc_Movl_Imm_Reg + To_Reg32 (Tr, Sz));
            Gen_Imm (Stmt, Sz);
         when Sz_32
           | Sz_32l
           | Sz_32h =>
            Gen_Rex_B (Tr, Sz);
            Gen_8 (Opc_Movl_Imm_Reg + To_Reg32 (Tr, Sz));
            Gen_Imm (Stmt, Sz);
         when Sz_64 =>
            if Get_Expr_Kind (Stmt) = OE_Const then
               if Get_Expr_High (Stmt) = 0 then
                  Gen_Rex_B (Tr, Sz_32);
                  Gen_8 (Opc_Movl_Imm_Reg + To_Reg32 (Tr, Sz));
                  Gen_32 (Unsigned_32 (Get_Expr_Low (Stmt)));
               else
                  Gen_Rex_B (Tr, Sz_64);
                  Gen_8 (Opc_Movl_Imm_Reg + To_Reg32 (Tr, Sz));
                  Gen_32 (Unsigned_32 (Get_Expr_Low (Stmt)));
                  Gen_32 (Unsigned_32 (Get_Expr_High (Stmt)));
               end if;
            else
               Gen_Rex_B (Tr, Sz_64);
               Gen_8 (Opc_Movl_Imm_Reg + To_Reg32 (Tr, Sz));
               Gen_Imm_Addr (Stmt);
            end if;
      end case;
      End_Insn;
   end Emit_Load_Imm;

   function Mode_Fp_To_Mf (Mode : Mode_Fp) return Byte is
   begin
      case Mode is
         when Mode_F32 =>
            return 2#00_0#;
         when Mode_F64 =>
            return 2#10_0#;
      end case;
   end Mode_Fp_To_Mf;

   subtype Nat_Align is Natural range 0 .. 4;

   function Gen_Constant_Start (Log2sz : Nat_Align) return Symbol
   is
      Sym : Symbol;
   begin
      --  Write the constant in .rodata
      Set_Current_Section (Sect_Rodata);
      Gen_Pow_Align (Log2sz);
      Prealloc (2 ** Log2sz);
      Sym := Create_Local_Symbol;
      Set_Symbol_Pc (Sym, False);
      return Sym;
   end Gen_Constant_Start;

   function Gen_Constant_32 (Val : Unsigned_32) return Symbol
   is
      Sym : Symbol;
   begin
      Sym := Gen_Constant_Start (2);
      Gen_32 (Val);
      Set_Current_Section (Sect_Text);
      return Sym;
   end Gen_Constant_32;

   function Gen_Constant_64 (Lo, Hi : Unsigned_32) return Symbol
   is
      Sym : Symbol;
   begin
      Sym := Gen_Constant_Start (3);
      Gen_32 (Lo);
      Gen_32 (Hi);
      Set_Current_Section (Sect_Text);
      return Sym;
   end Gen_Constant_64;

   function Gen_Constant_128 (Lo, Hi : Unsigned_32) return Symbol
   is
      Sym : Symbol;
   begin
      Sym := Gen_Constant_Start (4);
      Gen_32 (Lo);
      Gen_32 (Hi);
      Gen_32 (Lo);
      Gen_32 (Hi);
      Set_Current_Section (Sect_Text);
      return Sym;
   end Gen_Constant_128;

   Xmm_Sign32_Sym : Symbol := Null_Symbol;
   Xmm_Sign64_Sym : Symbol := Null_Symbol;

   function Get_Xmm_Sign_Constant (Mode : Mode_Fp) return Symbol is
   begin
      case Mode is
         when Mode_F32 =>
            if Xmm_Sign32_Sym = Null_Symbol then
               Xmm_Sign32_Sym := Gen_Constant_128
                 (16#8000_0000#, 16#8000_0000#);
            end if;
            return Xmm_Sign32_Sym;
         when Mode_F64 =>
            if Xmm_Sign64_Sym = Null_Symbol then
               Xmm_Sign64_Sym := Gen_Constant_128
                 (0, 16#8000_0000#);
            end if;
            return Xmm_Sign64_Sym;
      end case;
   end Get_Xmm_Sign_Constant;

   Xmm_Mask32_Sym : Symbol := Null_Symbol;
   Xmm_Mask64_Sym : Symbol := Null_Symbol;

   function Get_Xmm_Mask_Constant (Mode : Mode_Fp) return Symbol is
   begin
      case Mode is
         when Mode_F32 =>
            if Xmm_Mask32_Sym = Null_Symbol then
               Xmm_Mask32_Sym := Gen_Constant_128
                 (16#7fff_ffff#, 16#7fff_ffff#);
            end if;
            return Xmm_Mask32_Sym;
         when Mode_F64 =>
            if Xmm_Mask64_Sym = Null_Symbol then
               Xmm_Mask64_Sym := Gen_Constant_128
                 (16#ffff_ffff#, 16#7fff_ffff#);
            end if;
            return Xmm_Mask64_Sym;
      end case;
   end Get_Xmm_Mask_Constant;

   procedure Gen_SSE_Prefix (Mode : Mode_Fp) is
   begin
      case Mode is
         when Mode_F32 =>
            Gen_8 (16#f3#);
         when Mode_F64 =>
            Gen_8 (16#f2#);
      end case;
   end Gen_SSE_Prefix;

   procedure Gen_SSE_Opc (Op : Byte) is
   begin
      Gen_8 (16#0f#, Op);
   end Gen_SSE_Opc;

   procedure Gen_SSE_D16_Opc (Mode : Mode_Fp; Opc : Byte) is
   begin
      case Mode is
         when Mode_F32 =>
            null;
         when Mode_F64 =>
            Gen_8 (Opc_Data16);
      end case;
      Gen_8 (16#0f#);
      Gen_8 (Opc);
   end Gen_SSE_D16_Opc;

   procedure Emit_Load_Fp (Stmt : O_Enode; Mode : Mode_Fp)
   is
      Sym : Symbol;
      R : O_Reg;
      Lo : constant Unsigned_32 := Unsigned_32 (Get_Expr_Low (Stmt));
   begin
      case Mode is
         when Mode_F32 =>
            Sym := Gen_Constant_32 (Lo);
         when Mode_F64 =>
            Sym := Gen_Constant_64 (Lo, Unsigned_32 (Get_Expr_High (Stmt)));
      end case;

      --  Load the constant.
      R := Get_Expr_Reg (Stmt);
      case R is
         when R_St0 =>
            Start_Insn;
            Gen_8 (2#11011_001# + Mode_Fp_To_Mf (Mode));
            Gen_8 (2#00_000_101#);
            Gen_X86_32 (Sym, 0);
            End_Insn;
         when Regs_Xmm =>
            Start_Insn;
            Gen_SSE_Prefix (Mode);
            Gen_SSE_Opc (Opc_Movsd_Xmm_M64);
            Gen_8 (2#00_000_101# + To_Reg_Xmm (R) * 2#1_000#);
            if Flags.M64 then
               --  RIP relative
               Gen_X86_Pc32 (Sym, 0);
            else
               --  Disp32.
               Gen_X86_32 (Sym, 0);
            end if;
            End_Insn;
         when others =>
            raise Program_Error;
      end case;
   end Emit_Load_Fp;

   procedure Emit_Load_Fp_Mem (Stmt : O_Enode; Mode : Mode_Fp)
   is
      Dest : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      if Dest in Regs_Xmm then
         Start_Insn;
         Gen_SSE_Prefix (Mode);
         Init_Modrm_Mem (Get_Expr_Operand (Stmt), Sz_Fp, Dest);
         Gen_SSE_Opc (Opc_Movsd_Xmm_M64);
         Gen_Mod_Rm_Reg;
         End_Insn;
      else
         Start_Insn;
         Init_Modrm_Mem (Get_Expr_Operand (Stmt), Sz_Fp);
         Gen_8 (2#11011_001# + Mode_Fp_To_Mf (Mode));
         Gen_Mod_Rm_Opc (2#000_000#);
         End_Insn;
      end if;
   end Emit_Load_Fp_Mem;

   procedure Emit_Load_Mem (Stmt : O_Enode; Sz : Insn_Size)
   is
      Tr  : constant O_Reg := Get_Expr_Reg (Stmt);
      Val : constant O_Enode := Get_Expr_Operand (Stmt);
   begin
      case Tr is
         when Regs_R64
           | Regs_Pair =>
            --  mov REG, OP
            Start_Insn;
            Init_Modrm_Mem (Val, Sz, Tr);
            Gen_Insn_Sz (Opc_Mov_Reg_Rm, Sz);
            Gen_Mod_Rm_Reg;
            End_Insn;
         when R_Eq =>
            --  Cmp OP, 1
            Start_Insn;
            Init_Modrm_Mem (Val, Sz);
            Gen_Insn_Grp1 (Opc2_Grp1_Cmp, 1);
            End_Insn;
         when others =>
            Error_Emit ("emit_load_mem", Stmt);
      end case;
   end Emit_Load_Mem;

   procedure Emit_Store (Stmt : O_Enode; Sz : Insn_Size)
   is
      T : constant O_Enode := Get_Assign_Target (Stmt);
      R : constant O_Enode := Get_Expr_Operand (Stmt);
      Tr : constant O_Reg := Get_Expr_Reg (T);
      Rr : constant O_Reg := Get_Expr_Reg (R);
      B : Byte;
   begin
      Start_Insn;
      case Rr is
         when R_Imm =>
            if False and (Tr in Regs_R64 or Tr in Regs_Pair) then
               B := 2#1011_1_000#;
               case Sz is
                  when Sz_8 =>
                     B := B and not 2#0000_1_000#;
                  when Sz_16 =>
                     Gen_8 (16#66#);
                  when Sz_32
                    | Sz_32l
                    | Sz_32h
                    | Sz_64 =>
                     null;
               end case;
               Gen_8 (B + To_Reg32 (Tr, Sz));
            else
               Init_Modrm_Mem (T, Sz);
               Gen_Insn_Sz (Opc_Mov_Rm_Imm, Sz);
               Gen_Mod_Rm_Opc (16#00#);
            end if;
            Gen_Imm (R, Sz);
         when Regs_R64
           | Regs_Pair =>
            Init_Modrm_Mem (T, Sz, Rr);
            Gen_Insn_Sz (Opc_Mov_Rm_Reg, Sz);
            Gen_Mod_Rm_Reg;
         when others =>
            Error_Emit ("emit_store", Stmt);
      end case;
      End_Insn;
   end Emit_Store;

   procedure Emit_Store_Fp (Stmt : O_Enode; Mode : Mode_Fp) is
   begin
      -- fstp
      Start_Insn;
      Init_Modrm_Mem (Get_Assign_Target (Stmt), Sz_Ptr);
      Gen_8 (2#11011_00_1# + Mode_Fp_To_Mf (Mode));
      Gen_Mod_Rm_Opc (2#011_000#);
      End_Insn;
   end Emit_Store_Fp;

   procedure Emit_Store_Xmm (Stmt : O_Enode; Mode : Mode_Fp) is
   begin
      --  movsd
      Start_Insn;
      Gen_SSE_Prefix (Mode);
      Init_Modrm_Mem (Get_Assign_Target (Stmt), Sz_Fp,
                      Get_Expr_Reg (Get_Expr_Operand (Stmt)));
      Gen_SSE_Opc (Opc_Movsd_M64_Xmm);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Store_Xmm;

   procedure Gen_Push_Pop_Reg (Opc : Byte; Reg : O_Reg; Sz : Insn_Size) is
   begin
      Start_Insn;
      if Reg in Regs_R8_R15 then
         Gen_8 (Opc_Rex_B);
      end if;
      Gen_8 (Opc + To_Reg32 (Reg, Sz));
      End_Insn;
   end Gen_Push_Pop_Reg;

   procedure Emit_Push (Val : O_Enode; Sz : Insn_Size)
   is
      R : constant O_Reg := Get_Expr_Reg (Val);
   begin
      case R is
         when R_Imm =>
            Start_Insn;
            if Is_Imm8 (Val, Sz) then
               Gen_8 (Opc_Push_Imm8);
               Gen_Imm8 (Val, Sz);
            else
               Gen_8 (Opc_Push_Imm);
               Gen_Imm (Val, Sz);
            end if;
            End_Insn;
         when Regs_R64
           | Regs_Pair =>
            Gen_Push_Pop_Reg (Opc_Push_Reg, R, Sz);
         when others =>
            Start_Insn;
            Init_Modrm_Expr (Val, Sz);
            Gen_8 (Opc_Grp5);
            Gen_Mod_Rm_Opc (Opc2_Grp5_Push_Rm);
            End_Insn;
      end case;
   end Emit_Push;

   procedure Emit_Subl_Sp_Imm (Len : Byte) is
   begin
      Start_Insn;
      Gen_Rex (Opc_Rex_W);
      Gen_8 (Opc_Grp1v_Rm_Imm8);
      Gen_8 (Opc2_Grp1_Sub + 2#11_000_100#);
      Gen_8 (Len);
      End_Insn;
   end Emit_Subl_Sp_Imm;

   procedure Emit_Addl_Sp_Imm (Len : Byte)
   is
      pragma Assert (not Flags.M64);
   begin
      Start_Insn;
      Gen_8 (Opc_Grp1v_Rm_Imm8);
      Gen_8 (Opc2_Grp1_Add + 2#11_000_100#);
      Gen_8 (Len);
      End_Insn;
   end Emit_Addl_Sp_Imm;

   procedure Emit_Push_Fp (Op : O_Enode; Mode : Mode_Fp)
   is
      Reg : constant O_Reg := Get_Expr_Reg (Op);
      Len : Byte;
   begin
      --  subl esp, val
      case Mode is
         when Mode_F32 =>
            Len := 4;
         when Mode_F64 =>
            Len := 8;
      end case;
      Emit_Subl_Sp_Imm (Len);

      if Reg = R_St0 then
         --  fstp st, (esp)
         Start_Insn;
         Gen_8 (2#11011_001# + Mode_Fp_To_Mf (Mode));
         Gen_8 (2#00_011_100#);  --  Modrm: SIB, no disp
         Gen_8 (2#00_100_100#);  --  SIB: SS=0, no index, base=esp
         End_Insn;
      else
         pragma Assert (Reg in Regs_Xmm);
         Start_Insn;
         Gen_SSE_Prefix (Mode);
         Gen_SSE_Opc (Opc_Movsd_M64_Xmm);
         Gen_8 (To_Reg_Xmm (Reg) * 8 + 2#00_000_100#);  --  Modrm: [--]
         Gen_8 (2#00_100_100#);  --  SIB: SS=0, no index, base=esp
         End_Insn;
      end if;
   end Emit_Push_Fp;

   function Prepare_Label (Label : O_Enode) return Symbol
   is
      Sym : Symbol;
   begin
      Sym := Get_Label_Symbol (Label);
      if Sym = Null_Symbol then
         Sym := Create_Local_Symbol;
         Set_Label_Symbol (Label, Sym);
      end if;
      return Sym;
   end Prepare_Label;

   procedure Emit_Jmp_T (Stmt : O_Enode; Reg : O_Reg)
   is
      Sym : Symbol;
      Val : Pc_Type;
      Opc : Byte;
   begin
      Sym := Prepare_Label (Get_Jump_Label (Stmt));
      Val := Get_Symbol_Value (Sym);
      Start_Insn;
      Opc := To_Cond (Reg);
      if Val = 0 then
         --  Assume long jmp.
         Gen_8 (Opc_0f);
         Gen_8 (Opc2_0f_Jcc + Opc);
         Gen_X86_Pc32 (Sym, 0);
      else
         if Val + 128 < Get_Current_Pc + 4 then
            --  Long jmp.
            Gen_8 (Opc_0f);
            Gen_8 (Opc2_0f_Jcc + Opc);
            Gen_32 (To_Unsigned_32 (Val - (Get_Current_Pc + 4)));
         else
            --  short jmp.
            Gen_8 (Opc_Jcc + Opc);
            Gen_8 (Byte (Val - (Get_Current_Pc + 1)));
         end if;
      end if;
      End_Insn;
   end Emit_Jmp_T;

   procedure Emit_Jmp (Stmt : O_Enode)
   is
      Sym : Symbol;
      Val : Pc_Type;
   begin
      Sym := Prepare_Label (Get_Jump_Label (Stmt));
      Val := Get_Symbol_Value (Sym);
      Start_Insn;
      if Val = 0 then
         --  Assume long jmp.
         Gen_8 (Opc_Jmp_Long);
         Gen_X86_Pc32 (Sym, 0);
      else
         if Val + 128 < Get_Current_Pc + 4 then
            --  Long jmp.
            Gen_8 (Opc_Jmp_Long);
            Gen_32 (To_Unsigned_32 (Val - (Get_Current_Pc + 4)));
         else
            --  short jmp.
            Gen_8 (Opc_Jmp_Short);
            Gen_8 (Byte ((Val - (Get_Current_Pc + 1)) and 16#Ff#));
         end if;
      end if;
      End_Insn;
   end Emit_Jmp;

   procedure Emit_Label (Stmt : O_Enode)
   is
      Sym : Symbol;
   begin
      Sym := Prepare_Label (Stmt);
      Set_Symbol_Pc (Sym, False);
   end Emit_Label;

   procedure Gen_Call (Sym : Symbol) is
   begin
      Start_Insn;
      Gen_8 (Opc_Call);
      Gen_X86_Pc32 (Sym, 0);
      End_Insn;
   end Gen_Call;

   procedure Emit_Stack_Adjust (Stmt : O_Enode)
   is
      Val : constant Int32 := Get_Stack_Adjust (Stmt);
   begin
      if Val > 0 then
         --  subl esp, val
         Emit_Subl_Sp_Imm (Byte (Val));
      elsif Val < 0 then
         Start_Insn;
         Init_Modrm_Reg (R_Sp, Sz_Ptr);
         Gen_Insn_Grp1 (Opc2_Grp1_Add, -Val);
         End_Insn;
      end if;
   end Emit_Stack_Adjust;

   procedure Emit_Call (Stmt : O_Enode)
   is
      use Ortho_Code.Decls;
      Subprg : constant O_Dnode := Get_Call_Subprg (Stmt);
      Sym : constant Symbol := Get_Decl_Symbol (Subprg);
      Mode : constant Mode_Type := Get_Expr_Mode (Stmt);
   begin
      Gen_Call (Sym);

      if Abi.Flag_Sse2 and then not Flags.M64 and then Mode in Mode_Fp then
         declare
            Sslot : constant Int32 := -Int32 (Cur_Subprg.Target.Fp_Slot);
         begin
            --  Move from St0 to Xmm0.
            --  fstp slot(%ebp)
            Start_Insn;
            Init_Modrm_Offset (R_Bp, Sslot, Sz_Fp);
            Gen_8 (2#11011_001# + Mode_Fp_To_Mf (Mode));
            Gen_Mod_Rm_Opc (2#00_011_000#);
            End_Insn;
            --  movsd slot(%ebp), %xmm0
            Start_Insn;
            Gen_SSE_Prefix (Mode);
            Init_Modrm_Offset (R_Bp, Sslot, Sz_Fp);
            Gen_SSE_Opc (Opc_Movsd_Xmm_M64);
            Gen_Mod_Rm_Opc (2#00_000_000#);
            End_Insn;
         end;
      end if;
   end Emit_Call;

   procedure Emit_Intrinsic (Stmt : O_Enode)
   is
      Op : constant Int32 := Get_Intrinsic_Operation (Stmt);
   begin
      --  Call sym
      Gen_Call (Intrinsics_Symbol (Op));

      --  addl esp, val
      Emit_Addl_Sp_Imm (16);
   end Emit_Intrinsic;

   procedure Emit_Setcc (Dest : O_Enode; Cond : O_Reg) is
   begin
      pragma Assert (Cond in Regs_Cc);
      Start_Insn;
      Init_Modrm_Expr (Dest, Sz_8);
      Gen_8 (Opc_0f);
      Gen_8 (Opc2_0f_Setcc + To_Cond (Cond));
      Gen_Mod_Rm_Opc (2#000_000#);
      End_Insn;
   end Emit_Setcc;

   procedure Emit_Setcc_Reg (Reg : O_Reg; Cond : O_Reg) is
   begin
      pragma Assert (Cond in Regs_Cc);
      Start_Insn;
      Gen_8 (Opc_0f);
      Gen_8 (Opc2_0f_Setcc + To_Cond (Cond));
      Gen_8 (2#11_000_000# + To_Reg32 (Reg, Sz_8));
      End_Insn;
   end Emit_Setcc_Reg;

   procedure Emit_Tst (Reg : O_Reg; Sz : Insn_Size) is
   begin
      Start_Insn;
      Init_Modrm_Reg (Reg, Sz, Reg, Sz);
      Gen_Insn_Sz (Opc_Test_Rm_Reg, Sz);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Tst;

   procedure Gen_Cmp_Imm (Reg : O_Reg; Val : Int32; Sz : Insn_Size) is
   begin
      Start_Insn;
      Init_Modrm_Reg (Reg, Sz);
      Gen_Insn_Grp1 (Opc2_Grp1_Cmp, Val);
      End_Insn;
   end Gen_Cmp_Imm;

   procedure Emit_Spill (Stmt : O_Enode; Sz : Insn_Size)
   is
      Expr : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg : constant O_Reg := Get_Expr_Reg (Expr);
   begin
      --  A reload is missing.
      pragma Assert (Reg /= R_Spill);
      Start_Insn;
      Init_Modrm_Mem (Stmt, Sz, Reg);
      Gen_Insn_Sz (Opc_Mov_Rm_Reg, Sz);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Spill;

   procedure Emit_Spill_Xmm (Stmt : O_Enode; Mode : Mode_Fp)
   is
      Expr : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg : constant O_Reg := Get_Expr_Reg (Expr);
   begin
      --  A reload is missing.
      pragma Assert (Reg in Regs_Xmm);
      --  movsd
      Start_Insn;
      Gen_SSE_Prefix (Mode);
      Init_Modrm_Mem (Stmt, Sz_Fp, Reg);
      Gen_SSE_Opc (Opc_Movsd_M64_Xmm);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Spill_Xmm;

   procedure Emit_Load (Reg : O_Reg; Val : O_Enode; Sz : Insn_Size)
   is
   begin
      Start_Insn;
      Init_Modrm_Expr (Val, Sz, Reg);
      Gen_Insn_Sz (Opc_Mov_Reg_Rm, Sz);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Load;

   procedure Emit_Lea (Stmt : O_Enode)
   is
      Reg : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      --  Hack: change the register to use the real address instead of it.
      Set_Expr_Reg (Stmt, R_Mem);

      Start_Insn;
      Init_Modrm_Mem (Stmt, Sz_Ptr, Reg);
      Gen_8 (Opc_Leal_Reg_Rm);
      Gen_Mod_Rm_Reg;
      End_Insn;

      --  Restore.
      Set_Expr_Reg (Stmt, Reg);
   end Emit_Lea;

   procedure Gen_Umul (Stmt : O_Enode; Sz : Insn_Size)
   is
   begin
      pragma Assert (Get_Expr_Reg (Get_Expr_Left (Stmt)) = R_Ax);
      Start_Insn;
      Init_Modrm_Expr (Get_Expr_Right (Stmt), Sz);
      Gen_Insn_Sz (Opc_Grp3_Width, Sz);
      Gen_Mod_Rm_Opc (Opc2_Grp3_Mul);
      End_Insn;
   end Gen_Umul;

   procedure Gen_Mul (Stmt : O_Enode; Sz : Insn_Size)
   is
      Reg : constant O_Reg := Get_Expr_Reg (Stmt);
      Right : constant O_Enode := Get_Expr_Right (Stmt);
      Reg_R : O_Reg;
   begin
      pragma Assert (Get_Expr_Reg (Get_Expr_Left (Stmt)) = Reg);
      Start_Insn;
      if Reg = R_Ax then
         Init_Modrm_Expr (Right, Sz);
         Gen_Insn_Sz (Opc_Grp3_Width, Sz);
         Gen_Mod_Rm_Opc (Opc2_Grp3_Mul);
      else
         Reg_R := Get_Expr_Reg (Right);
         case Reg_R is
            when R_Imm =>
               Init_Modrm_Reg (Reg, Sz, Reg, Sz);
               if Is_Imm8 (Right, Sz) then
                  Gen_8 (Opc_Imul_Reg_Rm_Imm8);
                  Gen_Mod_Rm_Reg;
                  Gen_Imm8 (Right, Sz);
               else
                  Gen_8 (Opc_Imul_Reg_Rm_Imm32);
                  Gen_Mod_Rm_Reg;
                  Gen_Imm (Right, Sz);
               end if;
            when R_Mem
              | R_Spill
              | Regs_R64 =>
               Init_Modrm_Expr (Right, Sz, Reg);
               Gen_8 (Opc_0f);
               Gen_8 (Opc2_0f_Imul);
               Gen_Mod_Rm_Reg;
            when others =>
               Error_Emit ("gen_mul", Stmt);
         end case;
      end if;
      End_Insn;
   end Gen_Mul;

   --  Do not trap if COND is true.
   procedure Gen_Ov_Check (Cond : O_Reg) is
   begin
      --  JXX +2
      Gen_2 (Opc_Jcc + To_Cond (Cond), 16#02#);
      --  INT 4 (overflow).
      Gen_2 (Opc_Int, 16#04#);
   end Gen_Ov_Check;

   procedure Gen_Into is
   begin
      if Flags.M64 then
         Gen_Ov_Check (R_No);
      else
         Gen_1 (Opc_Into);
      end if;
   end Gen_Into;

   procedure Emit_Abs (Val : O_Enode; Mode : Mode_Type)
   is
      Szl, Szh : Insn_Size;
      Pc_Jmp : Pc_Type;
   begin
      case Mode is
         when Mode_I32 =>
            Szh := Sz_32;
            Szl := Sz_32;
         when Mode_I64 =>
            if Flags.M64 then
               Szh := Sz_64;
               Szl := Sz_64;
            else
               Szh := Sz_32h;
               Szl := Sz_32l;
            end if;
         when others =>
            raise Program_Error;
      end case;
      Emit_Tst (Get_Expr_Reg (Val), Szh);
      --  JGE xxx (skip if positive).
      Gen_2 (Opc_Jcc + To_Cond (R_Sge), 0);
      Pc_Jmp := Get_Current_Pc;
      --  NEG
      Gen_Grp3_Insn (Opc2_Grp3_Neg, Val, Szl);
      if (not Flags.M64) and Mode = Mode_I64 then
         --  Propagate carry.
         --  Adc reg,0
         --  neg reg
         Start_Insn;
         Init_Modrm_Expr (Val, Sz_32h);
         Gen_Insn_Grp1 (Opc2_Grp1_Adc, 0);
         End_Insn;
         Gen_Grp3_Insn (Opc2_Grp3_Neg, Val, Sz_32h);
      end if;
      Gen_Into;
      Patch_8 (Pc_Jmp - 1, Unsigned_8 (Get_Current_Pc - Pc_Jmp));
   end Emit_Abs;

   procedure Gen_Alloca (Stmt : O_Enode)
   is
      Reg : constant O_Reg := Get_Expr_Reg (Get_Expr_Operand (Stmt));
   begin
      pragma Assert (Reg in Regs_R64);
      pragma Assert (Reg = Get_Expr_Reg (Stmt));
      --  Align stack on word.
      --  Add reg, (stack_boundary - 1)
      Start_Insn;
      Gen_Rex_B (Reg, Sz_Ptr);
      Gen_8 (Opc_Grp1v_Rm_Imm8);
      Gen_8 (Opc2_Grp1_Add or 2#11_000_000# or To_Reg32 (Reg));
      Gen_8 (Byte (X86.Flags.Stack_Boundary - 1));
      End_Insn;
      --  and reg, ~(stack_boundary - 1)
      Start_Insn;
      Gen_Rex_B (Reg, Sz_Ptr);
      Gen_8 (Opc_Grp1v_Rm_Imm32);
      Gen_8 (Opc2_Grp1_And or 2#11_000_000# or To_Reg32 (Reg));
      Gen_32 (not (X86.Flags.Stack_Boundary - 1));
      End_Insn;
      if X86.Flags.Flag_Alloca_Call then
         Gen_Call (Chkstk_Symbol);
      else
         --  subl esp, reg
         Start_Insn;
         Gen_Rex_B (Reg, Sz_Ptr);
         Gen_8 (Opc_Subl_Reg_Rm);
         Gen_8 (2#11_100_000# + To_Reg32 (Reg));
         End_Insn;
      end if;
      --  movl reg, esp
      Start_Insn;
      Gen_Rex_B (Reg, Sz_Ptr);
      Gen_8 (Opc_Mov_Rm_Reg + 1);
      Gen_8 (2#11_100_000# + To_Reg32 (Reg));
      End_Insn;
   end Gen_Alloca;

   --  Byte/word to long.
   procedure Gen_Movzx (Reg : Regs_R64; Op : O_Enode; Dst_Sz : Insn_Size) is
   begin
      Start_Insn;
      Init_Modrm_Expr (Op, Dst_Sz, Reg);
      Gen_8 (Opc_0f);
      case Get_Expr_Mode (Op) is
         when Mode_I8 | Mode_U8 | Mode_B2 =>
            Gen_8 (Opc2_0f_Movzx);
         when Mode_I16 | Mode_U16 =>
            Gen_8 (Opc2_0f_Movzx + 1);
         when others =>
            raise Program_Error;
      end case;
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Gen_Movzx;

   procedure Gen_Movsxd (Src : O_Reg; Dst : O_Reg) is
   begin
      Start_Insn;
      Init_Modrm_Reg (Src, Sz_64, Dst, Sz_64);
      Gen_8 (Opc_Movsxd_Reg_Rm);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Gen_Movsxd;

   procedure Emit_Move (Operand : O_Enode; Sz : Insn_Size; Reg : O_Reg) is
   begin
      --  mov REG, OP
      Start_Insn;
      Init_Modrm_Expr (Operand, Sz, Reg);
      Gen_Insn_Sz (Opc_Mov_Reg_Rm, Sz);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Move;

   procedure Emit_Move_Xmm (Operand : O_Enode; Mode : Mode_Fp; Reg : O_Reg) is
   begin
      --  movsd REG, OP
      Start_Insn;
      Gen_SSE_Prefix (Mode);
      Init_Modrm_Expr (Operand, Sz_Fp, Reg);
      Gen_SSE_Opc (Opc_Movsd_Xmm_M64);
      Gen_Mod_Rm_Reg;
      End_Insn;
   end Emit_Move_Xmm;

   --  Convert U32 to xx.
   procedure Gen_Conv_U32 (Stmt : O_Enode)
   is
      Op : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg_Op : constant O_Reg := Get_Expr_Reg (Op);
      Reg_Res : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      case Get_Expr_Mode (Stmt) is
         when Mode_I32 =>
            pragma Assert (Reg_Res in Regs_R32);
            if Reg_Op /= Reg_Res then
               Emit_Load (Reg_Res, Op, Sz_32);
            end if;
            Emit_Tst (Reg_Res, Sz_32);
            Gen_Ov_Check (R_Sge);
         when Mode_I64 =>
            if Flags.M64 then
               Emit_Move (Op, Sz_32, Reg_Res);
            else
               pragma Assert (Reg_Res = R_Edx_Eax);
               pragma Assert (Reg_Op = R_Ax);
               --  Clear edx.
               Gen_Clear_Edx;
            end if;
         when Mode_U8
           | Mode_B2 =>
            pragma Assert (Reg_Res in Regs_R32);
            if Reg_Op /= Reg_Res then
               Emit_Load (Reg_Res, Op, Sz_32);
            end if;
            --  cmpl VAL, 0xff
            Start_Insn;
            Init_Modrm_Expr (Op, Sz_32);
            Gen_8 (Opc_Grp1v_Rm_Imm32);
            Gen_Mod_Rm_Opc (Opc2_Grp1_Cmp);
            Gen_32 (16#00_00_00_Ff#);
            End_Insn;
            Gen_Ov_Check (R_Ule);
         when others =>
            Error_Emit ("gen_conv_u32", Stmt);
      end case;
   end Gen_Conv_U32;

   --  Convert I32 to xxx
   procedure Gen_Conv_I32 (Stmt : O_Enode)
   is
      Op : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg_Op : constant O_Reg := Get_Expr_Reg (Op);
      Reg_Res : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      case Get_Expr_Mode (Stmt) is
         when Mode_I64 =>
            if Flags.M64 then
               Gen_Movsxd (Reg_Op, Reg_Res);
            else
               pragma Assert (Reg_Res = R_Edx_Eax);
               pragma Assert (Reg_Op = R_Ax);
               Gen_Cdq (Sz_32);
            end if;
         when Mode_U32 =>
            pragma Assert (Reg_Res in Regs_R32);
            if Reg_Op /= Reg_Res then
               Emit_Load (Reg_Res, Op, Sz_32);
            end if;
            Emit_Tst (Reg_Res, Sz_32);
            Gen_Ov_Check (R_Sge);
         when Mode_B2 =>
            if Reg_Op /= Reg_Res then
               Emit_Load (Reg_Res, Op, Sz_32);
            end if;
            Gen_Cmp_Imm (Reg_Res, 1, Sz_32);
            Gen_Ov_Check (R_Ule);
         when Mode_U8 =>
            if Reg_Op /= Reg_Res then
               Emit_Load (Reg_Res, Op, Sz_32);
            end if;
            Gen_Cmp_Imm (Reg_Res, 16#Ff#, Sz_32);
            Gen_Ov_Check (R_Ule);
         when Mode_F64 =>
            if Reg_Res in Regs_Xmm then
               --  cvtsi2sd
               Gen_SSE_Prefix (Mode_F64);
               Init_Modrm_Expr (Op, Sz_32, Reg_Res);
               Gen_SSE_Opc (Opc_Cvtsi2sd_Xmm_Rm);
               Gen_Mod_Rm_Reg;
               End_Insn;
            else
               Emit_Push (Op, Sz_32);
               --  fild (%esp)
               Start_Insn;
               Gen_8 (2#11011_011#);
               Gen_8 (2#00_000_100#);
               Gen_8 (2#00_100_100#);
               End_Insn;
               --  addl %esp, 4
               Emit_Addl_Sp_Imm (4);
            end if;
         when others =>
            Error_Emit ("gen_conv_i32", Stmt);
      end case;
   end Gen_Conv_I32;

   --  Convert U8 to xxx
   procedure Gen_Conv_U8 (Stmt : O_Enode)
   is
      Mode : constant Mode_Type := Get_Expr_Mode (Stmt);
      Op : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg_Res : constant O_Reg := Get_Expr_Reg (Stmt);
      Reg_Op : constant O_Reg := Get_Expr_Reg (Op);
   begin
      case Mode is
         when Mode_U32
           | Mode_I32
           | Mode_U16
           | Mode_I16 =>
            pragma Assert (Reg_Res in Regs_R64);
            Gen_Movzx (Reg_Res, Op, Int_Mode_To_Size (Mode));
         when Mode_I64
           | Mode_U64 =>
            if Flags.M64 then
               Gen_Movzx (Reg_Res, Op, Sz_64);
            else
               pragma Assert (Reg_Res = R_Edx_Eax);
               pragma Assert (Reg_Op = R_Ax);
               Gen_Movzx (R_Ax, Op, Sz_32);
               --  Sign-extend, but we know the sign is positive.
               Gen_Cdq (Sz_32);
            end if;
         when others =>
            Error_Emit ("gen_conv_U8", Stmt);
      end case;
   end Gen_Conv_U8;

   --  Convert B2 to xxx
   procedure Gen_Conv_B2 (Stmt : O_Enode)
   is
      Mode : constant Mode_Type := Get_Expr_Mode (Stmt);
      Op : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg_Op : constant O_Reg := Get_Expr_Reg (Op);
      Reg_Res : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      case Mode is
         when Mode_U32
           | Mode_I32
           | Mode_U16
           | Mode_I16 =>
            pragma Assert (Reg_Res in Regs_R64);
            Gen_Movzx (Reg_Res, Op, Int_Mode_To_Size (Mode));
         when Mode_I64 =>
            if Flags.M64 then
               Gen_Movzx (Reg_Res, Op, Sz_64);
            else
               pragma Assert (Reg_Res = R_Edx_Eax);
               pragma Assert (Reg_Op = R_Ax);
               Gen_Movzx (R_Ax, Op, Sz_32);
               --  Sign-extend, but we know the sign is positive.
               Gen_Cdq (Sz_32);
            end if;
         when others =>
            Error_Emit ("gen_conv_B2", Stmt);
      end case;
   end Gen_Conv_B2;

   --  Convert I64 to xxx
   procedure Gen_Conv_I64 (Stmt : O_Enode)
   is
      Mode : constant Mode_Type := Get_Expr_Mode (Stmt);
      Op : constant O_Enode := Get_Expr_Operand (Stmt);
      Reg_Op : constant O_Reg := Get_Expr_Reg (Op);
      Reg_Res : constant O_Reg := Get_Expr_Reg (Stmt);
   begin
      case Mode is
         when Mode_I32 =>
            if Flags.M64 then
               --  movsxd src, dst
               Gen_Movsxd (Reg_Op, Reg_Res);
               --  cmp src,dst
               Start_Insn;
               Init_Modrm_Reg (Reg_Op, Sz_64, Reg_Res, Sz_64);
               Gen_8 (Opc_Cmpl_Rm_Reg);
               Gen_Mod_Rm_Reg;
               End_Insn;
            else
               pragma Assert (Reg_Op = R_Edx_Eax);
               pragma Assert (Reg_Res = R_Ax);
               --  move dx to reg_helper
               Start_Insn;
               Gen_8 (Opc_Mov_Rm_Reg + 1);
               Gen_8 (2#11_010_000# + To_Reg32 (Reg_Helper));
               End_Insn;
               --  Sign extend eax.
               Gen_Cdq (Sz_32);
               --  cmp reg_helper, dx
               Start_Insn;
               Gen_8 (Opc_Cmpl_Rm_Reg);
               Gen_8 (2#11_010_000# + To_Reg32 (Reg_Helper));
               End_Insn;
            end if;
            --  Overflow if extended value is different from initial value.
            Gen_Ov_Check (R_Eq);
         when Mode_U8
           | Mode_B2 =>
            declare
               Ubound : Int32;
            begin
               if Mode = Mode_B2 then
                  Ubound := 1;
               else
                  Ubound := 16#ff#;
               end if;

               if Flags.M64 then
                  Emit_Load (Reg_Res, Op, Sz_64);
                  Start_Insn;
                  Init_Modrm_Reg (Reg_Res, Sz_64);
                  Gen_Insn_Grp1 (Opc2_Grp1_Cmp, Ubound);
                  End_Insn;
               else
                  pragma Assert (Reg_Op in Regs_Pair);
                  --  Check MSB = 0
                  Emit_Tst (Reg_Op, Sz_32h);
                  Gen_Ov_Check (R_Eq);
                  --  Check LSB <= 255 (U8) or LSB <= 1 (B2)
                  if Reg_Op /= Reg_Res then
                     --  Move reg_op -> reg_res
                     --  FIXME: factorize with OE_Mov.
                     Start_Insn;
                     Init_Modrm_Reg (Reg_Op, Sz_32l, Reg_Res);
                     Gen_Insn_Sz (Opc_Mov_Reg_Rm, Sz_32);
                     Gen_Mod_Rm_Reg;
                     End_Insn;
                  end if;
                  Gen_Cmp_Imm (Reg_Res, Ubound, Sz_32);
               end if;
            end;
            Gen_Ov_Check (R_Ule);