/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/yosys.h" #include "kernel/macc.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct MaccmapWorker { std::vector> bits; RTLIL::Module *module; int width; MaccmapWorker(RTLIL::Module *module, int width) : module(module), width(width) { bits.resize(width); } void add(RTLIL::SigBit bit, int position) { if (position >= width || bit == State::S0) return; if (bits.at(position).count(bit)) { bits.at(position).erase(bit); add(bit, position+1); } else { bits.at(position).insert(bit); } } void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract) { a.extend_u0(width, is_signed); if (do_subtract) { a = module->Not(NEW_ID, a); add(State::S1, 0); } for (int i = 0; i < width; i++) add(a[i], i); } void add(RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract) { if (GetSize(a) < GetSize(b)) std::swap(a, b); a.extend_u0(width, is_signed); if (GetSize(b) > width) b.extend_u0(width, is_signed); for (int i = 0; i < GetSize(b); i++) if (is_signed && i+1 == GetSize(b)) { a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract); } else { add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); a = {a.extract(0, width-1), State::S0}; } } void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2) { int start_index = 0, stop_index = GetSize(in1); while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0) start_index++; while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0) stop_index--; if (start_index == stop_index) { out1 = RTLIL::SigSpec(0, GetSize(in1)); out2 = RTLIL::SigSpec(0, GetSize(in1)); } else { RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, GetSize(in1)-stop_index); in1 = in1.extract(start_index, stop_index-start_index); in2 = in2.extract(start_index, stop_index-start_index); in3 = in3.extract(start_index, stop_index-start_index); int width = GetSize(in1); RTLIL::Wire *w1 = module->addWire(NEW_ID, width); RTLIL::Wire *w2 = module->addWire(NEW_ID, width); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa)); cell->setParam(ID::WIDTH, width); cell->setPort(ID::A, in1); cell->setPort(ID::B, in2); cell->setPort(ID::C, in3); cell->setPort(ID::Y, w1); cell->setPort(ID::X, w2); out1 = {out_zeros_msb, w1, out_zeros_lsb}; out2 = {out_zeros_msb, w2, out_zeros_lsb}; } } int tree_bit_slots(int n) { #if 0 int retval = 1; while (n > 2) { retval += n / 3; n = 2*(n / 3) + (n % 3); } return retval; #else return max(n - 1, 0); #endif } RTLIL::SigSpec synth() { std::vector summands; std::vector tree_sum_bits; int unique_tree_bits = 0; int count_tree_words = 0; while (1) { RTLIL::SigSpec summand(0, width); bool got_data_bits = false; for (int i = 0; i < width; i++) if (!bits.at(i).empty()) { auto it = bits.at(i).begin(); summand[i] = *it; bits.at(i).erase(it); got_data_bits = true; } if (!got_data_bits) break; summands.push_back(summand); while (1) { int free_bit_slots = tree_bit_slots(GetSize(summands)) - GetSize(tree_sum_bits); int max_depth = 0, max_position = 0; for (int i = 0; i < width; i++) if (max_depth <= GetSize(bits.at(i))) { max_depth = GetSize(bits.at(i)); max_position = i; } if (max_depth == 0 || max_position > 4) break; int required_bits = 0; for (int i = 0; i <= max_position; i++) if (GetSize(bits.at(i)) == max_depth) required_bits += 1 << i; if (required_bits > free_bit_slots) break; for (int i = 0; i <= max_position; i++) if (GetSize(bits.at(i)) == max_depth) { auto it = bits.at(i).begin(); RTLIL::SigBit bit = *it; for (int k = 0; k < (1 << i); k++, free_bit_slots--) tree_sum_bits.push_back(bit); bits.at(i).erase(it); unique_tree_bits++; } count_tree_words++; } } if (!tree_sum_bits.empty()) log(" packed %d (%d) bits / %d words into adder tree\n", GetSize(tree_sum_bits), unique_tree_bits, count_tree_words); if (GetSize(summands) == 0) { log_assert(tree_sum_bits.empty()); return RTLIL::SigSpec(0, width); } if (GetSize(summands) == 1) { log_assert(tree_sum_bits.empty()); return summands.front(); } while (GetSize(summands) > 2) { std::vector new_summands; for (int i = 0; i < GetSize(summands); i += 3) if (i+2 < GetSize(summands)) { RTLIL::SigSpec in1 = summands[i]; RTLIL::SigSpec in2 = summands[i+1]; RTLIL::SigSpec in3 = summands[i+2]; RTLIL::SigSpec out1, out2; fulladd(in1, in2, in3, out1, out2); RTLIL::SigBit extra_bit = State::S0; if (!tree_sum_bits.empty()) { extra_bit = tree_sum_bits.back(); tree_sum_bits.pop_back(); } new_summands.push_back(out1); new_summands.push_back({out2.extract(0, width-1), extra_bit}); } else { new_summands.push_back(summands[i]); i -= 2; } summands.swap(new_summands); } RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu)); c->setPort(ID::A, summands.front()); c->setPort(ID::B, summands.back()); c->setPort(ID::CI, State::S0); c->setPort(ID::BI, State::S0); c->setPort(ID::Y, module->addWire(NEW_ID, width)); c->setPort(ID::X, module->addWire(NEW_ID, width)); c->setPort(ID::CO, module->addWire(NEW_ID, width)); c->fixup_parameters(); if (!tree_sum_bits.empty()) { c->setPort(ID::CI, tree_sum_bits.back()); tree_sum_bits.pop_back(); } log_assert(tree_sum_bits.empty()); return c->getPort(ID::Y); } }; PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false); void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) { int width = GetSize(cell->getPort(ID::Y)); Macc macc; macc.from_cell(cell); RTLIL::SigSpec all_input_bits; all_input_bits.append(cell->getPort(ID::A)); all_input_bits.append(cell->getPort(ID::B)); if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) { module->connect(cell->getPort(ID::Y), RTLIL::SigSpec(RTLIL::Sx, width)); return; } for (auto &port : macc.ports) if (GetSize(port.in_b) == 0) log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), GetSize(port.in_a), port.is_signed ? "signed" : "unsigned"); else log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b), GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned"); if (GetSize(macc.bit_ports) != 0) log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), GetSize(macc.bit_ports)); if (unmap) { typedef std::pair summand_t; std::vector summands; for (auto &port : macc.ports) { summand_t this_summand; if (GetSize(port.in_b)) { this_summand.first = module->addWire(NEW_ID, width); module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed); } else if (GetSize(port.in_a) != width) { this_summand.first = module->addWire(NEW_ID, width); module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed); } else { this_summand.first = port.in_a; } this_summand.second = port.do_subtract; summands.push_back(this_summand); } for (auto &bit : macc.bit_ports) summands.push_back(summand_t(bit, false)); if (GetSize(summands) == 0) summands.push_back(summand_t(RTLIL::SigSpec(0, width), false)); while (GetSize(summands) > 1) { std::vector new_summands; for (int i = 0; i < GetSize(summands); i += 2) { if (i+1 < GetSize(summands)) { summand_t this_summand; this_summand.first = module->addWire(NEW_ID, width); this_summand.second = summands[i].second && summands[i+1].second; if (summands[i].second == summands[i+1].second) module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); else if (summands[i].second) module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first); else if (summands[i+1].second) module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); else log_abort(); new_summands.push_back(this_summand); } else new_summands.push_back(summands[i]); } summands.swap(new_summands); } if (summands.front().second) module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y)); else module->connect(cell->getPort(ID::Y), summands.front().first); } else { MaccmapWorker worker(module, width); for (auto &port : macc.ports) if (GetSize(port.in_b) == 0) worker.add(port.in_a, port.is_signed, port.do_subtract); else worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract); for (auto &bit : macc.bit_ports) worker.add(bit, 0); module->connect(cell->getPort(ID::Y), worker.synth()); } } YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN struct MaccmapPass : public Pass { MaccmapPass() : Pass("maccmap", "mapping macc cells") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|--
/*
             LUFA Library
     Copyright (C) Dean Camera, 2017.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/

/*
  Copyright 2017  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, distribute, and sell this
  software and its documentation for any purpose is hereby granted
  without fee, provided that the above copyright notice appear in
  all copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaims all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

/** \file
 *
 *  Main source file for the GenericHID demo. This file contains the main tasks of
 *  the demo and is responsible for the initial application hardware configuration.
 */

#include "GenericHID.h"

/** Buffer to hold the previously generated HID report, for comparison purposes inside the HID class driver. */
static uint8_t PrevHIDReportBuffer[GENERIC_REPORT_SIZE];

/** LUFA HID Class driver interface configuration and state information. This structure is
 *  passed to all HID Class driver functions, so that multiple instances of the same class
 *  within a device can be differentiated from one another.
 */
USB_ClassInfo_HID_Device_t Generic_HID_Interface =
	{
		.Config =
			{
				.InterfaceNumber              = INTERFACE_ID_GenericHID,
				.ReportINEndpoint             =
					{
						.Address              = GENERIC_IN_EPADDR,
						.Size                 = GENERIC_EPSIZE,
						.Banks                = 1,
					},
				.PrevReportINBuffer           = PrevHIDReportBuffer,
				.PrevReportINBufferSize       = sizeof(PrevHIDReportBuffer),
			},
	};


/** Main program entry point. This routine contains the overall program flow, including initial
 *  setup of all components and the main program loop.
 */
int main(void)
{
	SetupHardware();

	LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
	GlobalInterruptEnable();

	for (;;)
	{
		HID_Device_USBTask(&Generic_HID_Interface);
		USB_USBTask();
	}
}

/** Configures the board hardware and chip peripherals for the demo's functionality. */
void SetupHardware(void)
{
#if (ARCH == ARCH_AVR8)
	/* Disable watchdog if enabled by bootloader/fuses */
	MCUSR &= ~(1 << WDRF);
	wdt_disable();

	/* Disable clock division */
	clock_prescale_set(clock_div_1);
#elif (ARCH == ARCH_XMEGA)
	/* Start the PLL to multiply the 2MHz RC oscillator to 32MHz and switch the CPU core to run from it */
	XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, F_CPU);
	XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL);

	/* Start the 32MHz internal RC oscillator and start the DFLL to increase it to 48MHz using the USB SOF as a reference */
	XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ);
	XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, F_USB);

	PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
#endif

	/* Hardware Initialization */
	LEDs_Init();
	USB_Init();
}

/** Event handler for the library USB Connection event. */
void EVENT_USB_Device_Connect(void)
{
	LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING);
}

/** Event handler for the library USB Disconnection event. */
void EVENT_USB_Device_Disconnect(void)
{
	LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
}

/** Event handler for the library USB Configuration Changed event. */
void EVENT_USB_Device_ConfigurationChanged(void)
{
	bool ConfigSuccess = true;

	ConfigSuccess &= HID_Device_ConfigureEndpoints(&Generic_HID_Interface);

	USB_Device_EnableSOFEvents();

	LEDs_SetAllLEDs(ConfigSuccess ? LEDMASK_USB_READY : LEDMASK_USB_ERROR);
}

/** Event handler for the library USB Control Request reception event. */
void EVENT_USB_Device_ControlRequest(void)
{
	HID_Device_ProcessControlRequest(&Generic_HID_Interface);
}

/** Event handler for the USB device Start Of Frame event. */
void EVENT_USB_Device_StartOfFrame(void)
{
	HID_Device_MillisecondElapsed(&Generic_HID_Interface);
}

/** HID class driver callback function for the creation of HID reports to the host.
 *
 *  \param[in]     HIDInterfaceInfo  Pointer to the HID class interface configuration structure being referenced
 *  \param[in,out] ReportID    Report ID requested by the host if non-zero, otherwise callback should set to the generated report ID
 *  \param[in]     ReportType  Type of the report to create, either HID_REPORT_ITEM_In or HID_REPORT_ITEM_Feature
 *  \param[out]    ReportData  Pointer to a buffer where the created report should be stored
 *  \param[out]    ReportSize  Number of bytes written in the report (or zero if no report is to be sent)
 *
 *  \return Boolean \c true to force the sending of the report, \c false to let the library determine if it needs to be sent
 */
bool CALLBACK_HID_Device_CreateHIDReport(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo,
                                         uint8_t* const ReportID,
                                         const uint8_t ReportType,
                                         void* ReportData,
                                         uint16_t* const ReportSize)
{
	uint8_t* Data        = (uint8_t*)ReportData;
	uint8_t  CurrLEDMask = LEDs_GetLEDs();

	Data[0] = ((CurrLEDMask & LEDS_LED1) ? 1 : 0);
	Data[1] = ((CurrLEDMask & LEDS_LED2) ? 1 : 0);
	Data[2] = ((CurrLEDMask & LEDS_LED3) ? 1 : 0);
	Data[3] = ((CurrLEDMask & LEDS_LED4) ? 1 : 0);

	*ReportSize = GENERIC_REPORT_SIZE;
	return false;
}

/** HID class driver callback function for the processing of HID reports from the host.
 *
 *  \param[in] HIDInterfaceInfo  Pointer to the HID class interface configuration structure being referenced
 *  \param[in] ReportID    Report ID of the received report from the host
 *  \param[in] ReportType  The type of report that the host has sent, either HID_REPORT_ITEM_Out or HID_REPORT_ITEM_Feature
 *  \param[in] ReportData  Pointer to a buffer where the received report has been stored
 *  \param[in] ReportSize  Size in bytes of the received HID report
 */
void CALLBACK_HID_Device_ProcessHIDReport(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo,
                                          const uint8_t ReportID,
                                          const uint8_t ReportType,
                                          const void* ReportData,
                                          const uint16_t ReportSize)
{
	uint8_t* Data       = (uint8_t*)ReportData;
	uint8_t  NewLEDMask = LEDS_NO_LEDS;

	if (Data[0])
	  NewLEDMask |= LEDS_LED1;

	if (Data[1])
	  NewLEDMask |= LEDS_LED2;

	if (Data[2])
	  NewLEDMask |= LEDS_LED3;

	if (Data[3])
	  NewLEDMask |= LEDS_LED4;

	LEDs_SetAllLEDs(NewLEDMask);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-23 14:01:34 +0000