/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/consteval.h" #include "kernel/log.h" #include #include #include #include static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) { RTLIL::SigSpec lvalue; for (auto sync : proc->syncs) for (auto &action : sync->actions) if (action.first.size() > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; } for (auto sync : proc->syncs) { RTLIL::SigSpec this_lvalue; for (auto &action : sync->actions) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); if (common_sig.size() > 0) lvalue = common_sig; } return lvalue; } static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map> &async_rules, RTLIL::Process *proc) { RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); for (auto &it : async_rules) { RTLIL::SigSpec sync_value = it.first; RTLIL::SigSpec sync_value_inv; RTLIL::SigSpec sync_high_signals; RTLIL::SigSpec sync_low_signals; for (auto &it2 : it.second) if (it2->type == RTLIL::SyncType::ST0) sync_low_signals.append(it2->signal); else if (it2->type == RTLIL::SyncType::ST1) sync_high_signals.append(it2->signal); else log_abort(); if (sync_low_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } if (sync_low_signals.size() > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); sync_high_signals.append(cell->connections["\\Y"]); mod->add(cell); } if (sync_high_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cel

#ifndef SUSPEND_H
#define SUSPEND_H

#include <stdint.h>
#include <stdbool.h>

void suspend_idle(uint8_t timeout);
void suspend_power_down(void);
bool suspend_wakeup_condition(void);
void suspend_wakeup_init(void);

void suspend_wakeup_init_user(void);
void suspend_wakeup_init_kb(void);
void suspend_power_down_user(void);
void suspend_power_down_kb(void);

#endif

sig.replace(action.first, action.second, &rstval); sync_level = sync; } else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { if (sync_edge != NULL && sync_edge != sync) log_error("Multiple edge sensitive events found for this signal!\n"); sig.replace(action.first, action.second, &insig); sync_edge = sync; } else if (sync->type == RTLIL::SyncType::STa) { if (sync_always != NULL && sync_always != sync) log_error("Multiple always events found for this signal!\n"); sig.replace(action.first, action.second, &insig); sync_always = sync; } else { log_error("Event with any-edge sensitivity found for this signal!\n"); } action.first.remove2(sig, &action.second); } if (many_async_rules.size() > 0) { many_async_rules[rstval].insert(sync_level); if (many_async_rules.size() == 1) { sync_level = new RTLIL::SyncRule; sync_level->type = RTLIL::SyncType::ST1; sync_level->signal = mod->addWire(NEW_ID); sync_level->actions.push_back(RTLIL::SigSig(sig, rstval)); free_sync_level = true; RTLIL::SigSpec inputs, compare; for (auto &it : many_async_rules[rstval]) { inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } assert(inputs.size() == compare.size()); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; cell->connections["\\Y"] = sync_level->signal; mod->add(cell); many_async_rules.clear(); } else { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } } ce.assign_map.apply(insig); ce.assign_map.apply(rstval); ce.assign_map.apply(sig); if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } if (sync_always) { if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); mod->connections.push_back(RTLIL::SigSig(sig, insig)); continue; } if (!sync_edge) log_error("Missing edge-sensitive event for this signal!\n"); if (many_async_rules.size() > 0) { log("WARNING: Complex async reset for dff `%s'.\n", log_signal(sig)); gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc); } else if (!rstval.is_fully_const() && !ce.eval(rstval)) { log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval)); gen_dffsr(mod, insig, rstval, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level->signal, proc); } else gen_dff(mod, insig, rstval.chunks()[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); if (free_sync_level) delete sync_level; } } struct ProcDffPass : public Pass { ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" proc_dff [selection]\n"); log("\n"); log("This pass identifies flip-flops in the processes and converts them to\n"); log("d-type flip-flop cells.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing PROC_DFF pass (convert process syncs to FFs).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) { ConstEval ce(mod_it.second); for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) proc_dff(mod_it.second, proc_it.second, ce); } } } ProcDffPass;