From 7c57ad3858b31aa714d90a14360254289990782c Mon Sep 17 00:00:00 2001 From: Dean Camera Date: Tue, 13 Aug 2013 21:30:34 +0200 Subject: Fix XMEGA TWI driver indentation and style to conform to the rest of the LUFA codebase. --- LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.c | 135 ++++++++++++++---------------- LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.h | 72 ++++++++-------- 2 files changed, 103 insertions(+), 104 deletions(-) (limited to 'LUFA/Drivers') diff --git a/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.c b/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.c index 81fbd0784..e5a5529b2 100644 --- a/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.c +++ b/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.c @@ -34,83 +34,77 @@ #define __INCLUDE_FROM_TWI_C #include "../TWI.h" -static inline bool bitmask_is_set(uint8_t byte, uint8_t mask) { - return (byte & mask) == mask; -} - -uint8_t TWI_StartTransmission(TWI_t *twi, +uint8_t TWI_StartTransmission(TWI_t* const TWI, const uint8_t SlaveAddress, const uint8_t TimeoutMS) { - uint16_t TimeoutRemaining; - - twi->MASTER.ADDR = SlaveAddress; - - TimeoutRemaining = (TimeoutMS * 100); - while (TimeoutRemaining) - { - uint8_t status = twi->MASTER.STATUS; - if (bitmask_is_set(status, TWI_MASTER_WIF_bm | TWI_MASTER_ARBLOST_bm)) - { - // Case 1: Arbitration lost. Try again. (or error) - twi->MASTER.ADDR = SlaveAddress; - } - else if (bitmask_is_set(status, TWI_MASTER_WIF_bm | TWI_MASTER_RXACK_bm)) - { - // Case 2: No response from slave. - // We need to release the bus. - TWI_StopTransmission(twi); - return TWI_ERROR_SlaveResponseTimeout; - } - else if (status & TWI_MASTER_WIF_bm) - { - // Case 3: Slave ACK the Write. Ready! - return TWI_ERROR_NoError; - } - else if (status & TWI_MASTER_RIF_bm) - { - // Case 4: Slave ACK the Read. Ready! (a byte will be read) - return TWI_ERROR_NoError; - } - // Still waiting.. - _delay_us(10); - TimeoutRemaining--; - } - - if (!(TimeoutRemaining)) { - if (twi->MASTER.STATUS & TWI_MASTER_CLKHOLD_bm) { - // Release the bus if we're holding it. - TWI_StopTransmission(twi); - } - } - return TWI_ERROR_BusCaptureTimeout; + uint16_t TimeoutRemaining; + + TWI->MASTER.ADDR = SlaveAddress; + + TimeoutRemaining = (TimeoutMS * 100); + while (TimeoutRemaining) + { + uint8_t status = TWI->MASTER.STATUS; + + if ((status & (TWI_MASTER_WIF_bm | TWI_MASTER_ARBLOST_bm)) == (TWI_MASTER_WIF_bm | TWI_MASTER_ARBLOST_bm)) + { + TWI->MASTER.ADDR = SlaveAddress; + } + else if ((status & (TWI_MASTER_WIF_bm | TWI_MASTER_RXACK_bm)) == (TWI_MASTER_WIF_bm | TWI_MASTER_RXACK_bm)) + { + TWI_StopTransmission(twi); + return TWI_ERROR_SlaveResponseTimeout; + } + else if (status & (TWI_MASTER_WIF_bm | TWI_MASTER_RIF_bm)) + { + return TWI_ERROR_NoError; + } + + _delay_us(10); + TimeoutRemaining--; + } + + if (!(TimeoutRemaining)) { + if (TWI->MASTER.STATUS & TWI_MASTER_CLKHOLD_bm) { + TWI_StopTransmission(twi); + } + } + + return TWI_ERROR_BusCaptureTimeout; } -bool TWI_SendByte(TWI_t *twi, const uint8_t Byte) +bool TWI_SendByte(TWI_t* const TWI, + const uint8_t Byte) { - // We assume we're ready to write! - twi->MASTER.DATA = Byte; - while (!(twi->MASTER.STATUS & TWI_MASTER_WIF_bm)); - return (twi->MASTER.STATUS & TWI_MASTER_WIF_bm) && !(twi->MASTER.STATUS & TWI_MASTER_RXACK_bm); + TWI->MASTER.DATA = Byte; + + while (!(TWI->MASTER.STATUS & TWI_MASTER_WIF_bm)); + + return (TWI->MASTER.STATUS & TWI_MASTER_WIF_bm) && !(TWI->MASTER.STATUS & TWI_MASTER_RXACK_bm); } -bool TWI_ReceiveByte(TWI_t *twi, uint8_t* const Byte, - const bool LastByte) +bool TWI_ReceiveByte(TWI_t* const TWI, + uint8_t* const Byte, + const bool LastByte) { - // If we're here, we should already be reading. Wait if we haven't read yet. - if (bitmask_is_set(twi->MASTER.STATUS, TWI_MASTER_BUSERR_bm | TWI_MASTER_ARBLOST_bm)) { - return false; - } - while (!(twi->MASTER.STATUS & TWI_MASTER_RIF_bm)); - *Byte = twi->MASTER.DATA; - if (LastByte) - twi->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc; - else - twi->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc; - return true; + if ((TWI->MASTER.STATUS & (TWI_MASTER_BUSERR_bm | TWI_MASTER_ARBLOST_bm)) == (TWI_MASTER_BUSERR_bm | TWI_MASTER_ARBLOST_bm)) { + return false; + } + + while (!(TWI->MASTER.STATUS & TWI_MASTER_RIF_bm)); + + *Byte = TWI->MASTER.DATA; + + if (LastByte) + TWI->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc; + else + TWI->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc; + + return true; } -uint8_t TWI_ReadPacket(TWI_t *twi, +uint8_t TWI_ReadPacket(TWI_t* const TWI, const uint8_t SlaveAddress, const uint8_t TimeoutMS, const uint8_t* InternalAddress, @@ -133,7 +127,7 @@ uint8_t TWI_ReadPacket(TWI_t *twi, } if ((ErrorCode = TWI_StartTransmission(twi, (SlaveAddress & TWI_DEVICE_ADDRESS_MASK) | TWI_ADDRESS_READ, - TimeoutMS)) == TWI_ERROR_NoError) + TimeoutMS)) == TWI_ERROR_NoError) { while (Length--) { @@ -143,15 +137,15 @@ uint8_t TWI_ReadPacket(TWI_t *twi, break; } } - } - TWI_StopTransmission(twi); + + TWI_StopTransmission(twi); } return ErrorCode; } -uint8_t TWI_WritePacket(TWI_t *twi, +uint8_t TWI_WritePacket(TWI_t* const twi, const uint8_t SlaveAddress, const uint8_t TimeoutMS, const uint8_t* InternalAddress, @@ -160,6 +154,7 @@ uint8_t TWI_WritePacket(TWI_t *twi, uint8_t Length) { uint8_t ErrorCode; + if ((ErrorCode = TWI_StartTransmission(twi, (SlaveAddress & TWI_DEVICE_ADDRESS_MASK) | TWI_ADDRESS_WRITE, TimeoutMS)) == TWI_ERROR_NoError) { diff --git a/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.h b/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.h index 0a5d477b2..1f45263aa 100644 --- a/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.h +++ b/LUFA/Drivers/Peripheral/XMEGA/TWI_XMEGA.h @@ -178,77 +178,81 @@ * \attention The value of the \c BitLength parameter should not be set below 10 or invalid bus conditions may * occur, as indicated in the XMEGA microcontroller datasheet. * - * \param[in] twi The TWI Peripheral to use - * \param[in] Baud Value of the BAUD register of the TWI Master. + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. + * \param[in] Baud Value of the BAUD register of the TWI Master. */ - static inline void TWI_Init(TWI_t *twi, const uint8_t Baud) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); - static inline void TWI_Init(TWI_t *twi, const uint8_t Baud) + static inline void TWI_Init(TWI_t* const TWI, + const uint8_t Baud) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); + static inline void TWI_Init(TWI_t* const TWI, + const uint8_t Baud) { - twi->CTRL = 0x00; - twi->MASTER.BAUD = Baud; - twi->MASTER.CTRLA = TWI_MASTER_ENABLE_bm; - twi->MASTER.CTRLB = 0; - twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc; + TWI->CTRL = 0x00; + TWI->MASTER.BAUD = Baud; + TWI->MASTER.CTRLA = TWI_MASTER_ENABLE_bm; + TWI->MASTER.CTRLB = 0; + TWI->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc; } /** Turns off the TWI driver hardware. If this is called, any further TWI operations will require a call to * \ref TWI_Init() before the TWI can be used again. - * - * \param[in] twi The TWI Peripheral to use + * + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. */ - static inline void TWI_Disable(TWI_t *twi) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); - static inline void TWI_Disable(TWI_t *twi) + static inline void TWI_Disable(TWI_t* const TWI) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); + static inline void TWI_Disable(TWI_t* const TWI) { - twi->MASTER.CTRLA &= ~TWI_MASTER_ENABLE_bm; + TWI->MASTER.CTRLA &= ~TWI_MASTER_ENABLE_bm; } - /** Sends a TWI STOP onto the TWI bus, terminating communication with the currently addressed device. - * - * \param[in] twi The TWI Peripheral to use - */ - static inline void TWI_StopTransmission(TWI_t *twi) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); - static inline void TWI_StopTransmission(TWI_t *twi) + /** Sends a TWI STOP onto the TWI bus, terminating communication with the currently addressed device. + * + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. + */ + static inline void TWI_StopTransmission(TWI_t* const TWI) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); + static inline void TWI_StopTransmission(TWI_t* const TWI) { - twi->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc; + TWI->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc; } /* Function Prototypes: */ /** Begins a master mode TWI bus communication with the given slave device address. * - * \param[in] twi The TWI Peripheral to use + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. * \param[in] SlaveAddress Address of the slave TWI device to communicate with. * \param[in] TimeoutMS Timeout period within which the slave must respond, in milliseconds. * * \return A value from the \ref TWI_ErrorCodes_t enum. */ - uint8_t TWI_StartTransmission(TWI_t *twi, - const uint8_t SlaveAddress, + uint8_t TWI_StartTransmission(TWI_t* const TWI, + const uint8_t SlaveAddress, const uint8_t TimeoutMS) ATTR_NON_NULL_PTR_ARG(1); /** Sends a byte to the currently addressed device on the TWI bus. * - * \param[in] twi The TWI Peripheral to use + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. * \param[in] Byte Byte to send to the currently addressed device * * \return Boolean \c true if the recipient ACKed the byte, \c false otherwise */ - bool TWI_SendByte(TWI_t *twi, const uint8_t Byte) ATTR_NON_NULL_PTR_ARG(1); + bool TWI_SendByte(TWI_t* const TWI, + const uint8_t Byte) ATTR_NON_NULL_PTR_ARG(1); /** Receives a byte from the currently addressed device on the TWI bus. * - * \param[in] twi The TWI Peripheral to use + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. * \param[in] Byte Location where the read byte is to be stored. * \param[in] LastByte Indicates if the byte should be ACKed if false, NAKed if true. * * \return Boolean \c true if the byte reception successfully completed, \c false otherwise. */ - bool TWI_ReceiveByte(TWI_t *twi, uint8_t* const Byte, + bool TWI_ReceiveByte(TWI_t* const TWI, + uint8_t* const Byte, const bool LastByte) ATTR_NON_NULL_PTR_ARG(1, 2); /** High level function to perform a complete packet transfer over the TWI bus to the specified * device. * - * \param[in] twi The TWI Peripheral to use + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. * \param[in] SlaveAddress Base address of the TWI slave device to communicate with. * \param[in] TimeoutMS Timeout for bus capture and slave START ACK, in milliseconds. * \param[in] InternalAddress Pointer to a location where the internal slave read start address is stored. @@ -258,8 +262,8 @@ * * \return A value from the \ref TWI_ErrorCodes_t enum. */ - uint8_t TWI_ReadPacket(TWI_t *twi, - const uint8_t SlaveAddress, + uint8_t TWI_ReadPacket(TWI_t* const TWI, + const uint8_t SlaveAddress, const uint8_t TimeoutMS, const uint8_t* InternalAddress, uint8_t InternalAddressLen, @@ -269,7 +273,7 @@ /** High level function to perform a complete packet transfer over the TWI bus from the specified * device. * - * \param[in] twi The TWI Peripheral to use + * \param[in] TWI Pointer to the base of the TWI peripheral within the device. * \param[in] SlaveAddress Base address of the TWI slave device to communicate with * \param[in] TimeoutMS Timeout for bus capture and slave START ACK, in milliseconds * \param[in] InternalAddress Pointer to a location where the internal slave write start address is stored @@ -279,8 +283,8 @@ * * \return A value from the \ref TWI_ErrorCodes_t enum. */ - uint8_t TWI_WritePacket(TWI_t *twi, - const uint8_t SlaveAddress, + uint8_t TWI_WritePacket(TWI_t* const TWI, + const uint8_t SlaveAddress, const uint8_t TimeoutMS, const uint8_t* InternalAddress, uint8_t InternalAddressLen, -- cgit v1.2.3