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-rw-r--r--boards/base/STM32F746-Discovery/board.mk8
-rw-r--r--boards/base/STM32F746-Discovery/board_STM32LTDC.h2
-rw-r--r--boards/base/STM32F746-Discovery/example_raw32/Makefile2
-rw-r--r--boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h76
-rw-r--r--boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c4
-rw-r--r--boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c48
-rw-r--r--boards/base/STM32F746-Discovery/stm32f7_i2c.c164
-rw-r--r--boards/base/STM32F746-Discovery/stm32f7_i2c.h14
-rw-r--r--boards/base/Win32/board.mk4
9 files changed, 311 insertions, 11 deletions
diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk
index dd1f8441..9386fae0 100644
--- a/boards/base/STM32F746-Discovery/board.mk
+++ b/boards/base/STM32F746-Discovery/board.mk
@@ -18,8 +18,9 @@ ifeq ($(OPT_OS),raw32)
GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \
- $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
- GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit
+ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c \
+ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c
+ GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE
SRCFLAGS+= -std=c99
GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \
$(CMSIS)/Include \
@@ -27,4 +28,5 @@ ifeq ($(OPT_OS),raw32)
LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld
endif
-include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk \ No newline at end of file
+include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
+include $(GFXLIB)/drivers/ginput/touch/FT5336/driver.mk \ No newline at end of file
diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h
index 059e7e9d..ffe28e02 100644
--- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h
+++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h
@@ -44,8 +44,6 @@ static const ltdcConfig driverCfg = {
static void configureLcdPins(void)
{
- GPIO_InitTypeDef gpio_init_structure;
-
// Enable GPIOs clock
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN; // GPIOE
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN; // GPIOG
diff --git a/boards/base/STM32F746-Discovery/example_raw32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile
index 298d74bf..dee0f01a 100644
--- a/boards/base/STM32F746-Discovery/example_raw32/Makefile
+++ b/boards/base/STM32F746-Discovery/example_raw32/Makefile
@@ -55,7 +55,7 @@ LDFLAGS =
SRC =
OBJS =
-DEFS = GOS_RAW_HEAP_SIZE=40960
+DEFS = GFX_OS_HEAP_SIZE=40960
LIBS =
INCPATH =
diff --git a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h
new file mode 100644
index 00000000..8031eca5
--- /dev/null
+++ b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.org/license.html
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+#include "stm32f7xx.h"
+#include "stm32f7_i2c.h"
+
+// Resolution and Accuracy Settings
+#define GMOUSE_FT5336_PEN_CALIBRATE_ERROR 8
+#define GMOUSE_FT5336_PEN_CLICK_ERROR 6
+#define GMOUSE_FT5336_PEN_MOVE_ERROR 4
+#define GMOUSE_FT5336_FINGER_CALIBRATE_ERROR 14
+#define GMOUSE_FT5336_FINGER_CLICK_ERROR 18
+#define GMOUSE_FT5336_FINGER_MOVE_ERROR 14
+
+// How much extra data to allocate at the end of the GMouse structure for the board's use
+#define GMOUSE_FT5336_BOARD_DATA_SIZE 0
+
+// The FT5336 I2C slave address (including the R/W bit)
+#define FT5336_SLAVE_ADDR 0x70
+
+static bool_t init_board(GMouse* m, unsigned instance)
+{
+ (void)m;
+ (void)instance;
+
+ // I2C3_SCL GPIOH7, alternate, opendrain, highspeed
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock for
+ GPIOH->MODER |= GPIO_MODER_MODER7_1; // Alternate function
+ GPIOH->OTYPER |= GPIO_OTYPER_OT_7; // OpenDrain
+ GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR7; // LowSpeed
+ GPIOH->AFR[0] |= (0b0100 << 4*7); // AF4
+
+ // I2C3_SDA GPIOH8, alternate, opendrain, highspeed
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock
+ GPIOH->MODER |= GPIO_MODER_MODER8_1; // Alternate function
+ GPIOH->OTYPER |= GPIO_OTYPER_OT_8; // OpenDrain
+ GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8; // LowSpeed
+ GPIOH->AFR[1] |= (0b0100 << 4*0); // AF4
+
+ // Initialize the I2C3 peripheral
+ if (!(i2cInit(I2C3))) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+static void write_reg(GMouse* m, uint8_t reg, uint8_t val)
+{
+ (void)m;
+
+ i2cWriteReg(I2C3, FT5336_SLAVE_ADDR, reg, val);
+}
+
+static uint8_t read_byte(GMouse* m, uint8_t reg)
+{
+ (void)m;
+
+ return i2cReadByte(I2C3, FT5336_SLAVE_ADDR, reg);
+}
+
+static uint16_t read_word(GMouse* m, uint8_t reg)
+{
+ (void)m;
+
+ return i2cReadWord(I2C3, FT5336_SLAVE_ADDR, reg);
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
index 9ffe25ee..f7c4952d 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
@@ -176,7 +176,9 @@ void SystemInit(void)
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
+ //RCC->PLLCFGR = 0x24003010; // From discovery example
+ // M = 12 = 0b1100, N = 192 = 0b11000000, P = 2 = 0b10, Q = 2 = 0b10
+ RCC->PLLCFGR = 0x00C0980C;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
index 3d493e5c..794d3c66 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
@@ -13,7 +13,6 @@ systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
static void SystemClock_Config(void);
static void CPU_CACHE_Enable(void);
-static void LCD_Config(void);
void Raw32OSInit(void) {
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@@ -65,6 +64,7 @@ void Raw32OSInit(void) {
*/
void SystemClock_Config(void)
{
+#if 0
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
HAL_StatusTypeDef ret = HAL_OK;
@@ -74,10 +74,10 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 25;
- RCC_OscInitStruct.PLL.PLLN = 400; // 432
+ RCC_OscInitStruct.PLL.PLLM = 12;
+ RCC_OscInitStruct.PLL.PLLN = 192; // 432
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = 8; // 9
+ RCC_OscInitStruct.PLL.PLLQ = 2; // 9
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
if(ret != HAL_OK)
@@ -104,6 +104,46 @@ void SystemClock_Config(void)
{
while(1) { ; }
}
+#else
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ __PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 12;
+ RCC_OscInitStruct.PLL.PLLN = 192;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ HAL_PWREx_ActivateOverDrive();
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);
+
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+ PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+#endif
}
/**
diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.c b/boards/base/STM32F746-Discovery/stm32f7_i2c.c
new file mode 100644
index 00000000..b0fa8163
--- /dev/null
+++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.c
@@ -0,0 +1,164 @@
+#include "stm32f7_i2c.h"
+
+/*
+ * The CR2 register needs atomic access. Hence always use this function to setup a transfer configuration.
+ */
+static void _i2cConfigTransfer(I2C_TypeDef* i2c, uint16_t slaveAddr, uint8_t numBytes, uint32_t mode, uint32_t request)
+{
+ uint32_t tmpreg = 0;
+
+ // Get the current CR2 register value
+ tmpreg = i2c->CR2;
+
+ // Clear tmpreg specific bits
+ tmpreg &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+ // update tmpreg
+ tmpreg |= (uint32_t) (((uint32_t) slaveAddr & I2C_CR2_SADD) | (((uint32_t) numBytes << 16) & I2C_CR2_NBYTES) | (uint32_t) mode | (uint32_t) request);
+
+ // Update the actual CR2 contents
+ i2c->CR2 = tmpreg;
+}
+
+/*
+ * According to the STM32Cube HAL the CR2 register needs to be reset after each transaction.
+ */
+static void _i2cResetCr2(I2C_TypeDef* i2c)
+{
+ i2c->CR2 &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));
+}
+
+bool_t i2cInit(I2C_TypeDef* i2c)
+{
+ // Enable I2Cx peripheral clock.
+ // Select APB1 as clock source
+ if (i2c == I2C1) {
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C1SEL;
+ RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
+ } else if (i2c == I2C2) {
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C2SEL;
+ RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
+ } else if (i2c == I2C3) {
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C3SEL;
+ RCC->APB1ENR |= RCC_APB1ENR_I2C3EN;
+ } else if (i2c == I2C4) {
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C4SEL;
+ RCC->APB1ENR |= RCC_APB1ENR_I2C4EN;
+ } else {
+ return FALSE;
+ }
+
+ // Disable the I2Cx peripheral
+ i2c->CR1 &= ~I2C_CR1_PE;
+ while (i2c->CR1 & I2C_CR1_PE);
+
+ // Set timings. Asuming I2CCLK is 50 MHz (APB1 clock source)
+ i2c->TIMINGR = 0x40912732; // Discovery BSP code from ST examples
+
+ // Use 7-bit addresses
+ i2c->CR2 &=~ I2C_CR2_ADD10;
+
+ // Enable auto-end mode
+ i2c->CR2 |= I2C_CR2_AUTOEND;
+
+ // Disable the analog filter
+ i2c->CR1 |= I2C_CR1_ANFOFF;
+
+ // Disable NOSTRETCH
+ i2c->CR1 |= I2C_CR1_NOSTRETCH;
+
+ // Enable the I2Cx peripheral
+ i2c->CR1 |= I2C_CR1_PE;
+
+ return TRUE;
+}
+
+void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length)
+{
+ // We are currently not able to send more than 255 bytes at once
+ if (length > 255) {
+ return;
+ }
+
+ // Setup the configuration
+ _i2cConfigTransfer(i2c, slaveAddr, length, (!I2C_CR2_RD_WRN) | I2C_CR2_AUTOEND, I2C_CR2_START);
+
+ // Transmit the whole buffer
+ while (length > 0) {
+ while (!(i2c->ISR & I2C_ISR_TXIS));
+ i2c->TXDR = *data++;
+ length--;
+ }
+
+ // Wait until the transfer is complete
+ while (!(i2c->ISR & I2C_ISR_TXE));
+
+ // Wait until the stop condition was automagically sent
+ while (!(i2c->ISR & I2C_ISR_STOPF));
+
+ // Reset the STOP bit
+ i2c->ISR &= ~I2C_ISR_STOPF;
+
+ // Reset the CR2 register
+ _i2cResetCr2(i2c);
+}
+
+void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data)
+{
+ i2cSend(i2c, slaveAddr, &data, 1);
+}
+
+void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value)
+{
+ uint8_t txbuf[2];
+ txbuf[0] = regAddr;
+ txbuf[1] = value;
+
+ i2cSend(i2c, slaveAddr, txbuf, 2);
+}
+
+void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length)
+{
+ // We are currently not able to read more than 255 bytes at once
+ if (length > 255) {
+ return;
+ }
+
+ // Setup the configuration
+ _i2cConfigTransfer(i2c, slaveAddr, length, I2C_CR2_RD_WRN | I2C_CR2_AUTOEND, I2C_CR2_START);
+
+ // Transmit the whole buffer
+ for (int i = 0; i < length; i++) {
+ while (!(i2c->ISR & I2C_ISR_RXNE));
+ data[i] = i2c->RXDR;
+ }
+
+ // Wait until the stop condition was automagically sent
+ while (!(i2c->ISR & I2C_ISR_STOPF));
+
+ // Reset the STOP bit
+ i2c->ISR &= ~I2C_ISR_STOPF;
+
+ // Reset the CR2 register
+ _i2cResetCr2(i2c);
+}
+
+uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr)
+{
+ uint8_t ret = 0xAA;
+
+ i2cSend(i2c, slaveAddr, &regAddr, 1);
+ i2cRead(i2c, slaveAddr, &ret, 1);
+
+ return ret;
+}
+
+uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr)
+{
+ uint8_t ret[2] = { 0xAA, 0xAA };
+
+ i2cSend(i2c, slaveAddr, &regAddr, 1);
+ i2cRead(i2c, slaveAddr, ret, 2);
+
+ return (uint16_t)((ret[0] << 8) | (ret[1] & 0x00FF));
+}
diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.h b/boards/base/STM32F746-Discovery/stm32f7_i2c.h
new file mode 100644
index 00000000..625aeed8
--- /dev/null
+++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.h
@@ -0,0 +1,14 @@
+#pragma once
+
+#include "stm32f7xx.h"
+#include "gfx.h"
+
+bool_t i2cInit(I2C_TypeDef* i2c);
+
+void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length);
+void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data);
+void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value);
+
+void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length);
+uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr);
+uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr);
diff --git a/boards/base/Win32/board.mk b/boards/base/Win32/board.mk
index adcbaeaf..b4577927 100644
--- a/boards/base/Win32/board.mk
+++ b/boards/base/Win32/board.mk
@@ -3,3 +3,7 @@ GFXSRC +=
GFXLIBS +=
include $(GFXLIB)/drivers/multiple/Win32/driver.mk
include $(GFXLIB)/drivers/gaudio/Win32/driver.mk
+
+ifeq ($(OPT_OS),win32.raw32)
+ GFXDEFS += GFX_OS_INIT_NO_WARNING=TRUE
+endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-29 15:02:37 +0000