From d4f2cb0d72c3fd6d0c57113bf71e3225b82c5306 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Thu, 9 Jul 2015 03:12:16 +0200 Subject: Some more work on the F7 discovery --- boards/base/STM32F746-Discovery/board.mk | 4 +- .../STM32F746-Discovery/board_STM32F746Discovery.h | 4 +- .../stm32746g_discovery_sdram.c | 499 --------------------- .../stm32746g_discovery_sdram.h | 165 ------- .../stm32f429i_discovery_sdram.c | 333 -------------- .../stm32f429i_discovery_sdram.h | 96 ---- .../stm32f746g_discovery_sdram.c | 499 +++++++++++++++++++++ .../stm32f746g_discovery_sdram.h | 167 +++++++ 8 files changed, 670 insertions(+), 1097 deletions(-) delete mode 100644 boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c delete mode 100644 boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h delete mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c delete mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h (limited to 'boards') diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index d43e1709..ce70ef15 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -1,5 +1,5 @@ GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery -GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c +GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk \ No newline at end of file diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h index 735cdbdb..33f6e2cb 100644 --- a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h +++ b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h @@ -8,8 +8,8 @@ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H -#include "stm32f4xx_fmc.h" -#include "stm32f429i_discovery_sdram.h" +#include "stm32f7xx_ll_fmc.h" +#include "stm32f746g_discovery_sdram.h" #include static const ltdcConfig driverCfg = { diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c deleted file mode 100644 index d214b3f1..00000000 --- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c +++ /dev/null @@ -1,499 +0,0 @@ -/** - ****************************************************************************** - * @file stm32746g_discovery_sdram.c - * @author MCD Application Team - * @version V1.0.0 - * @date 25-June-2015 - * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory - * device mounted on STM32746G-Discovery board. - @verbatim - 1. How To use this driver: - -------------------------- - - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted - on STM32746G-Discovery board. - - This driver does not need a specific component driver for the SDRAM device - to be included with. - - 2. Driver description: - --------------------- - + Initialization steps: - o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This - function includes the MSP layer hardware resources initialization and the - FMC controller configuration to interface with the external SDRAM memory. - o It contains the SDRAM initialization sequence to program the SDRAM external - device using the function BSP_SDRAM_Initialization_sequence(). Note that this - sequence is standard for all SDRAM devices, but can include some differences - from a device to another. If it is the case, the right sequence should be - implemented separately. - - + SDRAM read/write operations - o SDRAM external memory can be accessed with read/write operations once it is - initialized. - Read/write operation can be performed with AHB access using the functions - BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions - BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). - o The AHB access is performed with 32-bit width transaction, the DMA transfer - configuration is fixed at single (no burst) word transfer (see the - SDRAM_MspInit() static function). - o User can implement his own functions for read/write access with his desired - configurations. - o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() - is called in IRQ handler file, to serve the generated interrupt once the DMA - transfer is complete. - o You can send a command to the SDRAM device in runtime using the function - BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between - the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32746g_discovery_sdram.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32746G_DISCOVERY - * @{ - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM - * @{ - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables - * @{ - */ -static SDRAM_HandleTypeDef sdramHandle; -static FMC_SDRAM_TimingTypeDef Timing; -static FMC_SDRAM_CommandTypeDef Command; -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions - * @{ - */ - -/** - * @brief Initializes the SDRAM device. - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_Init(void) -{ - static uint8_t sdramstatus = SDRAM_ERROR; - /* SDRAM device configuration */ - sdramHandle.Instance = FMC_SDRAM_DEVICE; - - /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ - Timing.LoadToActiveDelay = 2; - Timing.ExitSelfRefreshDelay = 7; - Timing.SelfRefreshTime = 4; - Timing.RowCycleDelay = 7; - Timing.WriteRecoveryTime = 2; - Timing.RPDelay = 2; - Timing.RCDDelay = 2; - - sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; - sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; - sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; - sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; - sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; - sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; - sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; - sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; - sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; - sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; - - /* SDRAM controller initialization */ - - BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ - - if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) - { - sdramstatus = SDRAM_ERROR; - } - else - { - sdramstatus = SDRAM_OK; - } - - /* SDRAM initialization sequence */ - BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); - - return sdramstatus; -} - -/** - * @brief DeInitializes the SDRAM device. - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_DeInit(void) -{ - static uint8_t sdramstatus = SDRAM_ERROR; - /* SDRAM device de-initialization */ - sdramHandle.Instance = FMC_SDRAM_DEVICE; - - if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) - { - sdramstatus = SDRAM_ERROR; - } - else - { - sdramstatus = SDRAM_OK; - } - - /* SDRAM controller de-initialization */ - BSP_SDRAM_MspDeInit(&sdramHandle, NULL); - - return sdramstatus; -} - -/** - * @brief Programs the SDRAM device. - * @param RefreshCount: SDRAM refresh counter value - * @retval None - */ -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) -{ - __IO uint32_t tmpmrd = 0; - - /* Step 1: Configure a clock configuration enable command */ - Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; - Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; - Command.AutoRefreshNumber = 1; - Command.ModeRegisterDefinition = 0; - - /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); - - /* Step 2: Insert 100 us minimum delay */ - /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ - HAL_Delay(1); - - /* Step 3: Configure a PALL (precharge all) command */ - Command.CommandMode = FMC_SDRAM_CMD_PALL; - Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; - Command.AutoRefreshNumber = 1; - Command.ModeRegisterDefinition = 0; - - /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); - - /* Step 4: Configure an Auto Refresh command */ - Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; - Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; - Command.AutoRefreshNumber = 8; - Command.ModeRegisterDefinition = 0; - - /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); - - /* Step 5: Program the external memory mode register */ - tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ - SDRAM_MODEREG_CAS_LATENCY_2 |\ - SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; - Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; - Command.AutoRefreshNumber = 1; - Command.ModeRegisterDefinition = tmpmrd; - - /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); - - /* Step 6: Set the refresh rate counter */ - /* Set the device refresh rate */ - HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); -} - -/** - * @brief Reads an amount of data from the SDRAM memory in polling mode. - * @param uwStartAddress: Read start address - * @param pData: Pointer to data to be read - * @param uwDataSize: Size of read data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Reads an amount of data from the SDRAM memory in DMA mode. - * @param uwStartAddress: Read start address - * @param pData: Pointer to data to be read - * @param uwDataSize: Size of read data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Writes an amount of data to the SDRAM memory in polling mode. - * @param uwStartAddress: Write start address - * @param pData: Pointer to data to be written - * @param uwDataSize: Size of written data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Writes an amount of data to the SDRAM memory in DMA mode. - * @param uwStartAddress: Write start address - * @param pData: Pointer to data to be written - * @param uwDataSize: Size of written data from the memory - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) -{ - if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Sends command to the SDRAM bank. - * @param SdramCmd: Pointer to SDRAM command structure - * @retval SDRAM status - */ -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) -{ - if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) - { - return SDRAM_ERROR; - } - else - { - return SDRAM_OK; - } -} - -/** - * @brief Handles SDRAM DMA transfer interrupt request. - * @retval None - */ -void BSP_SDRAM_DMA_IRQHandler(void) -{ - HAL_DMA_IRQHandler(sdramHandle.hdma); -} - -/** - * @brief Initializes SDRAM MSP. - * @param hsdram: SDRAM handle - * @param Params - * @retval None - */ -__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) -{ - static DMA_HandleTypeDef dma_handle; - GPIO_InitTypeDef gpio_init_structure; - - /* Enable FMC clock */ - __HAL_RCC_FMC_CLK_ENABLE(); - - /* Enable chosen DMAx clock */ - __DMAx_CLK_ENABLE(); - - /* Enable GPIOs clock */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - - /* Common GPIO configuration */ - gpio_init_structure.Mode = GPIO_MODE_AF_PP; - gpio_init_structure.Pull = GPIO_PULLUP; - gpio_init_structure.Speed = GPIO_SPEED_FAST; - gpio_init_structure.Alternate = GPIO_AF12_FMC; - - /* GPIOC configuration */ - gpio_init_structure.Pin = GPIO_PIN_3; - HAL_GPIO_Init(GPIOC, &gpio_init_structure); - - /* GPIOD configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; - HAL_GPIO_Init(GPIOD, &gpio_init_structure); - - /* GPIOE configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ - GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ - GPIO_PIN_15; - HAL_GPIO_Init(GPIOE, &gpio_init_structure); - - /* GPIOF configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ - GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ - GPIO_PIN_15; - HAL_GPIO_Init(GPIOF, &gpio_init_structure); - - /* GPIOG configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ - GPIO_PIN_15; - HAL_GPIO_Init(GPIOG, &gpio_init_structure); - - /* GPIOH configuration */ - gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; - HAL_GPIO_Init(GPIOH, &gpio_init_structure); - - /* Configure common DMA parameters */ - dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; - dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; - dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; - dma_handle.Init.MemInc = DMA_MINC_ENABLE; - dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - dma_handle.Init.Mode = DMA_NORMAL; - dma_handle.Init.Priority = DMA_PRIORITY_HIGH; - dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; - dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; - - dma_handle.Instance = SDRAM_DMAx_STREAM; - - /* Associate the DMA handle */ - __HAL_LINKDMA(hsdram, hdma, dma_handle); - - /* Deinitialize the stream for new transfer */ - HAL_DMA_DeInit(&dma_handle); - - /* Configure the DMA stream */ - HAL_DMA_Init(&dma_handle); - - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); -} - -/** - * @brief DeInitializes SDRAM MSP. - * @param hsdram: SDRAM handle - * @param Params - * @retval None - */ -__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) -{ - static DMA_HandleTypeDef dma_handle; - - /* Disable NVIC configuration for DMA interrupt */ - HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); - - /* Deinitialize the stream for new transfer */ - dma_handle.Instance = SDRAM_DMAx_STREAM; - HAL_DMA_DeInit(&dma_handle); - - /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications - by surcharging this __weak function */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h deleted file mode 100644 index cafdce5c..00000000 --- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - ****************************************************************************** - * @file stm32746g_discovery_sdram.h - * @author MCD Application Team - * @version V1.0.0 - * @date 25-June-2015 - * @brief This file contains the common defines and functions prototypes for - * the stm32746g_discovery_sdram.c driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32746G_DISCOVERY_SDRAM_H -#define __STM32746G_DISCOVERY_SDRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32746G_DISCOVERY - * @{ - */ - -/** @addtogroup STM32746G_DISCOVERY_SDRAM - * @{ - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types - * @{ - */ - -/** - * @brief SDRAM status structure definition - */ -#define SDRAM_OK ((uint8_t)0x00) -#define SDRAM_ERROR ((uint8_t)0x01) - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants - * @{ - */ -#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) -#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ - -/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ -#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 - -#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 -/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ - -#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ - -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) - -/* DMA definitions for SDRAM DMA transfer */ -#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 -#define SDRAM_DMAx_STREAM DMA2_Stream0 -#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn -#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler -/** - * @} - */ - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) -/** - * @} - */ - -/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro - * @{ - */ -/** - * @} - */ - -/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions - * @{ - */ -uint8_t BSP_SDRAM_Init(void); -uint8_t BSP_SDRAM_DeInit(void); -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); -void BSP_SDRAM_DMA_IRQHandler(void); - -/* These functions can be modified in case the current settings (e.g. DMA stream) - need to be changed for specific application needs */ -void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); -void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32746G_DISCOVERY_SDRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c deleted file mode 100644 index 3b467b4b..00000000 --- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c +++ /dev/null @@ -1,333 +0,0 @@ -#include "ch.h" -#include "hal.h" - -#include "stm32f429i_discovery_sdram.h" -#include "stm32f4xx_fmc.h" - -/** - * @brief Configures the FMC and GPIOs to interface with the SDRAM memory. - * This function must be called before any read/write operation - * on the SDRAM. - * @param None - * @retval None - */ -void SDRAM_Init(void) -{ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* Enable FMC clock */ - rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE); - -/* FMC Configuration ---------------------------------------------------------*/ -/* FMC SDRAM Bank configuration */ - /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (6x11.90ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=63 (6x11.90ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 15ns => 2x11.90ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 15ns => 2x11.90ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - -/* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; - FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAM_InitSequence(); - -} - -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+--------------------+--------------------+ - + SDRAM pins assignment + - +-------------------+--------------------+--------------------+--------------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | - +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | - | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | - | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | - | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | - +-------------------+--------------------+--------------------+ - | PB5 <-> FMC_SDCKE1| - | PB6 <-> FMC_SDNE1 | - | PC0 <-> FMC_SDNWE | - +-------------------+ - -*/ - -// /* Common GPIO configuration */ -// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; -// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; -// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; -// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; -// -// /* GPIOB configuration */ -// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; -// -// GPIO_Init(GPIOB, &GPIO_InitStructure); -// -// /* GPIOC configuration */ -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; -// -// GPIO_Init(GPIOC, &GPIO_InitStructure); -// -// /* GPIOD configuration */ -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | -// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | -// GPIO_Pin_15; -// -// GPIO_Init(GPIOD, &GPIO_InitStructure); -// -// /* GPIOE configuration */ -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | -// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | -// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | -// GPIO_Pin_14 | GPIO_Pin_15; -// -// GPIO_Init(GPIOE, &GPIO_InitStructure); -// -// /* GPIOF configuration */ -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | -// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | -// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | -// GPIO_Pin_14 | GPIO_Pin_15; -// -// GPIO_Init(GPIOF, &GPIO_InitStructure); -// -// /* GPIOG configuration */ -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); -// -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | -// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; -// -// GPIO_Init(GPIOG, &GPIO_InitStructure); - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - -/* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and - //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than - //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh - //mode -/* Step 4 --------------------------------------------------------------------*/ - /* Insert 1 ms delay */ - chThdSleepMilliseconds(1); - -/* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (7.81 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(683); - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } -} - - -/** - * @brief Writes a Entire-word buffer to the SDRAM memory. - * @param pBuffer: pointer to buffer. - * @param uwWriteAddress: SDRAM memory internal address from which the data will be - * written. - * @param uwBufferSize: number of words to write. - * @retval None. - */ -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; - - /* Disable write protection */ - FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - /* While there is data to write */ - for (; uwBufferSize != 0; uwBufferSize--) - { - /* Transfer data to the memory */ - *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; - - /* Increment the address*/ - write_pointer += 4; - } - -} - -/** - * @brief Reads data buffer from the SDRAM memory. - * @param pBuffer: pointer to buffer. - * @param ReadAddress: SDRAM memory internal address from which the data will be - * read. - * @param uwBufferSize: number of words to write. - * @retval None. - */ -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwReadAddress; - - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - /* Read data */ - for(; uwBufferSize != 0x00; uwBufferSize--) - { - *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); - - /* Increment the address*/ - write_pointer += 4; - } -} - diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h deleted file mode 100644 index fba5115d..00000000 --- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f429i_discovery_sdram.h - * @author MCD Application Team - * @version V1.0.0 - * @date 20-September-2013 - * @brief This file contains all the functions prototypes for the - * stm324x9i_disco_sdram.c driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32429I_DISCO_SDRAM_H -#define __STM32429I_DISCO_SDRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -//FIXME this should not be needed -#define STM32F429_439xx - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** - * @brief FMC SDRAM Bank address - */ -#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) - -/** - * @brief FMC SDRAM Memory Width - */ -/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ -#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b - -/** - * @brief FMC SDRAM CAS Latency - */ -/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ -#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 - -/** - * @brief FMC SDRAM Memory clock period - */ -#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ -/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ - -/** - * @brief FMC SDRAM Memory Read Burst feature - */ -#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ -/* #define SDRAM_READBURST FMC_Read_Burst_Enable */ - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -void SDRAM_Init(void); -void SDRAM_InitSequence(void); -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize); -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c new file mode 100644 index 00000000..0ef2d634 --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -0,0 +1,499 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.c + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory + * device mounted on STM32746G-Discovery board. + @verbatim + 1. How To use this driver: + -------------------------- + - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted + on STM32746G-Discovery board. + - This driver does not need a specific component driver for the SDRAM device + to be included with. + + 2. Driver description: + --------------------- + + Initialization steps: + o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This + function includes the MSP layer hardware resources initialization and the + FMC controller configuration to interface with the external SDRAM memory. + o It contains the SDRAM initialization sequence to program the SDRAM external + device using the function BSP_SDRAM_Initialization_sequence(). Note that this + sequence is standard for all SDRAM devices, but can include some differences + from a device to another. If it is the case, the right sequence should be + implemented separately. + + + SDRAM read/write operations + o SDRAM external memory can be accessed with read/write operations once it is + initialized. + Read/write operation can be performed with AHB access using the functions + BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions + BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). + o The AHB access is performed with 32-bit width transaction, the DMA transfer + configuration is fixed at single (no burst) word transfer (see the + SDRAM_MspInit() static function). + o User can implement his own functions for read/write access with his desired + configurations. + o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() + is called in IRQ handler file, to serve the generated interrupt once the DMA + transfer is complete. + o You can send a command to the SDRAM device in runtime using the function + BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between + the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f746g_discovery_sdram.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables + * @{ + */ +static SDRAM_HandleTypeDef sdramHandle; +static FMC_SDRAM_TimingTypeDef Timing; +static FMC_SDRAM_CommandTypeDef Command; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions + * @{ + */ + +/** + * @brief Initializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Init(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device configuration */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ + Timing.LoadToActiveDelay = 2; + Timing.ExitSelfRefreshDelay = 7; + Timing.SelfRefreshTime = 4; + Timing.RowCycleDelay = 7; + Timing.WriteRecoveryTime = 2; + Timing.RPDelay = 2; + Timing.RCDDelay = 2; + + sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; + sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + + /* SDRAM controller initialization */ + + BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + + if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + + return sdramstatus; +} + +/** + * @brief DeInitializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_DeInit(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device de-initialization */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM controller de-initialization */ + BSP_SDRAM_MspDeInit(&sdramHandle, NULL); + + return sdramstatus; +} + +/** + * @brief Programs the SDRAM device. + * @param RefreshCount: SDRAM refresh counter value + * @retval None + */ +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +{ + __IO uint32_t tmpmrd = 0; + + /* Step 1: Configure a clock configuration enable command */ + Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + + /* Step 3: Configure a PALL (precharge all) command */ + Command.CommandMode = FMC_SDRAM_CMD_PALL; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 4: Configure an Auto Refresh command */ + Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 8; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = tmpmrd; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); +} + +/** + * @brief Reads an amount of data from the SDRAM memory in polling mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Reads an amount of data from the SDRAM memory in DMA mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in polling mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in DMA mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Sends command to the SDRAM bank. + * @param SdramCmd: Pointer to SDRAM command structure + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) +{ + if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Handles SDRAM DMA transfer interrupt request. + * @retval None + */ +void BSP_SDRAM_DMA_IRQHandler(void) +{ + HAL_DMA_IRQHandler(sdramHandle.hdma); +} + +/** + * @brief Initializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF12_FMC; + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + dma_handle.Init.Mode = DMA_NORMAL; + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + + dma_handle.Instance = SDRAM_DMAx_STREAM; + + /* Associate the DMA handle */ + __HAL_LINKDMA(hsdram, hdma, dma_handle); + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); +} + +/** + * @brief DeInitializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + + /* Disable NVIC configuration for DMA interrupt */ + HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); + + /* Deinitialize the stream for new transfer */ + dma_handle.Instance = SDRAM_DMAx_STREAM; + HAL_DMA_DeInit(&dma_handle); + + /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications + by surcharging this __weak function */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h new file mode 100644 index 00000000..56d7fd4b --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file contains the common defines and functions prototypes for + * the stm32746g_discovery_sdram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F746G_DISCOVERY_SDRAM_H +#define __STM32F746G_DISCOVERY_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_sdram.h" +#include "stm32f7xx_hal_dma.h" +#include "stm32f7xx_ll_fmc.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types + * @{ + */ + +/** + * @brief SDRAM status structure definition + */ +#define SDRAM_OK ((uint8_t)0x00) +#define SDRAM_ERROR ((uint8_t)0x01) + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants + * @{ + */ +#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) +#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ + +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 + +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ + +#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ + +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +/* DMA definitions for SDRAM DMA transfer */ +#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 +#define SDRAM_DMAx_STREAM DMA2_Stream0 +#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn +#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler +/** + * @} + */ + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions + * @{ + */ +uint8_t BSP_SDRAM_Init(void); +uint8_t BSP_SDRAM_DeInit(void); +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); +void BSP_SDRAM_DMA_IRQHandler(void); + +/* These functions can be modified in case the current settings (e.g. DMA stream) + need to be changed for specific application needs */ +void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); +void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_SDRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3