From 767188ed8d9d44d1f60ec9ed3f8fad295d6434fe Mon Sep 17 00:00:00 2001 From: Mateusz Tomaszkiewicz Date: Wed, 12 Jun 2013 23:23:05 +0200 Subject: SSD2119: make use of DMA This is mostly a copy from Eddie's work posted here: http://forum.chibios.org/phpbb/viewtopic.php?f=11&t=851#p11054 No work was done towards making it work as fast as possible. Tested with: https://github.com/etmatrix/ChibiOS-GFX-Example/blob/master/bench/main.c Results show performance of ~5.34 Mpx/s with use of DMA compared to ~4.78 Mpx/s without. --- .../SSD2119/gdisp_lld_board_embest_dmstf4bb.h | 65 +++++++++++++++------- 1 file changed, 44 insertions(+), 21 deletions(-) (limited to 'drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h') diff --git a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h index ccbba2a3..a223ad18 100644 --- a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h +++ b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h @@ -16,38 +16,60 @@ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H +#define GDISP_USE_DMA +#define GDISP_DMA_STREAM STM32_DMA2_STREAM6 + /* Using FSMC A19 (PE3) as DC */ -#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */ -#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */ +#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */ +#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */ + +#define SET_RST palSetPad(GPIOD, 3); +#define CLR_RST palClearPad(GPIOD, 3); -#define SET_RST palSetPad(GPIOD, 3); -#define CLR_RST palClearPad(GPIOD, 3); +const unsigned char FSMC_Bank = 0; -/* PWM configuration structure. We use timer 4 channel 2 (orange LED on board). */ +/* + * PWM configuration structure. We use timer 4 channel 2 (orange LED on board). + * The reason for so high clock is that with any lower, onboard coil is squeaking. + * The major disadvantage of this clock is a lack of linearity between PWM duty + * cycle width and brightness. In fact only with low preset one sees any change + * (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board + * behaves like this. + */ static const PWMConfig pwmcfg = { - 1000000, /* 1 MHz PWM clock frequency. */ - 100, /* PWM period is 100 cycles. */ - NULL, - { - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH, NULL} - }, - 0 + 1000000, /* 1 MHz PWM clock frequency. */ + 100, /* PWM period is 100 cycles. */ + NULL, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + 0 }; /** * @brief Initialise the board for the display. - * @notes This board definition uses GPIO and assumes exclusive access to these GPIO pins + * @notes This board definition uses GPIO and assumes exclusive access to these GPIO pins * * @notapi */ static inline void init_board(void) { - unsigned char FSMC_Bank; - /* STM32F4 FSMC init */ - rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); + #if defined(STM32F4XX) || defined(STM32F2XX) + /* STM32F4 FSMC init */ + rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); + + #if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) + if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL)) + gfxExit(); + dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM); + dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); + #endif + #else + #error "FSMC not implemented for this device" + #endif /* Group pins */ IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) | @@ -60,10 +82,11 @@ static inline void init_board(void) { palSetBusMode(&busD, PAL_MODE_ALTERNATE(12)); palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); - FSMC_Bank = 0; + /* FSMC timing */ +// FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ; /* FSMC timing */ - FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \ + FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \ | (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \ | (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ; -- cgit v1.2.3 From f820fb90d51e5dba715a520baf40474d521bdce2 Mon Sep 17 00:00:00 2001 From: Mateusz Tomaszkiewicz Date: Thu, 13 Jun 2013 00:20:00 +0200 Subject: SSD2119: GDISP_USE_FSMC "switch" added Enable FSMC functions only when GDISP_USE_FSMC is set. --- drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h') diff --git a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h index a223ad18..4993a511 100644 --- a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h +++ b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h @@ -16,6 +16,9 @@ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H +/* This board file uses only FSMC, so don't undefine this. */ +#define GDISP_USE_FSMC +/* But it is OK to disable DMA use. */ #define GDISP_USE_DMA #define GDISP_DMA_STREAM STM32_DMA2_STREAM6 @@ -57,6 +60,10 @@ static const PWMConfig pwmcfg = { */ static inline void init_board(void) { + #ifndef GDISP_USE_FSMC + #error "This board uses only FSMC, please define GDISP_USE_FSMC" + #endif + #if defined(STM32F4XX) || defined(STM32F2XX) /* STM32F4 FSMC init */ rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); -- cgit v1.2.3 From d57eacc345da25732ec6bace92878a76b587e548 Mon Sep 17 00:00:00 2001 From: Mateusz Tomaszkiewicz Date: Thu, 20 Jun 2013 22:49:36 +0200 Subject: SSD2119: FSMC settings tuned With FSMC BTR timing register settings tuned and DMA on, we get over 10.2 Mpx/s instead of 4.7 Mpx/s. --- .../SSD2119/gdisp_lld_board_embest_dmstf4bb.h | 24 ++++++++++------------ 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h') diff --git a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h index 4993a511..068af149 100644 --- a/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h +++ b/drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h @@ -29,15 +29,14 @@ #define SET_RST palSetPad(GPIOD, 3); #define CLR_RST palClearPad(GPIOD, 3); -const unsigned char FSMC_Bank = 0; - /* * PWM configuration structure. We use timer 4 channel 2 (orange LED on board). * The reason for so high clock is that with any lower, onboard coil is squeaking. * The major disadvantage of this clock is a lack of linearity between PWM duty * cycle width and brightness. In fact only with low preset one sees any change * (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board - * behaves like this. + * behaves like this. According to the G5126 datesheet (backlight LED driver) + * the PWM frequency should be somewhere between 200 Hz to 200 kHz. */ static const PWMConfig pwmcfg = { 1000000, /* 1 MHz PWM clock frequency. */ @@ -59,6 +58,7 @@ static const PWMConfig pwmcfg = { * @notapi */ static inline void init_board(void) { + unsigned char FSMC_Bank; #ifndef GDISP_USE_FSMC #error "This board uses only FSMC, please define GDISP_USE_FSMC" @@ -89,17 +89,15 @@ static inline void init_board(void) { palSetBusMode(&busD, PAL_MODE_ALTERNATE(12)); palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); - /* FSMC timing */ -// FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ; - - /* FSMC timing */ - FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \ - | (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \ - | (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ; + FSMC_Bank = 0; + /* FSMC timing register configuration */ + FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ + | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \ + | FSMC_BTR1_BUSTURN_0; - /* Bank1 NOR/SRAM control register configuration - * This is actually not needed as already set by default after reset */ - FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN; + /* Bank1 NOR/PSRAM control register configuration + * Write enable, memory databus width set to 16 bit, memory bank enable */ + FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_WREN | FSMC_BCR1_MWID_0 | FSMC_BCR1_MBKEN; /* Display backlight control */ /* TIM4 is an alternate function 2 (AF2) */ -- cgit v1.2.3