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Shape Rectangle Style fill Color b 0 g 0.463735 r 1 Text Text {\rtf1\ansi\ansicpg1252\cocoartf1187\cocoasubrtf340 \cocoascreenfonts1{\fonttbl\f0\fswiss\fcharset0 Helvetica;} {\colortbl;\red255\green255\blue255;\red37\green17\blue0;} \pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc \f0\fs24 \cf2 mitmproxy} Bounds {{4.6666666467984399, 351.33332316080771}, {102.66666412353516, 130.66667175292969}} Class ShapedGraphic ID 134 ImageID 3 Shape Rectangle Style fill Draws NO shadow Draws NO stroke Draws NO GridInfo GuidesLocked NO GuidesVisible YES HPages 1 ImageCounter 7 ImageLinkBack ImageList image6.tiff image3.icns KeepToScale Layers Lock NO Name Layer 1 Print YES View YES LayoutInfo Animate NO circoMinDist 18 circoSeparation 0.0 layoutEngine dot neatoSeparation 0.0 twopiSeparation 0.0 LinksVisible NO MagnetsVisible NO MasterSheets ModificationDate 2013-01-03 02:14:45 +0000 Modifier Aldo Cortesi NotesVisible NO Orientation 2 OriginVisible NO PageBreaks YES PrintInfo NSBottomMargin float 41 NSHorizonalPagination coded BAtzdHJlYW10eXBlZIHoA4QBQISEhAhOU051bWJlcgCEhAdOU1ZhbHVlAISECE5TT2JqZWN0AIWEASqEhAFxlwCG NSLeftMargin float 18 NSPaperSize size {595.19998741149902, 841.79998779296875} NSPrintReverseOrientation int 0 NSRightMargin float 18 NSTopMargin float 18 PrintOnePage ReadOnly NO RowAlign 1 RowSpacing 36 SheetTitle Canvas 1 SmartAlignmentGuidesActive YES SmartDistanceGuidesActive YES UniqueID 1 UseEntirePage VPages 1 WindowInfo CurrentSheet 0 ExpandedCanvases name Canvas 1 Frame {{271, 336}, {974, 874}} ListView OutlineWidth 142 RightSidebar ShowRuler Sidebar SidebarWidth 120 VisibleRegion {{0, 202}, {550, 469.33333333333337}} Zoom 1.5 ZoomValues Canvas 1 1.5 1 s="o">* get_intremap_lock(int req_id) { return (amd_iommu_perdev_intremap ? &ivrs_mappings[req_id].intremap_lock: &shared_intremap_lock); } static int get_intremap_requestor_id(int bdf) { ASSERT( bdf < ivrs_bdf_entries ); return ivrs_mappings[bdf].dte_requestor_id; } static int get_intremap_offset(u8 vector, u8 dm) { int offset = 0; offset = (dm << INT_REMAP_INDEX_DM_SHIFT) & INT_REMAP_INDEX_DM_MASK; offset |= (vector << INT_REMAP_INDEX_VECTOR_SHIFT ) & INT_REMAP_INDEX_VECTOR_MASK; return offset; } static u8 *get_intremap_entry(int bdf, int offset) { u8 *table; table = (u8*)ivrs_mappings[bdf].intremap_table; ASSERT( (table != NULL) && (offset < INTREMAP_ENTRIES) ); return (u8*) (table + offset); } static void free_intremap_entry(int bdf, int offset) { u32* entry; entry = (u32*)get_intremap_entry(bdf, offset); memset(entry, 0, sizeof(u32)); } static void update_intremap_entry(u32* entry, u8 vector, u8 int_type, u8 dest_mode, u8 dest) { set_field_in_reg_u32(IOMMU_CONTROL_ENABLED, 0, INT_REMAP_ENTRY_REMAPEN_MASK, INT_REMAP_ENTRY_REMAPEN_SHIFT, entry); set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, *entry, INT_REMAP_ENTRY_SUPIOPF_MASK, INT_REMAP_ENTRY_SUPIOPF_SHIFT, entry); set_field_in_reg_u32(int_type, *entry, INT_REMAP_ENTRY_INTTYPE_MASK, INT_REMAP_ENTRY_INTTYPE_SHIFT, entry); set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, *entry, INT_REMAP_ENTRY_REQEOI_MASK, INT_REMAP_ENTRY_REQEOI_SHIFT, entry); set_field_in_reg_u32((u32)dest_mode, *entry, INT_REMAP_ENTRY_DM_MASK, INT_REMAP_ENTRY_DM_SHIFT, entry); set_field_in_reg_u32((u32)dest, *entry, INT_REMAP_ENTRY_DEST_MAST, INT_REMAP_ENTRY_DEST_SHIFT, entry); set_field_in_reg_u32((u32)vector, *entry, INT_REMAP_ENTRY_VECTOR_MASK, INT_REMAP_ENTRY_VECTOR_SHIFT, entry); } void invalidate_interrupt_table(struct amd_iommu *iommu, u16 device_id) { u32 cmd[4], entry; cmd[3] = cmd[2] = 0; set_field_in_reg_u32(device_id, 0, IOMMU_INV_INT_TABLE_DEVICE_ID_MASK, IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT, &entry); cmd[0] = entry; set_field_in_reg_u32(IOMMU_CMD_INVALIDATE_INT_TABLE, 0, IOMMU_CMD_OPCODE_MASK, IOMMU_CMD_OPCODE_SHIFT, &entry); cmd[1] = entry; send_iommu_command(iommu, cmd); } static void update_intremap_entry_from_ioapic( int bdf, struct amd_iommu *iommu, struct IO_APIC_route_entry *ioapic_rte, unsigned int rte_upper, unsigned int value) { unsigned long flags; u32* entry; u8 delivery_mode, dest, vector, dest_mode; struct IO_APIC_route_entry *rte = ioapic_rte; int req_id; spinlock_t *lock; int offset; req_id = get_intremap_requestor_id(bdf); lock = get_intremap_lock(req_id); /* only remap interrupt vector when lower 32 bits in ioapic ire changed */ if ( likely(!rte_upper) ) { delivery_mode = rte->delivery_mode; vector = rte->vector; dest_mode = rte->dest_mode; dest = rte->dest.logical.logical_dest; spin_lock_irqsave(lock, flags); offset = get_intremap_offset(vector, delivery_mode); entry = (u32*)get_intremap_entry(req_id, offset); update_intremap_entry(entry, vector, delivery_mode, dest_mode, dest); spin_unlock_irqrestore(lock, flags); if ( iommu->enabled ) { spin_lock_irqsave(&iommu->lock, flags); invalidate_interrupt_table(iommu, req_id); flush_command_buffer(iommu); spin_unlock_irqrestore(&iommu->lock, flags); } } } int __init amd_iommu_setup_ioapic_remapping(void) { struct IO_APIC_route_entry rte = {0}; unsigned long flags; u32* entry; int apic, pin; u8 delivery_mode, dest, vector, dest_mode; u16 bdf, req_id; struct amd_iommu *iommu; spinlock_t *lock; int offset; /* Read ioapic entries and update interrupt remapping table accordingly */ for ( apic = 0; apic < nr_ioapics; apic++ ) { for ( pin = 0; pin < nr_ioapic_registers[apic]; pin++ ) { *(((int *)&rte) + 1) = io_apic_read(apic, 0x11 + 2 * pin); *(((int *)&rte) + 0) = io_apic_read(apic, 0x10 + 2 * pin); if ( rte.mask == 1 ) continue; /* get device id of ioapic devices */ bdf = ioapic_bdf[IO_APIC_ID(apic)]; iommu = find_iommu_for_device(bdf); if ( !iommu ) { AMD_IOMMU_DEBUG( "Fail to find iommu for ioapic device id = 0x%x\n", bdf); continue; } req_id = get_intremap_requestor_id(bdf); lock = get_intremap_lock(req_id); delivery_mode = rte.delivery_mode; vector = rte.vector; dest_mode = rte.dest_mode; dest = rte.dest.logical.logical_dest; spin_lock_irqsave(lock, flags); offset = get_intremap_offset(vector, delivery_mode); entry = (u32*)get_intremap_entry(req_id, offset); update_intremap_entry(entry, vector, delivery_mode, dest_mode, dest); spin_unlock_irqrestore(lock, flags); if ( iommu->enabled ) { spin_lock_irqsave(&iommu->lock, flags); invalidate_interrupt_table(iommu, req_id);