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* c4 hdmiJames McKenzie2025-04-282-0/+544
* c4 hdmiJames McKenzie2025-04-288-209/+125
* tidyJames McKenzie2025-04-283-44/+44
* tidyJames McKenzie2025-04-282-37/+37
* cyclone4 first stepsJames McKenzie2025-04-2815-40/+743
* move vram to moduleJames McKenzie2025-04-285-2/+38
* tidyJames McKenzie2025-04-288-187/+188
* tidyJames McKenzie2025-04-289-228/+255
* finished input stageJames McKenzie2025-04-272-0/+941
* finished input stageJames McKenzie2025-04-279-675/+137
* tidyJames McKenzie2025-04-278-455/+457
* meets timingJames McKenzie2025-04-274-102/+74
* note quite workingJames McKenzie2025-04-273-25/+75
* note quite workingJames McKenzie2025-04-2710-96/+628
* after tidyJames McKenzie2025-04-2610-749/+563
* before tidyJames McKenzie2025-04-2614-109/+1481
* first cut at spartan 6 fpgaJames McKenzie2025-04-2615-763/+707
* fix aux channel polarityJames McKenzie2025-04-2520-2132/+2598
* add noddy cyclone IV fpga designJames McKenzie2025-04-2015-0/+1743
* fishJames McKenzie2025-04-18246-0/+519681
* tidy up after rebaseJames McKenzie2025-04-181-0/+2
* fishJames McKenzie2025-04-181-0/+66607
* add vertical timingsroot2025-04-1814-36/+131185
* fishJames McKenzie2025-04-161-0/+0
* fishJames McKenzie2025-04-1639-0/+0
* add lcsc part numbersJames McKenzie2025-04-162-4/+121
* schematicsJames McKenzie2025-04-163-0/+0
* fishroot2025-04-165-0/+3
* add submoduleJames McKenzie2025-04-162-0/+4
* tidy upJames McKenzie2025-04-1558-0/+207425
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-24 17:28:29 +0000