-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: vram_cyclone4_impl.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.all; entity vram_cyclone4_impl is port ( data : in std_logic_vector (1 downto 0); rdaddress : in std_logic_vector (17 downto 0); rdclock : in std_logic; wraddress : in std_logic_vector (17 downto 0); wrclock : in std_logic := '1'; wren : in std_logic := '0'; q : out std_logic_vector (1 downto 0) ); end vram_cyclone4_impl; architecture SYN of vram_cyclone4_impl is signal sub_wire0 : std_logic_vector (1 downto 0); component altsyncram generic ( address_aclr_b : string; address_reg_b : string; clock_enable_input_a : string; clock_enable_input_b : string; clock_enable_output_b : string; intended_device_family : string; lpm_type : string; numwords_a : natural; numwords_b : natural; operation_mode : string; outdata_aclr_b : string; outdata_reg_b : string; power_up_uninitialized : string; widthad_a : natural; widthad_b : natural; width_a : natural; width_b : natural; width_byteena_a : natural ); port ( address_a : in std_logic_vector (17 downto 0); clock0 : in std_logic; data_a : in std_logic_vector (1 downto 0); q_b : out std_logic_vector (1 downto 0); wren_a : in std_logic; address_b : in std_logic_vector (17 downto 0); clock1 : in std_logic ); end component; begin q <= sub_wire0(1 downto 0); altsyncram_component : altsyncram generic map ( address_aclr_b => "NONE", address_reg_b => "CLOCK1", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", intended_device_family => "Cyclone IV E", lpm_type => "altsyncram", numwords_a => 245760, numwords_b => 245760, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "UNREGISTERED", power_up_uninitialized => "FALSE", widthad_a => 18, widthad_b => 18, width_a => 2, width_b => 2, width_byteena_a => 1 ) port map ( address_a => wraddress, clock0 => wrclock, data_a => data, wren_a => wren, address_b => rdaddress, clock1 => rdclock, q_b => sub_wire0 ); end SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "1" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "456192" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "1" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "2" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "2" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "228096" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "228096" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "18" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "18" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "2" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]" -- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]" -- Retrieval info: USED_PORT: rdaddress 0 0 18 0 INPUT NODEFVAL "rdaddress[17..0]" -- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" -- Retrieval info: USED_PORT: wraddress 0 0 18 0 INPUT NODEFVAL "wraddress[17..0]" -- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" -- Retrieval info: CONNECT: @address_a 0 0 18 0 wraddress 0 0 18 0 -- Retrieval info: CONNECT: @address_b 0 0 18 0 rdaddress 0 0 18 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 -- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 2 0 @q_b 0 0 2 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vram_cyclone4_impl.vhd FALSE