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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2015-07-21 17:58:23 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2015-07-21 17:58:23 -0700 |
| commit | ae46690b066a55d591133f18f75b384abb4bc084 (patch) | |
| tree | 9c78cbf543b4bbcfa21bd190bfb0ef470fd04aa8 | |
| parent | 6f13e63182d95a66ca840ce83349fcb1099ced23 (diff) | |
| download | abc-ae46690b066a55d591133f18f75b384abb4bc084.tar.gz abc-ae46690b066a55d591133f18f75b384abb4bc084.tar.bz2 abc-ae46690b066a55d591133f18f75b384abb4bc084.zip | |
Renaming Cba into Bac.
| -rw-r--r-- | src/base/cba/cbaWriteVer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/base/cba/cbaWriteVer.c b/src/base/cba/cbaWriteVer.c index de99458a..58604eb1 100644 --- a/src/base/cba/cbaWriteVer.c +++ b/src/base/cba/cbaWriteVer.c @@ -64,7 +64,7 @@ static void Prs_ManWriteVerilogSignal( FILE * pFile, Prs_Ntk_t * p, int Sig ) Prs_ManWriteVerilogConcat( pFile, p, Value ); else assert( 0 ); } -static void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) +void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) { int i, Sig; assert( Vec_IntSize(vSigs) > 0 ); |