Adding switch &get -m to import mapped network into the &-space.

4 files changed, 141 insertions, 15 deletions

diff --git a/src/base/abc/abc.h b/src/base/abc/abc.h
index bb6bc3cb..2d3e7588 100644
--- a/src/base/abc/abc.h
+++ b/src/base/abc/abc.h
@@ -637,6 +637,7 @@ extern ABC_DLL void               Abc_NodeBddToCnf( Abc_Obj_t * pNode, Mem_Flex_
 extern ABC_DLL void               Abc_NtkLogicMakeDirectSops( Abc_Ntk_t * pNtk );
 extern ABC_DLL int                Abc_NtkSopToAig( Abc_Ntk_t * pNtk );
 extern ABC_DLL int                Abc_NtkAigToBdd( Abc_Ntk_t * pNtk );
+extern ABC_DLL Gia_Man_t *        Abc_NtkAigToGia( Abc_Ntk_t * p );
 extern ABC_DLL int                Abc_NtkMapToSop( Abc_Ntk_t * pNtk );
 extern ABC_DLL int                Abc_NtkToSop( Abc_Ntk_t * pNtk, int fDirect );
 extern ABC_DLL int                Abc_NtkToBdd( Abc_Ntk_t * pNtk );
diff --git a/src/base/abc/abcFunc.c b/src/base/abc/abcFunc.c
index 437c44fd..3df465f5 100644
--- a/src/base/abc/abcFunc.c
+++ b/src/base/abc/abcFunc.c
@@ -868,6 +868,118 @@ DdNode * Abc_ConvertAigToBdd( DdManager * dd, Hop_Obj_t * pRoot )
 
 
 
+/**Function*************************************************************
+
+  Synopsis    [Converts the network from AIG to GIA representation.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_ConvertAigToGia_rec1( Gia_Man_t * p, Hop_Obj_t * pObj )
+{
+    assert( !Hop_IsComplement(pObj) );
+    if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
+        return;
+    Abc_ConvertAigToGia_rec1( p, Hop_ObjFanin0(pObj) ); 
+    Abc_ConvertAigToGia_rec1( p, Hop_ObjFanin1(pObj) );
+    pObj->iData = Gia_ManAppendAnd2( p, Hop_ObjChild0CopyI(pObj), Hop_ObjChild1CopyI(pObj) );
+    assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
+    Hop_ObjSetMarkA( pObj );
+}
+void Abc_ConvertAigToGia_rec2( Hop_Obj_t * pObj )
+{
+    assert( !Hop_IsComplement(pObj) );
+    if ( !Hop_ObjIsNode(pObj) || !Hop_ObjIsMarkA(pObj) )
+        return;
+    Abc_ConvertAigToGia_rec2( Hop_ObjFanin0(pObj) ); 
+    Abc_ConvertAigToGia_rec2( Hop_ObjFanin1(pObj) );
+    assert( Hop_ObjIsMarkA(pObj) ); // loop detection
+    Hop_ObjClearMarkA( pObj );
+}
+int Abc_ConvertAigToGia( Gia_Man_t * p, Hop_Obj_t * pRoot )
+{
+    assert( !Hop_IsComplement(pRoot) );
+    if ( Hop_ObjIsConst1( pRoot ) )
+        return 1;
+    Abc_ConvertAigToGia_rec1( p, pRoot );
+    Abc_ConvertAigToGia_rec2( pRoot );
+    return pRoot->iData;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Converts the network from AIG to BDD representation.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Gia_Man_t * Abc_NtkAigToGia( Abc_Ntk_t * p )
+{
+    Gia_Man_t * pNew;
+    Hop_Man_t * pHopMan;
+    Hop_Obj_t * pHopObj;
+    Vec_Int_t * vMapping;
+    Vec_Ptr_t * vNodes;
+    Abc_Obj_t * pNode, * pFanin;
+    int i, k, nObjs;
+    assert( Abc_NtkIsAigLogic(p) );
+    pHopMan = (Hop_Man_t *)p->pManFunc;
+    // create new manager
+    pNew = Gia_ManStart( 10000 );
+    pNew->pName = Abc_UtilStrsav( Abc_NtkName(p) );
+    Abc_NtkCleanCopy( p );
+    Hop_ManConst1(pHopMan)->iData = 1;
+    // create primary inputs
+    Abc_NtkForEachCi( p, pNode, i )
+        pNode->iTemp = Gia_ManAppendCi(pNew);
+    // find the number of objects
+    nObjs = Abc_NtkCiNum(p) + Abc_NtkCoNum(p);
+    Abc_NtkForEachNode( p, pNode, i )
+        nObjs += 2 + Hop_DagSize( (Hop_Obj_t *)pNode->pData );
+    vMapping = Vec_IntStart( nObjs );
+    // iterate through nodes used in the mapping
+    vNodes = Abc_NtkDfs( p, 0 );
+    Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
+    {
+        Abc_ObjForEachFanin( pNode, pFanin, k )
+            Hop_ManPi(pHopMan, k)->iData = pFanin->iTemp;
+        pHopObj = Hop_Regular( (Hop_Obj_t *)pNode->pData );
+        if ( Hop_DagSize(pHopObj) > 0 )
+        {
+            assert( Abc_ObjFaninNum(pNode) <= Hop_ManPiNum(pHopMan) );
+            Abc_ConvertAigToGia( pNew, pHopObj );
+            if ( !Gia_ObjIsAnd(Gia_ManObj(pNew, Abc_Lit2Var(pHopObj->iData))) )
+                continue;
+            if ( Vec_IntEntry(vMapping, Abc_Lit2Var(pHopObj->iData)) )
+                continue;
+            Vec_IntWriteEntry( vMapping, Abc_Lit2Var(pHopObj->iData), Vec_IntSize(vMapping) );
+            Vec_IntPush( vMapping, Abc_ObjFaninNum(pNode) );
+            Abc_ObjForEachFanin( pNode, pFanin, k )
+                Vec_IntPush( vMapping, Abc_Lit2Var(pFanin->iTemp)  );
+            Vec_IntPush( vMapping, Abc_Lit2Var(pHopObj->iData) );
+        }
+        pNode->iTemp = Abc_LitNotCond( pHopObj->iData, Hop_IsComplement( (Hop_Obj_t *)pNode->pData ) );
+    }
+    Vec_PtrFree( vNodes );
+    // create primary outputs
+    Abc_NtkForEachCo( p, pNode, i )
+        Gia_ManAppendCo( pNew, Abc_ObjFanin0(pNode)->iTemp );
+    Gia_ManSetRegNum( pNew, Abc_NtkLatchNum(p) );
+    // finish mapping 
+    assert( Gia_ManObjNum(pNew) <= nObjs );
+    assert( pNew->vMapping == NULL );
+    pNew->vMapping = vMapping;
+    return pNew;
+}
+
 
 /**Function*************************************************************
 
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c
index 55872a52..b45fde8f 100644
--- a/src/base/abci/abc.c
+++ b/src/base/abci/abc.c
@@ -24991,12 +24991,15 @@ int Abc_CommandAbc9Get( Abc_Frame_t * pAbc, int argc, char ** argv )
     Aig_Man_t * pAig;
     Gia_Man_t * pGia, * pTemp;
     char * pInits;
-    int c, fNames = 0, fVerbose = 0;
+    int c, fMapped = 0, fNames = 0, fVerbose = 0;
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "nvh" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "mnvh" ) ) != EOF )
     {
         switch ( c )
         {
+        case 'm':
+            fMapped ^= 1;
+            break;
         case 'n':
             fNames ^= 1;
             break;
@@ -25014,17 +25017,26 @@ int Abc_CommandAbc9Get( Abc_Frame_t * pAbc, int argc, char ** argv )
     }
     if ( !Abc_NtkIsStrash( pAbc->pNtkCur ) )
     {
-        // derive comb GIA
-        pStrash = Abc_NtkStrash( pAbc->pNtkCur, 0, 1, 0 );
-        pAig = Abc_NtkToDar( pStrash, 0, 0 );
-        Abc_NtkDelete( pStrash );
-        pGia = Gia_ManFromAig( pAig );
-        Aig_ManStop( pAig );
-        // perform undc/zero
-        pInits = Abc_NtkCollectLatchValuesStr( pAbc->pNtkCur );
-        pGia = Gia_ManDupZeroUndc( pTemp = pGia, pInits, fVerbose );
-        Gia_ManStop( pTemp );
-        ABC_FREE( pInits );
+        if ( fMapped )
+        {
+            assert( Abc_NtkIsLogic(pAbc->pNtkCur) );
+            Abc_NtkToAig( pAbc->pNtkCur );
+            pGia = Abc_NtkAigToGia( pAbc->pNtkCur );
+        }
+        else
+        {
+            // derive comb GIA
+            pStrash = Abc_NtkStrash( pAbc->pNtkCur, 0, 1, 0 );
+            pAig = Abc_NtkToDar( pStrash, 0, 0 );
+            Abc_NtkDelete( pStrash );
+            pGia = Gia_ManFromAig( pAig );
+            Aig_ManStop( pAig );
+            // perform undc/zero
+            pInits = Abc_NtkCollectLatchValuesStr( pAbc->pNtkCur );
+            pGia = Gia_ManDupZeroUndc( pTemp = pGia, pInits, fVerbose );
+            Gia_ManStop( pTemp );
+            ABC_FREE( pInits );
+        }
     }
     else
     {
@@ -25045,10 +25057,11 @@ int Abc_CommandAbc9Get( Abc_Frame_t * pAbc, int argc, char ** argv )
     return 0;
 
 usage:
-    Abc_Print( -2, "usage: &get [-nvh] <file>\n" );
+    Abc_Print( -2, "usage: &get [-mnvh] <file>\n" );
     Abc_Print( -2, "\t         converts the current network into GIA and moves it to the &-space\n" );
     Abc_Print( -2, "\t         (if the network is a sequential logic network, normalizes the flops\n" );
     Abc_Print( -2, "\t         to have const-0 initial values, equivalent to \"undc; st; zero\")\n" );
+    Abc_Print( -2, "\t-m     : toggles preserving the current mapping [default = %s]\n", fMapped? "yes": "no" );
     Abc_Print( -2, "\t-n     : toggles saving CI/CO names of the AIG [default = %s]\n", fNames? "yes": "no" );
     Abc_Print( -2, "\t-v     : toggles additional verbose output [default = %s]\n", fVerbose? "yes": "no" );
     Abc_Print( -2, "\t-h     : print the command usage\n");
diff --git a/src/base/abci/abcDar.c b/src/base/abci/abcDar.c
index 04b104e5..4fbf7c70 100644
--- a/src/base/abci/abcDar.c
+++ b/src/base/abci/abcDar.c
@@ -777,7 +777,7 @@ Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p )
             printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
     }
     // remove const node if it is not used
-    if ( Abc_ObjFanoutNum(pConst0) == 0 )
+    if ( !Abc_ObjIsNone(pConst0) && Abc_ObjFanoutNum(pConst0) == 0 )
         Abc_NtkDeleteObj( pConst0 );
 
     assert( Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew) );