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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2010-11-01 01:35:04 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2010-11-01 01:35:04 -0700 |
| commit | 6130e39b18b5f53902e4eab14f6d5cdde5219563 (patch) | |
| tree | 0db0628479a1b750e9af1f66cb8379ebd0913d31 /src/aig/cgt/cgtDecide.c | |
| parent | f0e77f6797c0504b0da25a56152b707d3357f386 (diff) | |
| download | abc-6130e39b18b5f53902e4eab14f6d5cdde5219563.tar.gz abc-6130e39b18b5f53902e4eab14f6d5cdde5219563.tar.bz2 abc-6130e39b18b5f53902e4eab14f6d5cdde5219563.zip | |
initial commit of public abc
Diffstat (limited to 'src/aig/cgt/cgtDecide.c')
| -rw-r--r-- | src/aig/cgt/cgtDecide.c | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/src/aig/cgt/cgtDecide.c b/src/aig/cgt/cgtDecide.c index 3e79ff73..54a69e95 100644 --- a/src/aig/cgt/cgtDecide.c +++ b/src/aig/cgt/cgtDecide.c @@ -21,6 +21,9 @@ #include "cgtInt.h" #include "sswInt.h" +ABC_NAMESPACE_IMPL_START + + //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// @@ -96,11 +99,11 @@ int Cgt_ManCheckGateComplete( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, Aig_Obj_t Vec_Ptr_t * vGates; Aig_Obj_t * pObj; int i; - Vec_PtrForEachEntry( vFanout, pObj, i ) + Vec_PtrForEachEntry( Aig_Obj_t *, vFanout, pObj, i ) { if ( Saig_ObjIsPo(pAig, pObj) ) return 0; - vGates = Vec_VecEntry( vGatesAll, Aig_ObjPioNum(pObj) - Saig_ManPoNum(pAig) ); + vGates = (Vec_Ptr_t *)Vec_VecEntry( vGatesAll, Aig_ObjPioNum(pObj) - Saig_ManPoNum(pAig) ); if ( Vec_PtrFind( vGates, pGate ) == -1 ) return 0; } @@ -125,7 +128,7 @@ Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int n int i, k; vFanout = Vec_PtrAlloc( 100 ); vGatesFull = Vec_PtrAlloc( 100 ); - Vec_VecForEachEntry( vGatesAll, pGate, i, k ) + Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k ) { pGateR = Aig_Regular(pGate); if ( pGateR->fMarkA ) @@ -136,7 +139,7 @@ Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int n Vec_PtrPush( vGatesFull, pGate ); } Vec_PtrFree( vFanout ); - Vec_VecForEachEntry( vGatesAll, pGate, i, k ) + Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k ) Aig_Regular(pGate)->fMarkA = 0; return vGatesFull; } @@ -197,8 +200,8 @@ Vec_Vec_t * Cgt_ManDecideSimple( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nO { nHitsMax = 0; pCandBest = NULL; - vCands = Vec_VecEntry( vGatesAll, i ); - Vec_PtrForEachEntry( vCands, pCand, k ) + vCands = (Vec_Ptr_t *)Vec_VecEntry( vGatesAll, i ); + Vec_PtrForEachEntry( Aig_Obj_t *, vCands, pCand, k ) { // check if this is indeed a clock-gate if ( nOdcMax == 0 && !Ssw_SmlCheckXorImplication( pSml, pObjLi, pObjLo, pCand ) ) @@ -260,15 +263,15 @@ Vec_Vec_t * Cgt_ManDecideArea( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdc // derive and label complete gates vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose ); // label complete gates - Vec_PtrForEachEntry( vCompletes, pGate, i ) + Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i ) Aig_Regular(pGate)->fMarkA = 1; // select only complete gates vGates = Vec_VecStart( Saig_ManRegNum(pAig) ); - Vec_VecForEachEntry( vGatesAll, pGate, i, k ) + Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k ) if ( Aig_Regular(pGate)->fMarkA ) Vec_VecPush( vGates, i, pGate ); // unlabel complete gates - Vec_PtrForEachEntry( vCompletes, pGate, i ) + Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i ) Aig_Regular(pGate)->fMarkA = 0; // count the number of gated flops Vec_VecForEachLevel( vGates, vOne, i ) @@ -294,3 +297,5 @@ Vec_Vec_t * Cgt_ManDecideArea( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdc //////////////////////////////////////////////////////////////////////// +ABC_NAMESPACE_IMPL_END + |