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author | Alan Mishchenko <alanmi@berkeley.edu> | 2008-05-08 08:01:00 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2008-05-08 08:01:00 -0700 |
commit | e94ccfd3fb07d22ed426e0386ccf536e470744b7 (patch) | |
tree | 395b99b931beee0c3416a098cc647f9b6a5b3080 /src/aig/fra/fraClaus.c | |
parent | 6175fcb8026bae3db5b4280b655131322d7944da (diff) | |
download | abc-e94ccfd3fb07d22ed426e0386ccf536e470744b7.tar.gz abc-e94ccfd3fb07d22ed426e0386ccf536e470744b7.tar.bz2 abc-e94ccfd3fb07d22ed426e0386ccf536e470744b7.zip |
Version abc80508
Diffstat (limited to 'src/aig/fra/fraClaus.c')
-rw-r--r-- | src/aig/fra/fraClaus.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/aig/fra/fraClaus.c b/src/aig/fra/fraClaus.c index c9ea4907..6f0a2012 100644 --- a/src/aig/fra/fraClaus.c +++ b/src/aig/fra/fraClaus.c @@ -606,7 +606,8 @@ int Fra_ClausProcessClauses( Clu_Man_t * p, int fRefs ) // simulate the AIG clk = clock(); - srand( 0xAABBAABB ); +// srand( 0xAABBAABB ); + Aig_ManRandom(1); pSeq = Fra_SmlSimulateSeq( p->pAig, 0, p->nPref + p->nSimFrames, p->nSimWords/p->nSimFrames ); if ( p->fTarget && pSeq->fNonConstOut ) { @@ -661,7 +662,8 @@ PRT( "Infoseq", clock() - clk ); // perform combinational simulation clk = clock(); - srand( 0xAABBAABB ); +// srand( 0xAABBAABB ); + Aig_ManRandom(1); pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref ); if ( p->fVerbose ) { @@ -728,7 +730,8 @@ int Fra_ClausProcessClauses2( Clu_Man_t * p, int fRefs ) // simulate the AIG clk = clock(); - srand( 0xAABBAABB ); +// srand( 0xAABBAABB ); + Aig_ManRandom(1); pSeq = Fra_SmlSimulateSeq( p->pAig, 0, p->nPref + p->nSimFrames, p->nSimWords/p->nSimFrames ); if ( p->fTarget && pSeq->fNonConstOut ) { @@ -743,7 +746,8 @@ if ( p->fVerbose ) // perform combinational simulation clk = clock(); - srand( 0xAABBAABB ); +// srand( 0xAABBAABB ); + Aig_ManRandom(1); pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref ); if ( p->fVerbose ) { @@ -1614,7 +1618,8 @@ void Fra_ClausEstimateCoverage( Clu_Man_t * p ) int * pStart, * pVar2Id; int clk = clock(); // simulate the circuit with nCombSimWords * 32 = 64K patterns - srand( 0xAABBAABB ); +// srand( 0xAABBAABB ); + Aig_ManRandom(1); pComb = Fra_SmlSimulateComb( p->pAig, nCombSimWords ); // create mapping from SAT vars to node IDs pVar2Id = ALLOC( int, p->pCnf->nVars ); |